From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org, anjo@rev.ng
Subject: [PATCH v3 19/39] accel/tcg: Modify atomic_mmu_lookup() to use CPUState
Date: Sat, 16 Sep 2023 14:41:03 -0700 [thread overview]
Message-ID: <20230916214123.525796-20-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org>
From: Anton Johansson <anjo@rev.ng>
The goal is to (in the future) allow for per-target compilation of
functions in atomic_template.h whilst atomic_mmu_lookup() and cputlb.c
are compiled once-per user- or system mode.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230912153428.17816-7-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[rth: Use cpu->neg.tlb instead of cpu_tlb()]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/atomic_template.h | 20 ++++++++++++--------
accel/tcg/cputlb.c | 26 +++++++++++++-------------
accel/tcg/user-exec.c | 8 ++++----
3 files changed, 29 insertions(+), 25 deletions(-)
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index 84c08b1425..1dc2151daf 100644
--- a/accel/tcg/atomic_template.h
+++ b/accel/tcg/atomic_template.h
@@ -73,7 +73,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, abi_ptr addr,
ABI_TYPE cmpv, ABI_TYPE newv,
MemOpIdx oi, uintptr_t retaddr)
{
- DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr);
+ DATA_TYPE *haddr = atomic_mmu_lookup(env_cpu(env), addr, oi,
+ DATA_SIZE, retaddr);
DATA_TYPE ret;
#if DATA_SIZE == 16
@@ -90,7 +91,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, abi_ptr addr,
ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, abi_ptr addr, ABI_TYPE val,
MemOpIdx oi, uintptr_t retaddr)
{
- DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr);
+ DATA_TYPE *haddr = atomic_mmu_lookup(env_cpu(env), addr, oi,
+ DATA_SIZE, retaddr);
DATA_TYPE ret;
ret = qatomic_xchg__nocheck(haddr, val);
@@ -104,7 +106,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, abi_ptr addr, \
ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \
{ \
DATA_TYPE *haddr, ret; \
- haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \
+ haddr = atomic_mmu_lookup(env_cpu(env), addr, oi, DATA_SIZE, retaddr); \
ret = qatomic_##X(haddr, val); \
ATOMIC_MMU_CLEANUP; \
atomic_trace_rmw_post(env, addr, oi); \
@@ -135,7 +137,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, abi_ptr addr, \
ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \
{ \
XDATA_TYPE *haddr, cmp, old, new, val = xval; \
- haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \
+ haddr = atomic_mmu_lookup(env_cpu(env), addr, oi, DATA_SIZE, retaddr); \
smp_mb(); \
cmp = qatomic_read__nocheck(haddr); \
do { \
@@ -176,7 +178,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, abi_ptr addr,
ABI_TYPE cmpv, ABI_TYPE newv,
MemOpIdx oi, uintptr_t retaddr)
{
- DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr);
+ DATA_TYPE *haddr = atomic_mmu_lookup(env_cpu(env), addr, oi,
+ DATA_SIZE, retaddr);
DATA_TYPE ret;
#if DATA_SIZE == 16
@@ -193,7 +196,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, abi_ptr addr,
ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, abi_ptr addr, ABI_TYPE val,
MemOpIdx oi, uintptr_t retaddr)
{
- DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr);
+ DATA_TYPE *haddr = atomic_mmu_lookup(env_cpu(env), addr, oi,
+ DATA_SIZE, retaddr);
ABI_TYPE ret;
ret = qatomic_xchg__nocheck(haddr, BSWAP(val));
@@ -207,7 +211,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, abi_ptr addr, \
ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \
{ \
DATA_TYPE *haddr, ret; \
- haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \
+ haddr = atomic_mmu_lookup(env_cpu(env), addr, oi, DATA_SIZE, retaddr); \
ret = qatomic_##X(haddr, BSWAP(val)); \
ATOMIC_MMU_CLEANUP; \
atomic_trace_rmw_post(env, addr, oi); \
@@ -235,7 +239,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, abi_ptr addr, \
ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \
{ \
XDATA_TYPE *haddr, ldo, ldn, old, new, val = xval; \
- haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \
+ haddr = atomic_mmu_lookup(env_cpu(env), addr, oi, DATA_SIZE, retaddr); \
smp_mb(); \
ldn = qatomic_read__nocheck(haddr); \
do { \
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 0e4bc82294..3703443b5c 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1856,7 +1856,7 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi,
* Probe for an atomic operation. Do not allow unaligned operations,
* or io operations to proceed. Return the host address.
*/
-static void *atomic_mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi,
+static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi,
int size, uintptr_t retaddr)
{
uintptr_t mmu_idx = get_mmuidx(oi);
@@ -1876,7 +1876,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi,
/* Enforce guest required alignment. */
if (unlikely(a_bits > 0 && (addr & ((1 << a_bits) - 1)))) {
/* ??? Maybe indicate atomic op to cpu_unaligned_access */
- cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE,
+ cpu_unaligned_access(cpu, addr, MMU_DATA_STORE,
mmu_idx, retaddr);
}
@@ -1889,18 +1889,18 @@ static void *atomic_mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi,
goto stop_the_world;
}
- index = tlb_index(env_cpu(env), mmu_idx, addr);
- tlbe = tlb_entry(env_cpu(env), mmu_idx, addr);
+ index = tlb_index(cpu, mmu_idx, addr);
+ tlbe = tlb_entry(cpu, mmu_idx, addr);
/* Check TLB entry and enforce page permissions. */
tlb_addr = tlb_addr_write(tlbe);
if (!tlb_hit(tlb_addr, addr)) {
- if (!victim_tlb_hit(env_cpu(env), mmu_idx, index, MMU_DATA_STORE,
+ if (!victim_tlb_hit(cpu, mmu_idx, index, MMU_DATA_STORE,
addr & TARGET_PAGE_MASK)) {
- tlb_fill(env_cpu(env), addr, size,
+ tlb_fill(cpu, addr, size,
MMU_DATA_STORE, mmu_idx, retaddr);
- index = tlb_index(env_cpu(env), mmu_idx, addr);
- tlbe = tlb_entry(env_cpu(env), mmu_idx, addr);
+ index = tlb_index(cpu, mmu_idx, addr);
+ tlbe = tlb_entry(cpu, mmu_idx, addr);
}
tlb_addr = tlb_addr_write(tlbe) & ~TLB_INVALID_MASK;
}
@@ -1912,7 +1912,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi,
* but addr_read will only be -1 if PAGE_READ was unset.
*/
if (unlikely(tlbe->addr_read == -1)) {
- tlb_fill(env_cpu(env), addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
+ tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
/*
* Since we don't support reads and writes to different
* addresses, and we do have the proper page loaded for
@@ -1932,10 +1932,10 @@ static void *atomic_mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi,
}
hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
- full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
+ full = &cpu->neg.tlb.d[mmu_idx].fulltlb[index];
if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
- notdirty_write(env_cpu(env), addr, size, full, retaddr);
+ notdirty_write(cpu, addr, size, full, retaddr);
}
if (unlikely(tlb_addr & TLB_FORCE_SLOW)) {
@@ -1948,7 +1948,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi,
wp_flags |= BP_MEM_READ;
}
if (wp_flags) {
- cpu_check_watchpoint(env_cpu(env), addr, size,
+ cpu_check_watchpoint(cpu, addr, size,
full->attrs, wp_flags, retaddr);
}
}
@@ -1956,7 +1956,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi,
return hostaddr;
stop_the_world:
- cpu_loop_exit_atomic(env_cpu(env), retaddr);
+ cpu_loop_exit_atomic(cpu, retaddr);
}
/*
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index ab48cb41e4..d2daeafbab 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -1386,7 +1386,7 @@ uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr,
/*
* Do not allow unaligned operations to proceed. Return the host address.
*/
-static void *atomic_mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi,
+static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi,
int size, uintptr_t retaddr)
{
MemOp mop = get_memop(oi);
@@ -1395,15 +1395,15 @@ static void *atomic_mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi,
/* Enforce guest required alignment. */
if (unlikely(addr & ((1 << a_bits) - 1))) {
- cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_STORE, retaddr);
+ cpu_loop_exit_sigbus(cpu, addr, MMU_DATA_STORE, retaddr);
}
/* Enforce qemu required alignment. */
if (unlikely(addr & (size - 1))) {
- cpu_loop_exit_atomic(env_cpu(env), retaddr);
+ cpu_loop_exit_atomic(cpu, retaddr);
}
- ret = g2h(env_cpu(env), addr);
+ ret = g2h(cpu, addr);
set_helper_retaddr(retaddr);
return ret;
}
--
2.34.1
next prev parent reply other threads:[~2023-09-16 21:42 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-16 21:40 [PATCH v3 00/39] target agnostic cleanups Richard Henderson
2023-09-16 21:40 ` [PATCH v3 01/39] target/arm: Replace TARGET_PAGE_ENTRY_EXTRA Richard Henderson
2023-09-16 21:40 ` [PATCH v3 02/39] accel/tcg: Move CPUTLB definitions from cpu-defs.h Richard Henderson
2023-09-16 21:40 ` [PATCH v3 03/39] qom: Propagate alignment through type system Richard Henderson
2023-09-16 21:40 ` [PATCH v3 04/39] target/arm: Remove size and alignment for cpu subclasses Richard Henderson
2023-09-16 21:40 ` [PATCH v3 05/39] target/*: Add instance_align to all cpu base classes Richard Henderson
2023-09-16 21:40 ` [PATCH v3 06/39] accel/tcg: Validate placement of CPUNegativeOffsetState Richard Henderson
2023-09-16 21:40 ` [PATCH v3 07/39] accel/tcg: Move CPUNegativeOffsetState into CPUState Richard Henderson
2023-09-16 21:40 ` [PATCH v3 08/39] accel/tcg: Remove CPUState.icount_decr_ptr Richard Henderson
2023-09-16 21:40 ` [PATCH v3 09/39] accel/tcg: Move can_do_io to CPUNegativeOffsetState Richard Henderson
2023-09-16 21:40 ` [PATCH v3 10/39] accel/tcg: Remove cpu_neg() Richard Henderson
2023-09-16 21:40 ` [PATCH v3 11/39] tcg: Rename cpu_env to tcg_env Richard Henderson
2023-09-16 21:40 ` [PATCH v3 12/39] accel/tcg: Replace CPUState.env_ptr with cpu_env() Richard Henderson
2023-09-16 21:40 ` [PATCH v3 13/39] accel/tcg: Remove cpu_set_cpustate_pointers Richard Henderson
2023-09-16 21:40 ` [PATCH v3 14/39] accel/tcg: Remove env_neg() Richard Henderson
2023-09-19 9:40 ` Philippe Mathieu-Daudé
2023-09-16 21:40 ` [PATCH v3 15/39] tcg: Remove TCGContext.tlb_fast_offset Richard Henderson
2023-09-16 21:41 ` [PATCH v3 16/39] accel/tcg: Modify tlb_*() to use CPUState Richard Henderson
2023-09-19 9:39 ` Philippe Mathieu-Daudé
2023-09-16 21:41 ` [PATCH v3 17/39] accel/tcg: Modify probe_access_internal() " Richard Henderson
2023-09-16 21:41 ` [PATCH v3 18/39] accel/tcg: Modify memory access functions " Richard Henderson
2023-09-16 21:41 ` Richard Henderson [this message]
2023-09-16 21:41 ` [PATCH v3 20/39] accel/tcg: Use CPUState in atomicity helpers Richard Henderson
2023-09-16 21:41 ` [PATCH v3 21/39] accel/tcg: Remove env_tlb() Richard Henderson
2023-09-19 9:45 ` Philippe Mathieu-Daudé
2023-09-16 21:41 ` [PATCH v3 22/39] accel/tcg: Unify user and softmmu do_[st|ld]*_mmu() Richard Henderson
2023-09-16 21:41 ` [PATCH v3 23/39] accel/tcg: move ld/st helpers to ldst_common.c.inc Richard Henderson
2023-09-16 21:41 ` [PATCH v3 24/39] exec: Make EXCP_FOO definitions target agnostic Richard Henderson
2023-09-16 21:41 ` [PATCH v3 25/39] exec: Move cpu_loop_foo() target agnostic functions to 'cpu-common.h' Richard Henderson
2023-09-16 21:41 ` [PATCH v3 26/39] accel/tcg: Restrict dump_exec_info() declaration Richard Henderson
2023-09-16 21:41 ` [PATCH v3 27/39] accel: Make accel-blocker.o target agnostic Richard Henderson
2023-09-16 21:41 ` [PATCH v3 28/39] accel: Rename accel-common.c -> accel-target.c Richard Henderson
2023-09-16 21:41 ` [PATCH v3 29/39] exec: Rename cpu.c -> cpu-target.c Richard Henderson
2023-09-16 21:41 ` [PATCH v3 30/39] exec: Rename target specific page-vary.c -> page-vary-target.c Richard Henderson
2023-09-16 21:41 ` [PATCH v3 31/39] accel/tcg: Rename target-specific 'internal.h' -> 'internal-target.h' Richard Henderson
2023-09-16 21:41 ` [PATCH v3 32/39] accel/tcg: Make monitor.c a target-agnostic unit Richard Henderson
2023-09-16 21:41 ` [PATCH v3 33/39] accel/tcg: Make icount.o a target agnostic unit Richard Henderson
2023-09-16 21:41 ` [PATCH v3 34/39] accel/tcg: Make cpu-exec-common.c " Richard Henderson
2023-09-16 21:41 ` [PATCH v3 35/39] accel: Rename accel_cpu_realizefn() -> accel_cpu_realize() Richard Henderson
2023-09-16 21:41 ` [PATCH v3 36/39] accel: Introduce accel_cpu_unrealize() stub Richard Henderson
2023-09-18 8:12 ` Philippe Mathieu-Daudé
2023-09-16 21:41 ` [PATCH v3 37/39] accel: Declare AccelClass::[un]realize_cpu() handlers Richard Henderson
2023-09-16 21:41 ` [PATCH v3 38/39] accel/tcg: Have tcg_exec_realizefn() return a boolean Richard Henderson
2023-09-16 21:41 ` [PATCH v3 39/39] accel/tcg: Restrict tcg_exec_[un]realizefn() to TCG Richard Henderson
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