From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: git@xen0n.name, c@jia.je, gaosong@loongson.cn, yangxiaojuan@loongson.cn
Subject: [PATCH 4/7] tcg/loongarch64: Use cpuinfo.h
Date: Sat, 16 Sep 2023 15:01:48 -0700 [thread overview]
Message-ID: <20230916220151.526140-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230916220151.526140-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.h | 8 ++++----
tcg/loongarch64/tcg-target.c.inc | 8 +-------
2 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 03017672f6..1bea15b02e 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -29,6 +29,8 @@
#ifndef LOONGARCH_TCG_TARGET_H
#define LOONGARCH_TCG_TARGET_H
+#include "host/cpuinfo.h"
+
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_NB_REGS 64
@@ -85,8 +87,6 @@ typedef enum {
TCG_VEC_TMP0 = TCG_REG_V23,
} TCGReg;
-extern bool use_lsx_instructions;
-
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_SP
#define TCG_TARGET_STACK_ALIGN 16
@@ -171,10 +171,10 @@ extern bool use_lsx_instructions;
#define TCG_TARGET_HAS_muluh_i64 1
#define TCG_TARGET_HAS_mulsh_i64 1
-#define TCG_TARGET_HAS_qemu_ldst_i128 use_lsx_instructions
+#define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_LSX)
#define TCG_TARGET_HAS_v64 0
-#define TCG_TARGET_HAS_v128 use_lsx_instructions
+#define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_LSX)
#define TCG_TARGET_HAS_v256 0
#define TCG_TARGET_HAS_not_vec 1
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 40074c46b8..52f2c26ce1 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -32,8 +32,6 @@
#include "../tcg-ldst.c.inc"
#include <asm/hwcap.h>
-bool use_lsx_instructions;
-
#ifdef CONFIG_DEBUG_TCG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"zero",
@@ -2316,10 +2314,6 @@ static void tcg_target_init(TCGContext *s)
exit(EXIT_FAILURE);
}
- if (hwcap & HWCAP_LOONGARCH_LSX) {
- use_lsx_instructions = 1;
- }
-
tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
@@ -2335,7 +2329,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
- if (use_lsx_instructions) {
+ if (cpuinfo & CPUINFO_LSX) {
tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25);
--
2.34.1
next prev parent reply other threads:[~2023-09-16 22:02 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-16 22:01 [PATCH 0/7] tcg/loongarch64: Improvements for 128-bit load/store Richard Henderson
2023-09-16 22:01 ` [PATCH 1/7] tcg: Add C_N2_I1 Richard Henderson
2023-09-30 11:39 ` Jiajie Chen
2023-09-16 22:01 ` [PATCH 2/7] tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128 Richard Henderson
2023-09-30 11:39 ` Jiajie Chen
2023-09-16 22:01 ` [PATCH 3/7] util: Add cpuinfo for loongarch64 Richard Henderson
2023-09-30 11:40 ` Jiajie Chen
2023-09-16 22:01 ` Richard Henderson [this message]
2023-09-30 11:41 ` [PATCH 4/7] tcg/loongarch64: Use cpuinfo.h Jiajie Chen
2023-09-16 22:01 ` [PATCH 5/7] host/include/loongarch64: Add atomic16 load and store Richard Henderson
2023-09-16 22:01 ` [PATCH 6/7] accel/tcg: Remove redundant case in store_atom_16 Richard Henderson
2023-09-16 22:01 ` [PATCH 7/7] accel/tcg: Fix condition for store_atom_insert_al16 Richard Henderson
2023-09-30 2:13 ` [PATCH 0/7] tcg/loongarch64: Improvements for 128-bit load/store Richard Henderson
2023-09-30 19:04 ` WANG Xuerui
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