[PATCH 0/3] hw/cxl: Misc small fixes

[PATCH 0/3] hw/cxl: Misc small fixes

[Jonathan Cameron via]

Misc set of trivial fixes.  No conflicts with other sets outstanding
so can go with main CXL patches or perhaps via the trivial tree.

Dmitry Frolov (1):
  hw/cxl: Fix out of bound array access

Jonathan Cameron (2):
  hw/mem/cxl_type3: Add missing copyright and license notice
  docs/cxl: Cleanout some more aarch64 examples.

 docs/system/devices/cxl.rst | 4 ++--
 include/hw/cxl/cxl.h        | 2 +-
 hw/mem/cxl_type3.c          | 9 +++++++++
 3 files changed, 12 insertions(+), 3 deletions(-)

-- 
2.39.2

[PATCH 1/3] hw/cxl: Fix out of bound array access

[Jonathan Cameron via]

From: Dmitry Frolov <frolov@swemel.ru>

According to cxl_interleave_ways_enc(), fw->num_targets is allowed to be up
to 16. This also corresponds to CXL r3.0 spec. So, the fw->target_hbs[]
array is iterated from 0 to 15. But it is staticaly declared of length 8.
Thus, out of bound array access may occur.

Fixes: c28db9e000 ("hw/pci-bridge: Make PCIe and CXL PXB Devices inherit from TYPE_PXB_DEV")
Signed-off-by: Dmitry Frolov <frolov@swemel.ru>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Link: https://lore.kernel.org/r/20230913101055.754709-1-frolov@swemel.ru
Cc: qemu-stable@nongnu.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 include/hw/cxl/cxl.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
index 56c9e7676e..4944725849 100644
--- a/include/hw/cxl/cxl.h
+++ b/include/hw/cxl/cxl.h
@@ -29,7 +29,7 @@ typedef struct PXBCXLDev PXBCXLDev;
 typedef struct CXLFixedWindow {
     uint64_t size;
     char **targets;
-    PXBCXLDev *target_hbs[8];
+    PXBCXLDev *target_hbs[16];
     uint8_t num_targets;
     uint8_t enc_int_ways;
     uint8_t enc_int_gran;
-- 
2.39.2

Re: [PATCH 1/3] hw/cxl: Fix out of bound array access

[Fan Ni]

On Mon, Sep 18, 2023 at 04:02:57PM +0100, Jonathan Cameron wrote:

> From: Dmitry Frolov <frolov@swemel.ru>
> 
> According to cxl_interleave_ways_enc(), fw->num_targets is allowed to be up
> to 16. This also corresponds to CXL r3.0 spec. So, the fw->target_hbs[]
> array is iterated from 0 to 15. But it is staticaly declared of length 8.

s/staticaly/statically/

Fan
> Thus, out of bound array access may occur.
> 
> Fixes: c28db9e000 ("hw/pci-bridge: Make PCIe and CXL PXB Devices inherit from TYPE_PXB_DEV")
> Signed-off-by: Dmitry Frolov <frolov@swemel.ru>
> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
> Link: https://urldefense.com/v3/__https://lore.kernel.org/r/20230913101055.754709-1-frolov@swemel.ru__;!!EwVzqGoTKBqv-0DWAJBm!RYOYJeMCX_mlzCETIKjHDYun2TZCQxC7wF1SxIdUwJ3BYbDOtmDpTaVXXiQgiFwLYI_4JAnU6Asem4T0aHKzwzPJWer7$ 
> Cc: qemu-stable@nongnu.org
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  include/hw/cxl/cxl.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
> index 56c9e7676e..4944725849 100644
> --- a/include/hw/cxl/cxl.h
> +++ b/include/hw/cxl/cxl.h
> @@ -29,7 +29,7 @@ typedef struct PXBCXLDev PXBCXLDev;
>  typedef struct CXLFixedWindow {
>      uint64_t size;
>      char **targets;
> -    PXBCXLDev *target_hbs[8];
> +    PXBCXLDev *target_hbs[16];
>      uint8_t num_targets;
>      uint8_t enc_int_ways;
>      uint8_t enc_int_gran;
> -- 
> 2.39.2
> 

[PATCH 2/3] hw/mem/cxl_type3: Add missing copyright and license notice

[Jonathan Cameron via]

This has been missing from the start. Assume it should match
with cxl/cxl-component-utils.c as both were part of early
postings from Ben.

Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 hw/mem/cxl_type3.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index c5855d4e7d..ad3f0f6a9d 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -1,3 +1,12 @@
+/*
+ * CXL Type 3 (memory expander) device
+ *
+ * Copyright(C) 2020 Intel Corporation.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See the
+ * COPYING file in the top-level directory.
+ */
+
 #include "qemu/osdep.h"
 #include "qemu/units.h"
 #include "qemu/error-report.h"
-- 
2.39.2

Re: [PATCH 2/3] hw/mem/cxl_type3: Add missing copyright and license notice

[Fan Ni]

On Mon, Sep 18, 2023 at 04:02:58PM +0100, Jonathan Cameron wrote:

> This has been missing from the start. Assume it should match
> with cxl/cxl-component-utils.c as both were part of early
> postings from Ben.
> 
> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---

Reviewed-by: Fan Ni <fan.ni@samsung.com>

>  hw/mem/cxl_type3.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index c5855d4e7d..ad3f0f6a9d 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1,3 +1,12 @@
> +/*
> + * CXL Type 3 (memory expander) device
> + *
> + * Copyright(C) 2020 Intel Corporation.
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2. See the
> + * COPYING file in the top-level directory.
> + */
> +
>  #include "qemu/osdep.h"
>  #include "qemu/units.h"
>  #include "qemu/error-report.h"
> -- 
> 2.39.2
> 

Re: [PATCH 2/3] hw/mem/cxl_type3: Add missing copyright and license notice

[Peter Maydell]

On Mon, 18 Sept 2023 at 16:04, Jonathan Cameron
<Jonathan.Cameron@huawei.com> wrote:
>
> This has been missing from the start. Assume it should match
> with cxl/cxl-component-utils.c as both were part of early
> postings from Ben.

Sounds plausible -- is there an Intel person who could give us
an acked-by for this?

(Ideally we wouldn't have let more gpl-2-only code into the
codebase without a rationale...)

> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  hw/mem/cxl_type3.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index c5855d4e7d..ad3f0f6a9d 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1,3 +1,12 @@
> +/*
> + * CXL Type 3 (memory expander) device
> + *
> + * Copyright(C) 2020 Intel Corporation.
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2. See the
> + * COPYING file in the top-level directory.
> + */
> +
>  #include "qemu/osdep.h"
>  #include "qemu/units.h"
>  #include "qemu/error-report.h"

-- PMM

Re: [PATCH 2/3] hw/mem/cxl_type3: Add missing copyright and license notice

[Jonathan Cameron via]

On Mon, 18 Sep 2023 17:31:38 +0100
Peter Maydell <peter.maydell@linaro.org> wrote:

> On Mon, 18 Sept 2023 at 16:04, Jonathan Cameron
> <Jonathan.Cameron@huawei.com> wrote:
> >
> > This has been missing from the start. Assume it should match
> > with cxl/cxl-component-utils.c as both were part of early
> > postings from Ben.  
> 
> Sounds plausible -- is there an Intel person who could give us
> an acked-by for this?
> 
> (Ideally we wouldn't have let more gpl-2-only code into the
> codebase without a rationale...)
> 

I've +CC'd the kernel CXL maintainers from Intel a few of whom
have also contributed some of the QEMU CXL code.
Hopefully someone can ack.

> > Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > ---
> >  hw/mem/cxl_type3.c | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> > index c5855d4e7d..ad3f0f6a9d 100644
> > --- a/hw/mem/cxl_type3.c
> > +++ b/hw/mem/cxl_type3.c
> > @@ -1,3 +1,12 @@
> > +/*
> > + * CXL Type 3 (memory expander) device
> > + *
> > + * Copyright(C) 2020 Intel Corporation.
> > + *
> > + * This work is licensed under the terms of the GNU GPL, version 2. See the
> > + * COPYING file in the top-level directory.
> > + */
> > +
> >  #include "qemu/osdep.h"
> >  #include "qemu/units.h"
> >  #include "qemu/error-report.h"  
> 
> -- PMM
> 

Re: [PATCH 2/3] hw/mem/cxl_type3: Add missing copyright and license notice

[Dave Jiang]

On 9/18/23 10:00, Jonathan Cameron wrote:
> On Mon, 18 Sep 2023 17:31:38 +0100
> Peter Maydell <peter.maydell@linaro.org> wrote:
> 
>> On Mon, 18 Sept 2023 at 16:04, Jonathan Cameron
>> <Jonathan.Cameron@huawei.com> wrote:
>>>
>>> This has been missing from the start. Assume it should match
>>> with cxl/cxl-component-utils.c as both were part of early
>>> postings from Ben.  
>>
>> Sounds plausible -- is there an Intel person who could give us
>> an acked-by for this?
>>
>> (Ideally we wouldn't have let more gpl-2-only code into the
>> codebase without a rationale...)
>>
> 
> I've +CC'd the kernel CXL maintainers from Intel a few of whom
> have also contributed some of the QEMU CXL code.
> Hopefully someone can ack.

I see that nvdimm.c from Intel is under LGPL 2.1. What is the typical license this should be applied for QEMU?

> 
>>> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>>> ---
>>>  hw/mem/cxl_type3.c | 9 +++++++++
>>>  1 file changed, 9 insertions(+)
>>>
>>> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
>>> index c5855d4e7d..ad3f0f6a9d 100644
>>> --- a/hw/mem/cxl_type3.c
>>> +++ b/hw/mem/cxl_type3.c
>>> @@ -1,3 +1,12 @@
>>> +/*
>>> + * CXL Type 3 (memory expander) device
>>> + *
>>> + * Copyright(C) 2020 Intel Corporation.
>>> + *
>>> + * This work is licensed under the terms of the GNU GPL, version 2. See the
>>> + * COPYING file in the top-level directory.
>>> + */
>>> +
>>>  #include "qemu/osdep.h"
>>>  #include "qemu/units.h"
>>>  #include "qemu/error-report.h"  
>>
>> -- PMM
>>
> 

Re: [PATCH 2/3] hw/mem/cxl_type3: Add missing copyright and license notice

[Peter Maydell]

On Mon, 18 Sept 2023 at 18:26, Dave Jiang <dave.jiang@intel.com> wrote:
>
>
>
> On 9/18/23 10:00, Jonathan Cameron wrote:
> > On Mon, 18 Sep 2023 17:31:38 +0100
> > Peter Maydell <peter.maydell@linaro.org> wrote:
> >
> >> On Mon, 18 Sept 2023 at 16:04, Jonathan Cameron
> >> <Jonathan.Cameron@huawei.com> wrote:
> >>>
> >>> This has been missing from the start. Assume it should match
> >>> with cxl/cxl-component-utils.c as both were part of early
> >>> postings from Ben.
> >>
> >> Sounds plausible -- is there an Intel person who could give us
> >> an acked-by for this?
> >>
> >> (Ideally we wouldn't have let more gpl-2-only code into the
> >> codebase without a rationale...)
> >>
> >
> > I've +CC'd the kernel CXL maintainers from Intel a few of whom
> > have also contributed some of the QEMU CXL code.
> > Hopefully someone can ack.
>
> I see that nvdimm.c from Intel is under LGPL 2.1. What is the typical license this should be applied for QEMU?

The project has a mix of licenses, for mostly historical reasons.
The overall license is thus GPLv2 (as the most-restrictive of the set).
Our preference (as noted in the top level LICENSE file) for new
code is for GPL-v2-or-later; we can take other GPL-2-compatible
licenses (preferably GPL-v2-or-later compatible) if there's a
good rationale from the submitter. (Historically, one reason
for the GPL-v2-only code has been "this came from the Linux
kernel and so it's GPL-2-only"; "we copied a lot of this code
from some other file in QEMU and that has license X" is
the other one.)

thanks
-- PMM

Re: [PATCH 2/3] hw/mem/cxl_type3: Add missing copyright and license notice

[Jonathan Cameron via]

On Mon, 18 Sep 2023 18:38:10 +0100
Peter Maydell <peter.maydell@linaro.org> wrote:

> On Mon, 18 Sept 2023 at 18:26, Dave Jiang <dave.jiang@intel.com> wrote:
> >
> >
> >
> > On 9/18/23 10:00, Jonathan Cameron wrote:  
> > > On Mon, 18 Sep 2023 17:31:38 +0100
> > > Peter Maydell <peter.maydell@linaro.org> wrote:
> > >  
> > >> On Mon, 18 Sept 2023 at 16:04, Jonathan Cameron
> > >> <Jonathan.Cameron@huawei.com> wrote:  
> > >>>
> > >>> This has been missing from the start. Assume it should match
> > >>> with cxl/cxl-component-utils.c as both were part of early
> > >>> postings from Ben.  
> > >>
> > >> Sounds plausible -- is there an Intel person who could give us
> > >> an acked-by for this?
> > >>
> > >> (Ideally we wouldn't have let more gpl-2-only code into the
> > >> codebase without a rationale...)
> > >>  
> > >
> > > I've +CC'd the kernel CXL maintainers from Intel a few of whom
> > > have also contributed some of the QEMU CXL code.
> > > Hopefully someone can ack.  
> >
> > I see that nvdimm.c from Intel is under LGPL 2.1. What is the typical license this should be applied for QEMU?  
> 
> The project has a mix of licenses, for mostly historical reasons.
> The overall license is thus GPLv2 (as the most-restrictive of the set).
> Our preference (as noted in the top level LICENSE file) for new
> code is for GPL-v2-or-later; we can take other GPL-2-compatible
> licenses (preferably GPL-v2-or-later compatible) if there's a
> good rationale from the submitter. (Historically, one reason
> for the GPL-v2-only code has been "this came from the Linux
> kernel and so it's GPL-2-only"; "we copied a lot of this code
> from some other file in QEMU and that has license X" is
> the other one.)

As this one is now 'historical' code I'll stick to the v2 only
but make sure anything new goes in with v2 or later unless there is
a good reason for another choice.

Thanks for the info,

Jonathan

> 
> thanks
> -- PMM
> 

Re: [PATCH 2/3] hw/mem/cxl_type3: Add missing copyright and license notice

[Dave Jiang]

On 9/18/23 10:00, Jonathan Cameron wrote:
> On Mon, 18 Sep 2023 17:31:38 +0100
> Peter Maydell <peter.maydell@linaro.org> wrote:
> 
>> On Mon, 18 Sept 2023 at 16:04, Jonathan Cameron
>> <Jonathan.Cameron@huawei.com> wrote:
>>>
>>> This has been missing from the start. Assume it should match
>>> with cxl/cxl-component-utils.c as both were part of early
>>> postings from Ben.  
>>
>> Sounds plausible -- is there an Intel person who could give us
>> an acked-by for this?
>>
>> (Ideally we wouldn't have let more gpl-2-only code into the
>> codebase without a rationale...)
>>
> 
> I've +CC'd the kernel CXL maintainers from Intel a few of whom
> have also contributed some of the QEMU CXL code.
> Hopefully someone can ack.
> 
>>> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Acked-by: Dave Jiang <dave.jiang@intel.com>

>>> ---
>>>  hw/mem/cxl_type3.c | 9 +++++++++
>>>  1 file changed, 9 insertions(+)
>>>
>>> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
>>> index c5855d4e7d..ad3f0f6a9d 100644
>>> --- a/hw/mem/cxl_type3.c
>>> +++ b/hw/mem/cxl_type3.c
>>> @@ -1,3 +1,12 @@
>>> +/*
>>> + * CXL Type 3 (memory expander) device
>>> + *
>>> + * Copyright(C) 2020 Intel Corporation.
>>> + *
>>> + * This work is licensed under the terms of the GNU GPL, version 2. See the
>>> + * COPYING file in the top-level directory.
>>> + */
>>> +
>>>  #include "qemu/osdep.h"
>>>  #include "qemu/units.h"
>>>  #include "qemu/error-report.h"  
>>
>> -- PMM
>>
> 

Re: [PATCH 2/3] hw/mem/cxl_type3: Add missing copyright and license notice

[Ira Weiny]

Jonathan Cameron wrote:
> On Mon, 18 Sep 2023 17:31:38 +0100
> Peter Maydell <peter.maydell@linaro.org> wrote:
> 
> > On Mon, 18 Sept 2023 at 16:04, Jonathan Cameron
> > <Jonathan.Cameron@huawei.com> wrote:
> > >
> > > This has been missing from the start. Assume it should match
> > > with cxl/cxl-component-utils.c as both were part of early
> > > postings from Ben.  
> > 
> > Sounds plausible -- is there an Intel person who could give us
> > an acked-by for this?

While we are at it; what about .../hw/mem/cxl_type3_stubs.c?

> > 
> > (Ideally we wouldn't have let more gpl-2-only code into the
> > codebase without a rationale...)

I'm curious about this statement.  Does the qemu project not want gpl v2
only code?  I agree with Jonathan that this is the intention of Ben's
initial submission; so from that PoV.

Acked-by: Ira Weiny <ira.weiny@intel.com>

Going forward I'd like to better understand the qemu communities view.

Thanks,
Ira

> > 
> 
> I've +CC'd the kernel CXL maintainers from Intel a few of whom
> have also contributed some of the QEMU CXL code.
> Hopefully someone can ack.
> 
> > > Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> > > ---
> > >  hw/mem/cxl_type3.c | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > >
> > > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> > > index c5855d4e7d..ad3f0f6a9d 100644
> > > --- a/hw/mem/cxl_type3.c
> > > +++ b/hw/mem/cxl_type3.c
> > > @@ -1,3 +1,12 @@
> > > +/*
> > > + * CXL Type 3 (memory expander) device
> > > + *
> > > + * Copyright(C) 2020 Intel Corporation.
> > > + *
> > > + * This work is licensed under the terms of the GNU GPL, version 2. See the
> > > + * COPYING file in the top-level directory.
> > > + */
> > > +
> > >  #include "qemu/osdep.h"
> > >  #include "qemu/units.h"
> > >  #include "qemu/error-report.h"  
> > 
> > -- PMM
> > 
> 

Re: [PATCH 2/3] hw/mem/cxl_type3: Add missing copyright and license notice

[Daniel P. Berrangé]

On Mon, Sep 18, 2023 at 02:14:40PM -0700, Ira Weiny wrote:
> Jonathan Cameron wrote:
> > On Mon, 18 Sep 2023 17:31:38 +0100
> > Peter Maydell <peter.maydell@linaro.org> wrote:
> > 
> > > On Mon, 18 Sept 2023 at 16:04, Jonathan Cameron
> > > <Jonathan.Cameron@huawei.com> wrote:
> > > >
> > > > This has been missing from the start. Assume it should match
> > > > with cxl/cxl-component-utils.c as both were part of early
> > > > postings from Ben.  
> > > 
> > > Sounds plausible -- is there an Intel person who could give us
> > > an acked-by for this?
> 
> While we are at it; what about .../hw/mem/cxl_type3_stubs.c?
> 
> > > 
> > > (Ideally we wouldn't have let more gpl-2-only code into the
> > > codebase without a rationale...)
> 
> I'm curious about this statement.  Does the qemu project not want gpl v2
> only code?

Correct, this is explicitly stated in the LICENSE file:

[quote]
As of July 2013, contributions under version 2 of the GNU General Public
License (and no later version) are only accepted for the following files
or directories: bsd-user/, linux-user/, hw/vfio/, hw/xen/xen_pt*.
[/quote]

>             I agree with Jonathan that this is the intention of Ben's
> initial submission; so from that PoV.

Ideally we would get all QEMU CXL contributors to agree to re-license
to the GPL-2.0-or-later, unless the code has been copied from another
project which was GPL-2.0-only thus forcing our code.

> 
> Acked-by: Ira Weiny <ira.weiny@intel.com>
> 
> Going forward I'd like to better understand the qemu communities view.

Please follow the LICENSE file which is explicit about QEMU's views
per the quoted text above.

With regards,
Daniel
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Re: [PATCH 2/3] hw/mem/cxl_type3: Add missing copyright and license notice

[Jonathan Cameron via]

On Tue, 19 Sep 2023 09:47:06 +0100
Daniel P. Berrangé <berrange@redhat.com> wrote:

> On Mon, Sep 18, 2023 at 02:14:40PM -0700, Ira Weiny wrote:
> > Jonathan Cameron wrote:  
> > > On Mon, 18 Sep 2023 17:31:38 +0100
> > > Peter Maydell <peter.maydell@linaro.org> wrote:
> > >   
> > > > On Mon, 18 Sept 2023 at 16:04, Jonathan Cameron
> > > > <Jonathan.Cameron@huawei.com> wrote:  
> > > > >
> > > > > This has been missing from the start. Assume it should match
> > > > > with cxl/cxl-component-utils.c as both were part of early
> > > > > postings from Ben.    
> > > > 
> > > > Sounds plausible -- is there an Intel person who could give us
> > > > an acked-by for this?  
> > 
> > While we are at it; what about .../hw/mem/cxl_type3_stubs.c?
> >   
> > > > 
> > > > (Ideally we wouldn't have let more gpl-2-only code into the
> > > > codebase without a rationale...)  
> > 
> > I'm curious about this statement.  Does the qemu project not want gpl v2
> > only code?  
> 
> Correct, this is explicitly stated in the LICENSE file:
> 
> [quote]
> As of July 2013, contributions under version 2 of the GNU General Public
> License (and no later version) are only accepted for the following files
> or directories: bsd-user/, linux-user/, hw/vfio/, hw/xen/xen_pt*.
> [/quote]
> 
> >             I agree with Jonathan that this is the intention of Ben's
> > initial submission; so from that PoV.  
> 
> Ideally we would get all QEMU CXL contributors to agree to re-license
> to the GPL-2.0-or-later, unless the code has been copied from another
> project which was GPL-2.0-only thus forcing our code.
> 
> > 
> > Acked-by: Ira Weiny <ira.weiny@intel.com>
> > 
> > Going forward I'd like to better understand the qemu communities view.  
> 
> Please follow the LICENSE file which is explicit about QEMU's views
> per the quoted text above.

I'd be fine with relaxing these, but there are quite a few contributors
so it will be a little difficult to establish.

Given, for that to be useful we need to do all the CXL files, I'll post
a v2 of this series setting this to GPL-v2-only and we can see if we
can address relicencing at a later date.

> 
> With regards,
> Daniel

Re: [PATCH 2/3] hw/mem/cxl_type3: Add missing copyright and license notice

[Warner Losh]

[-- Attachment #1: Type: text/plain, Size: 1159 bytes --]

On Mon, Sep 18, 2023 at 4:04 PM Jonathan Cameron via <qemu-devel@nongnu.org>
wrote:

> This has been missing from the start. Assume it should match
> with cxl/cxl-component-utils.c as both were part of early
> postings from Ben.
>
> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  hw/mem/cxl_type3.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index c5855d4e7d..ad3f0f6a9d 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -1,3 +1,12 @@
> +/*
> + * CXL Type 3 (memory expander) device
> + *
> + * Copyright(C) 2020 Intel Corporation.
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2. See
> the
> + * COPYING file in the top-level directory.
> + */
>

SPDX-License-Identifier: GPL-v2-only

while you're at it (plus a +1 on the other concerns in the thread, though
I'll let
that play out elsewhere).

Warner


> +
>  #include "qemu/osdep.h"
>  #include "qemu/units.h"
>  #include "qemu/error-report.h"
> --
> 2.39.2
>
>
>

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[PATCH 3/3] docs/cxl: Cleanout some more aarch64 examples.

[Jonathan Cameron via]

These crossed with the previous fix to get rid of examples
using aarch64 for which support is not yet upstream.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 docs/system/devices/cxl.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index b742120657..6ab5f72473 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -313,7 +313,7 @@ A very simple setup with just one directly attached CXL Type 3 Persistent Memory
 
 A very simple setup with just one directly attached CXL Type 3 Volatile Memory device::
 
-  qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \
+  qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \
   ...
   -object memory-backend-ram,id=vmem0,share=on,size=256M \
   -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \
@@ -323,7 +323,7 @@ A very simple setup with just one directly attached CXL Type 3 Volatile Memory d
 
 The same volatile setup may optionally include an LSA region::
 
-  qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \
+  qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \
   ...
   -object memory-backend-ram,id=vmem0,share=on,size=256M \
   -object memory-backend-file,id=cxl-lsa0,share=on,mem-path=/tmp/lsa.raw,size=256M \
-- 
2.39.2

Re: [PATCH 3/3] docs/cxl: Cleanout some more aarch64 examples.

[Fan Ni]

On Mon, Sep 18, 2023 at 04:02:59PM +0100, Jonathan Cameron wrote:

> These crossed with the previous fix to get rid of examples
> using aarch64 for which support is not yet upstream.
> 
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Reviewed-by: Fan Ni <fan.ni@samsung.com>

> ---
>  docs/system/devices/cxl.rst | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index b742120657..6ab5f72473 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -313,7 +313,7 @@ A very simple setup with just one directly attached CXL Type 3 Persistent Memory
>  
>  A very simple setup with just one directly attached CXL Type 3 Volatile Memory device::
>  
> -  qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \
> +  qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \
>    ...
>    -object memory-backend-ram,id=vmem0,share=on,size=256M \
>    -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \
> @@ -323,7 +323,7 @@ A very simple setup with just one directly attached CXL Type 3 Volatile Memory d
>  
>  The same volatile setup may optionally include an LSA region::
>  
> -  qemu-system-aarch64 -M virt,gic-version=3,cxl=on -m 4g,maxmem=8G,slots=8 -cpu max \
> +  qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \
>    ...
>    -object memory-backend-ram,id=vmem0,share=on,size=256M \
>    -object memory-backend-file,id=cxl-lsa0,share=on,mem-path=/tmp/lsa.raw,size=256M \
> -- 
> 2.39.2
> 

Re: [PATCH 3/3] docs/cxl: Cleanout some more aarch64 examples.

[Peter Maydell]

On Mon, 18 Sept 2023 at 16:04, Jonathan Cameron
<Jonathan.Cameron@huawei.com> wrote:
>
> These crossed with the previous fix to get rid of examples
> using aarch64 for which support is not yet upstream.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1892

thanks
-- PMM