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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id h16-20020a5d5490000000b0031773a8e5c4sm15062182wrv.37.2023.09.19.04.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Sep 2023 04:18:32 -0700 (PDT) Date: Tue, 19 Sep 2023 13:18:31 +0200 From: Andrew Jones To: Andreas Schwab Cc: qemu-devel@nongnu.org, Alexandre Ghiti , Bin Meng , Frank Chang , Alistair Francis , Palmer Dabbelt Subject: Re: [PATCH] riscv: Call set_satp_mode_max_supported in riscv_host_cpu_init Message-ID: <20230919-853624bc6079021587741eb4@orel> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Sep 19, 2023 at 09:57:32AM +0200, Andreas Schwab wrote: > When running in KVM mode with -cpu host, cfg.satp_mode.supported is not > initialized, causing an infinite loop in riscv_cpu_satp_mode_finalize. > > Fixes: 6df3747a27 ("riscv: Introduce satp mode hw capabilities") > Signed-off-by: Andreas Schwab > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f227c7664e..bb8dc3bb40 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -623,8 +623,10 @@ static void riscv_host_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > #if defined(TARGET_RISCV32) > set_misa(env, MXL_RV32, 0); > + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); > #elif defined(TARGET_RISCV64) > set_misa(env, MXL_RV64, 0); > + set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); > #endif > riscv_cpu_add_user_properties(obj); > } > -- > 2.42.0 > This should be fixed by https://lore.kernel.org/all/20230911064320.939791-37-alistair.francis@wdc.com/ Thanks, drew