[PULL v2 00/39] tcg patch queue

[PULL v2 00/39] tcg patch queue

[Richard Henderson]

v2: tcg/loongarch64 patch set without last minute tweaks.

r~

The following changes since commit 005ad32358f12fe9313a4a01918a55e60d4f39e5:

  Merge tag 'pull-tpm-2023-09-12-3' of https://github.com/stefanberger/qemu-tpm into staging (2023-09-13 13:41:57 -0400)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230915-2

for you to fetch changes up to a97a83753c90d79ed15a716610af23fabd84aaed:

  tcg: Map code_gen_buffer with PROT_BTI (2023-09-16 14:57:16 +0000)

----------------------------------------------------------------
*: Delete checks for old host definitions
tcg/loongarch64: Generate LSX instructions
fpu: Add conversions between bfloat16 and [u]int8
fpu: Handle m68k extended precision denormals properly
accel/tcg: Improve cputlb i/o organization
accel/tcg: Simplify tlb_plugin_lookup
accel/tcg: Remove false-negative halted assertion
tcg: Add gvec compare with immediate and scalar operand
tcg/aarch64: Emit BTI insns at jump landing pads

----------------------------------------------------------------
Akihiko Odaki (3):
      util: Delete checks for old host definitions
      softmmu: Delete checks for old host definitions
      thunk: Delete checks for old host definitions

Jiajie Chen (16):
      tcg/loongarch64: Import LSX instructions
      tcg/loongarch64: Lower basic tcg vec ops to LSX
      tcg: pass vece to tcg_target_const_match()
      tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt
      tcg/loongarch64: Lower add/sub_vec to vadd/vsub
      tcg/loongarch64: Lower vector bitwise operations
      tcg/loongarch64: Lower neg_vec to vneg
      tcg/loongarch64: Lower mul_vec to vmul
      tcg/loongarch64: Lower vector min max ops
      tcg/loongarch64: Lower vector saturated ops
      tcg/loongarch64: Lower vector shift vector ops
      tcg/loongarch64: Lower bitsel_vec to vbitsel
      tcg/loongarch64: Lower vector shift integer ops
      tcg/loongarch64: Lower rotv_vec ops to LSX
      tcg/loongarch64: Lower rotli_vec to vrotri
      tcg/loongarch64: Implement 128-bit load & store

LIU Zhiwei (2):
      accel/tcg: Fix the comment for CPUTLBEntryFull
      fpu: Add conversions between bfloat16 and [u]int8

Nicholas Piggin (1):
      accel/tcg: mttcg remove false-negative halted assertion

Richard Henderson (17):
      tcg: Add gvec compare with immediate and scalar operand
      target/arm: Use tcg_gen_gvec_cmpi for compare vs 0
      accel/tcg: Simplify tlb_plugin_lookup
      accel/tcg: Split out io_prepare and io_failed
      accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failed
      plugin: Simplify struct qemu_plugin_hwaddr
      accel/tcg: Merge cpu_transaction_failed into io_failed
      accel/tcg: Replace direct use of io_readx/io_writex in do_{ld,st}_1
      accel/tcg: Merge io_readx into do_ld_mmio_beN
      accel/tcg: Merge io_writex into do_st_mmio_leN
      accel/tcg: Introduce do_ld16_mmio_beN
      accel/tcg: Introduce do_st16_mmio_leN
      fpu: Handle m68k extended precision denormals properly
      tcg: Add tcg_out_tb_start backend hook
      util/cpuinfo-aarch64: Add CPUINFO_BTI
      tcg/aarch64: Emit BTI insns at jump landing pads
      tcg: Map code_gen_buffer with PROT_BTI

 accel/tcg/tcg-runtime.h              |   25 +
 host/include/aarch64/host/cpuinfo.h  |    1 +
 include/exec/cpu-defs.h              |   12 +-
 include/exec/user/thunk.h            |    3 +-
 include/fpu/softfloat.h              |   12 +
 include/hw/core/cpu.h                |   13 -
 include/qemu/plugin-memory.h         |   11 +-
 include/qemu/typedefs.h              |    1 -
 include/tcg/tcg-op-gvec-common.h     |    6 +
 tcg/loongarch64/tcg-target-con-set.h |    9 +
 tcg/loongarch64/tcg-target-con-str.h |    3 +
 tcg/loongarch64/tcg-target.h         |   40 +-
 tcg/loongarch64/tcg-target.opc.h     |   12 +
 accel/tcg/cputlb.c                   |  437 ++-
 accel/tcg/tcg-accel-ops-mttcg.c      |    9 +-
 accel/tcg/tcg-runtime-gvec.c         |   26 +
 fpu/softfloat.c                      |   67 +-
 plugins/api.c                        |   27 +-
 softmmu/async-teardown.c             |    3 -
 target/arm/tcg/translate.c           |   56 +-
 tcg/region.c                         |   41 +-
 tcg/tcg-op-gvec.c                    |  149 +
 tcg/tcg.c                            |    7 +-
 tests/tcg/m68k/denormal.c            |   53 +
 util/cpuinfo-aarch64.c               |    7 +
 util/oslib-posix.c                   |   15 +-
 fpu/softfloat-parts.c.inc            |    7 +-
 tcg/aarch64/tcg-target.c.inc         |   59 +-
 tcg/arm/tcg-target.c.inc             |    7 +-
 tcg/i386/tcg-target.c.inc            |    7 +-
 tcg/loongarch64/tcg-insn-defs.c.inc  | 6019 +++++++++++++++++++++++++++++++++-
 tcg/loongarch64/tcg-target.c.inc     |  624 +++-
 tcg/mips/tcg-target.c.inc            |    7 +-
 tcg/ppc/tcg-target.c.inc             |    7 +-
 tcg/riscv/tcg-target.c.inc           |    7 +-
 tcg/s390x/tcg-target.c.inc           |    7 +-
 tcg/sparc64/tcg-target.c.inc         |    7 +-
 tcg/tci/tcg-target.c.inc             |    7 +-
 tests/tcg/m68k/Makefile.target       |    2 +-
 39 files changed, 7419 insertions(+), 393 deletions(-)
 create mode 100644 tcg/loongarch64/tcg-target.opc.h
 create mode 100644 tests/tcg/m68k/denormal.c

[PULL v2 21/39] tcg/loongarch64: Implement 128-bit load & store

[Richard Henderson]

From: Jiajie Chen <c@jia.je>

If LSX is available, use LSX instructions to implement 128-bit load &
store when MO_128 is required, otherwise use two 64-bit loads & stores.

Signed-off-by: Jiajie Chen <c@jia.je>
Message-Id: <20230908022302.180442-17-c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/loongarch64/tcg-target-con-set.h |  2 +
 tcg/loongarch64/tcg-target.h         |  2 +-
 tcg/loongarch64/tcg-target.c.inc     | 59 ++++++++++++++++++++++++++++
 3 files changed, 62 insertions(+), 1 deletion(-)

diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
index 914572d21b..77d62e38e7 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -18,6 +18,7 @@ C_O0_I1(r)
 C_O0_I2(rZ, r)
 C_O0_I2(rZ, rZ)
 C_O0_I2(w, r)
+C_O0_I3(r, r, r)
 C_O1_I1(r, r)
 C_O1_I1(w, r)
 C_O1_I1(w, w)
@@ -37,3 +38,4 @@ C_O1_I2(w, w, wM)
 C_O1_I2(w, w, wA)
 C_O1_I3(w, w, w, w)
 C_O1_I4(r, rZ, rJ, rZ, rZ)
+C_O2_I1(r, r, r)
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index 67b0a95532..03017672f6 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -171,7 +171,7 @@ extern bool use_lsx_instructions;
 #define TCG_TARGET_HAS_muluh_i64        1
 #define TCG_TARGET_HAS_mulsh_i64        1
 
-#define TCG_TARGET_HAS_qemu_ldst_i128   0
+#define TCG_TARGET_HAS_qemu_ldst_i128   use_lsx_instructions
 
 #define TCG_TARGET_HAS_v64              0
 #define TCG_TARGET_HAS_v128             use_lsx_instructions
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 82901d678a..fde744e766 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1081,6 +1081,48 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
     }
 }
 
+static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg data_lo, TCGReg data_hi,
+                                   TCGReg addr_reg, MemOpIdx oi, bool is_ld)
+{
+    TCGLabelQemuLdst *ldst;
+    HostAddress h;
+
+    ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld);
+
+    if (h.aa.atom == MO_128) {
+        /*
+         * Use VLDX/VSTX when 128-bit atomicity is required.
+         * If address is aligned to 16-bytes, the 128-bit load/store is atomic.
+         */
+        if (is_ld) {
+            tcg_out_opc_vldx(s, TCG_VEC_TMP0, h.base, h.index);
+            tcg_out_opc_vpickve2gr_d(s, data_lo, TCG_VEC_TMP0, 0);
+            tcg_out_opc_vpickve2gr_d(s, data_hi, TCG_VEC_TMP0, 1);
+        } else {
+            tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_lo, 0);
+            tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_hi, 1);
+            tcg_out_opc_vstx(s, TCG_VEC_TMP0, h.base, h.index);
+        }
+    } else {
+        /* Otherwise use a pair of LD/ST. */
+        tcg_out_opc_add_d(s, TCG_REG_TMP0, h.base, h.index);
+        if (is_ld) {
+            tcg_out_opc_ld_d(s, data_lo, TCG_REG_TMP0, 0);
+            tcg_out_opc_ld_d(s, data_hi, TCG_REG_TMP0, 8);
+        } else {
+            tcg_out_opc_st_d(s, data_lo, TCG_REG_TMP0, 0);
+            tcg_out_opc_st_d(s, data_hi, TCG_REG_TMP0, 8);
+        }
+    }
+
+    if (ldst) {
+        ldst->type = TCG_TYPE_I128;
+        ldst->datalo_reg = data_lo;
+        ldst->datahi_reg = data_hi;
+        ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
+    }
+}
+
 /*
  * Entry-points
  */
@@ -1145,6 +1187,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
     TCGArg a0 = args[0];
     TCGArg a1 = args[1];
     TCGArg a2 = args[2];
+    TCGArg a3 = args[3];
     int c2 = const_args[2];
 
     switch (opc) {
@@ -1507,6 +1550,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_qemu_ld_a64_i64:
         tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
         break;
+    case INDEX_op_qemu_ld_a32_i128:
+    case INDEX_op_qemu_ld_a64_i128:
+        tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, true);
+        break;
     case INDEX_op_qemu_st_a32_i32:
     case INDEX_op_qemu_st_a64_i32:
         tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
@@ -1515,6 +1562,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_qemu_st_a64_i64:
         tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
         break;
+    case INDEX_op_qemu_st_a32_i128:
+    case INDEX_op_qemu_st_a64_i128:
+        tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, false);
+        break;
 
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
@@ -1996,6 +2047,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_qemu_st_a64_i64:
         return C_O0_I2(rZ, r);
 
+    case INDEX_op_qemu_ld_a32_i128:
+    case INDEX_op_qemu_ld_a64_i128:
+        return C_O2_I1(r, r, r);
+
+    case INDEX_op_qemu_st_a32_i128:
+    case INDEX_op_qemu_st_a64_i128:
+        return C_O0_I3(r, r, r);
+
     case INDEX_op_brcond_i32:
     case INDEX_op_brcond_i64:
         return C_O0_I2(rZ, rZ);
-- 
2.34.1

Re: [PULL v2 00/39] tcg patch queue

[Stefan Hajnoczi]

[-- Attachment #1: Type: text/plain, Size: 115 bytes --]

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[PULL v2 00/39] tcg patch queue

[Richard Henderson]

v2: Fix rebase error in patch 38 (tcg/s390x: Support TCG_COND_TST{EQ,NE}).


r~


The following changes since commit 39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440:

  Merge tag 'pull-qapi-2024-02-03' of https://repo.or.cz/qemu/armbru into staging (2024-02-03 13:31:58 +0000)

are available in the Git repository at:

  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240205-2

for you to fetch changes up to 23c5692abc3917151dee36c00d751cf5bc46ef19:

  tcg/tci: Support TCG_COND_TST{EQ,NE} (2024-02-05 22:45:41 +0000)

----------------------------------------------------------------
tcg: Introduce TCG_COND_TST{EQ,NE}
target/alpha: Use TCG_COND_TST{EQ,NE}
target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond
target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc
target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}
target/s390x: Improve general case of disas_jcc

----------------------------------------------------------------
Paolo Bonzini (1):
      tcg/i386: Use TEST r,r to test 8/16/32 bits

Philippe Mathieu-Daudé (1):
      tcg/aarch64: Massage tcg_out_brcond()

Richard Henderson (37):
      tcg: Introduce TCG_COND_TST{EQ,NE}
      tcg: Introduce TCG_TARGET_HAS_tst
      tcg/optimize: Split out arg_is_const_val
      tcg/optimize: Split out do_constant_folding_cond1
      tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2
      tcg/optimize: Handle TCG_COND_TST{EQ,NE}
      tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported
      target/alpha: Pass immediate value to gen_bcond_internal()
      target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S}
      target/alpha: Use TCG_COND_TST{EQ,NE} for CMOVLB{C,S}
      target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero
      target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond
      target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc
      target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}
      target/s390x: Improve general case of disas_jcc
      tcg: Add TCGConst argument to tcg_target_const_match
      tcg/aarch64: Support TCG_COND_TST{EQ,NE}
      tcg/aarch64: Generate TBZ, TBNZ
      tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX
      tcg/arm: Split out tcg_out_cmp()
      tcg/arm: Support TCG_COND_TST{EQ,NE}
      tcg/i386: Pass x86 condition codes to tcg_out_cmov
      tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp
      tcg/i386: Support TCG_COND_TST{EQ,NE}
      tcg/i386: Improve TSTNE/TESTEQ vs powers of two
      tcg/sparc64: Hoist read of tcg_cond_to_rcond
      tcg/sparc64: Pass TCGCond to tcg_out_cmp
      tcg/sparc64: Support TCG_COND_TST{EQ,NE}
      tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc
      tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel
      tcg/ppc: Tidy up tcg_target_const_match
      tcg/ppc: Add TCG_CT_CONST_CMP
      tcg/ppc: Support TCG_COND_TST{EQ,NE}
      tcg/s390x: Split constraint A into J+U
      tcg/s390x: Add TCG_CT_CONST_CMP
      tcg/s390x: Support TCG_COND_TST{EQ,NE}
      tcg/tci: Support TCG_COND_TST{EQ,NE}

 docs/devel/tcg-ops.rst           |   2 +
 include/tcg/tcg-cond.h           |  74 ++++--
 tcg/aarch64/tcg-target-con-set.h |   5 +-
 tcg/aarch64/tcg-target-con-str.h |   1 +
 tcg/aarch64/tcg-target.h         |   2 +
 tcg/arm/tcg-target.h             |   2 +
 tcg/i386/tcg-target-con-set.h    |   6 +-
 tcg/i386/tcg-target-con-str.h    |   1 +
 tcg/i386/tcg-target.h            |   2 +
 tcg/loongarch64/tcg-target.h     |   2 +
 tcg/mips/tcg-target.h            |   2 +
 tcg/ppc/tcg-target-con-set.h     |   5 +-
 tcg/ppc/tcg-target-con-str.h     |   1 +
 tcg/ppc/tcg-target.h             |   2 +
 tcg/riscv/tcg-target.h           |   2 +
 tcg/s390x/tcg-target-con-set.h   |   8 +-
 tcg/s390x/tcg-target-con-str.h   |   3 +-
 tcg/s390x/tcg-target.h           |   2 +
 tcg/sparc64/tcg-target.h         |   2 +
 tcg/tcg-internal.h               |   2 +
 tcg/tci/tcg-target.h             |   2 +
 target/alpha/translate.c         |  94 ++++----
 target/m68k/translate.c          |  74 +++---
 target/s390x/tcg/translate.c     | 100 +++------
 target/sparc/translate.c         |   4 +-
 tcg/optimize.c                   | 474 ++++++++++++++++++++++++++++++---------
 tcg/tcg.c                        |  40 +++-
 tcg/tci.c                        |  14 ++
 tcg/aarch64/tcg-target.c.inc     | 166 +++++++++++---
 tcg/arm/tcg-target.c.inc         |  62 +++--
 tcg/i386/tcg-target.c.inc        | 201 ++++++++++++-----
 tcg/loongarch64/tcg-target.c.inc |   3 +-
 tcg/mips/tcg-target.c.inc        |   3 +-
 tcg/ppc/tcg-target.c.inc         | 294 ++++++++++++++++++------
 tcg/riscv/tcg-target.c.inc       |   3 +-
 tcg/s390x/tcg-target.c.inc       | 246 +++++++++++++-------
 tcg/sparc64/tcg-target.c.inc     |  65 ++++--
 tcg/tci/tcg-target.c.inc         |   3 +-
 38 files changed, 1379 insertions(+), 595 deletions(-)

Re: [PULL v2 00/39] tcg patch queue

[Peter Maydell]

On Tue, 6 Feb 2024 at 03:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> v2: Fix rebase error in patch 38 (tcg/s390x: Support TCG_COND_TST{EQ,NE}).
>
>
> r~
>
>
> The following changes since commit 39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440:
>
>   Merge tag 'pull-qapi-2024-02-03' of https://repo.or.cz/qemu/armbru into staging (2024-02-03 13:31:58 +0000)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240205-2
>
> for you to fetch changes up to 23c5692abc3917151dee36c00d751cf5bc46ef19:
>
>   tcg/tci: Support TCG_COND_TST{EQ,NE} (2024-02-05 22:45:41 +0000)
>
> ----------------------------------------------------------------
> tcg: Introduce TCG_COND_TST{EQ,NE}
> target/alpha: Use TCG_COND_TST{EQ,NE}
> target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond
> target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc
> target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}
> target/s390x: Improve general case of disas_jcc

This really doesn't want to pass the ubuntu-20.04-s390x-all job:

https://gitlab.com/qemu-project/qemu/-/jobs/6109442678
https://gitlab.com/qemu-project/qemu/-/jobs/6108249863
https://gitlab.com/qemu-project/qemu/-/jobs/6106928534
https://gitlab.com/qemu-project/qemu/-/jobs/6105718495

Now, this has definitely been a flaky job recently, so maybe it's
not this pullreq's fault.

This is a passing job from the last successful merge:
https://gitlab.com/qemu-project/qemu/-/jobs/6089342252
That took 24 minutes to run, and all the failed jobs above
took 70 minutes plus.

TBH I think there is something weird with the runner. Looking
at the timestamps in the log, it seems like the passing job
completed its compile step in about 14 minutes, whereas one
of the failing jobs took about 39 minutes. So the entire
run of the job slowed down by more than 2.5x, which is enough
to put it into the range where either the whole job or
individual tests time out.

thuth: any idea why that might happen? (I look in on the
machine from time to time and it doesn't seem to be doing
anything it shouldn't that would be eating CPU.)

Christian: this is on the s390x machine we have. Does the
VM setup for that share IO or CPU with other VMs somehow?
Is there some reason why it might have very variable
performance over time?

thanks
-- PMM

Re: [PULL v2 00/39] tcg patch queue

[Peter Maydell]

On Tue, 6 Feb 2024 at 21:24, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Tue, 6 Feb 2024 at 03:22, Richard Henderson
> <richard.henderson@linaro.org> wrote:
> >
> > v2: Fix rebase error in patch 38 (tcg/s390x: Support TCG_COND_TST{EQ,NE}).
> >
> >
> > r~
> >
> >
> > The following changes since commit 39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440:
> >
> >   Merge tag 'pull-qapi-2024-02-03' of https://repo.or.cz/qemu/armbru into staging (2024-02-03 13:31:58 +0000)
> >
> > are available in the Git repository at:
> >
> >   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240205-2
> >
> > for you to fetch changes up to 23c5692abc3917151dee36c00d751cf5bc46ef19:
> >
> >   tcg/tci: Support TCG_COND_TST{EQ,NE} (2024-02-05 22:45:41 +0000)
> >
> > ----------------------------------------------------------------
> > tcg: Introduce TCG_COND_TST{EQ,NE}
> > target/alpha: Use TCG_COND_TST{EQ,NE}
> > target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond
> > target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc
> > target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}
> > target/s390x: Improve general case of disas_jcc
>
> This really doesn't want to pass the ubuntu-20.04-s390x-all job:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/6109442678
> https://gitlab.com/qemu-project/qemu/-/jobs/6108249863
> https://gitlab.com/qemu-project/qemu/-/jobs/6106928534
> https://gitlab.com/qemu-project/qemu/-/jobs/6105718495
>
> Now, this has definitely been a flaky job recently, so maybe it's
> not this pullreq's fault.
>
> This is a passing job from the last successful merge:
> https://gitlab.com/qemu-project/qemu/-/jobs/6089342252
> That took 24 minutes to run, and all the failed jobs above
> took 70 minutes plus.

Ruling out anything about this particular merge attempt:

This is a passing job from a recent succesful merge:
 https://gitlab.com/qemu-project/qemu/-/jobs/6089089816
That took 37 minutes to run (21 mins in configure-n-compile).

This is a failing job for the same commit:
  https://gitlab.com/qemu-project/qemu/-/jobs/6086439717
That took 58 minutes (26 mins in configure-n-compile).

So there's a lot of between run variation, though in that
case it was not so much as in some of these examples.

-- PMM

Re: [PULL v2 00/39] tcg patch queue

[Christian Borntraeger]

Am 06.02.24 um 22:24 schrieb Peter Maydell:
[..]
> Christian: this is on the s390x machine we have. Does the
> VM setup for that share IO or CPU with other VMs somehow?

Yes it does, this is a shared system. I will talk to the team if there is anything that we can do about this.

Re: [PULL v2 00/39] tcg patch queue

[Peter Maydell]

On Tue, 6 Feb 2024 at 03:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> v2: Fix rebase error in patch 38 (tcg/s390x: Support TCG_COND_TST{EQ,NE}).
>
>
> r~
>
>
> The following changes since commit 39a6e4f87e7b75a45b08d6dc8b8b7c2954c87440:
>
>   Merge tag 'pull-qapi-2024-02-03' of https://repo.or.cz/qemu/armbru into staging (2024-02-03 13:31:58 +0000)
>
> are available in the Git repository at:
>
>   https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240205-2
>
> for you to fetch changes up to 23c5692abc3917151dee36c00d751cf5bc46ef19:
>
>   tcg/tci: Support TCG_COND_TST{EQ,NE} (2024-02-05 22:45:41 +0000)
>
> ----------------------------------------------------------------
> tcg: Introduce TCG_COND_TST{EQ,NE}
> target/alpha: Use TCG_COND_TST{EQ,NE}
> target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond
> target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc
> target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM}
> target/s390x: Improve general case of disas_jcc
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.

-- PMM