From: Nick Bowler <nbowler@draconx.ca>
To: qemu-devel@nongnu.org
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
Artyom Tarasenko <atar4qemu@gmail.com>
Subject: [PATCH 6/8] target/sparc: Fix VIS fpmerge input registers.
Date: Mon, 25 Sep 2023 01:03:55 -0400 [thread overview]
Message-ID: <20230925050545.30912-7-nbowler@draconx.ca> (raw)
In-Reply-To: <20230925050545.30912-1-nbowler@draconx.ca>
On a real UltraSparc II CPU, the fpmerge instruction reads two
single-precision input registers, but the emulator is reading
from double-precision input registers instead.
These are unlikely to contain the correct data so in most instances
the results of the emulation are just garbage in most instances.
Signed-off-by: Nick Bowler <nbowler@draconx.ca>
---
target/sparc/helper.h | 2 +-
target/sparc/translate.c | 6 +++++-
target/sparc/vis_helper.c | 26 +++++++++++++-------------
3 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index 7a588f3068..b71688079f 100644
--- a/target/sparc/helper.h
+++ b/target/sparc/helper.h
@@ -125,7 +125,7 @@ DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_RWG, s64, env, f32)
DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_RWG, s64, env, f64)
DEF_HELPER_FLAGS_1(fqtox, TCG_CALL_NO_RWG, s64, env)
-DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i32, i32)
DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i32, i64)
DEF_HELPER_FLAGS_2(fmul8x16al, TCG_CALL_NO_RWG_SE, i64, i32, i32)
DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_NO_RWG_SE, i64, i32, i32)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index cfccd95c3a..241ac429ca 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4825,7 +4825,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x04b: /* VIS I fpmerge */
CHECK_FPU_FEATURE(dc, VIS1);
- gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge);
+ cpu_src1_32 = gen_load_fpr_F(dc, rs1);
+ cpu_src2_32 = gen_load_fpr_F(dc, rs2);
+ cpu_dst_64 = gen_dest_fpr_D(dc, rd);
+ gen_helper_fpmerge(cpu_dst_64, cpu_src1_32, cpu_src2_32);
+ gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0x04c: /* VIS II bshuffle */
CHECK_FPU_FEATURE(dc, VIS2);
diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c
index 306383ba60..029aad3923 100644
--- a/target/sparc/vis_helper.c
+++ b/target/sparc/vis_helper.c
@@ -77,22 +77,22 @@ typedef union {
float32 f;
} VIS32;
-uint64_t helper_fpmerge(uint64_t src1, uint64_t src2)
+uint64_t helper_fpmerge(uint32_t src1, uint32_t src2)
{
- VIS64 s, d;
+ VIS32 s1, s2;
+ VIS64 d;
- s.ll = src1;
- d.ll = src2;
+ s1.l = src1;
+ s2.l = src2;
- /* Reverse calculation order to handle overlap */
- d.VIS_B64(7) = s.VIS_B64(3);
- d.VIS_B64(6) = d.VIS_B64(3);
- d.VIS_B64(5) = s.VIS_B64(2);
- d.VIS_B64(4) = d.VIS_B64(2);
- d.VIS_B64(3) = s.VIS_B64(1);
- d.VIS_B64(2) = d.VIS_B64(1);
- d.VIS_B64(1) = s.VIS_B64(0);
- /* d.VIS_B64(0) = d.VIS_B64(0); */
+ d.VIS_B64(0) = s2.VIS_B32(0);
+ d.VIS_B64(1) = s1.VIS_B32(0);
+ d.VIS_B64(2) = s2.VIS_B32(1);
+ d.VIS_B64(3) = s1.VIS_B32(1);
+ d.VIS_B64(4) = s2.VIS_B32(2);
+ d.VIS_B64(5) = s1.VIS_B32(2);
+ d.VIS_B64(6) = s2.VIS_B32(3);
+ d.VIS_B64(7) = s1.VIS_B32(3);
return d.ll;
}
--
2.41.0
next prev parent reply other threads:[~2023-09-25 12:57 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-25 5:03 [PATCH 0/8] SPARC VIS fixes Nick Bowler
2023-09-25 5:03 ` [PATCH 1/8] target/sparc: Fix VIS fmul8x16 input register Nick Bowler
2023-09-28 21:29 ` Richard Henderson
2023-09-25 5:03 ` [PATCH 2/8] target/sparc: Fix VIS fmul8x16au instruction Nick Bowler
2023-09-28 21:32 ` Richard Henderson
2023-09-29 0:41 ` Nick Bowler
2023-09-29 1:04 ` Richard Henderson
2023-09-25 5:03 ` [PATCH 3/8] target/sparc: Fix VIS fmul8x16al instruction Nick Bowler
2023-09-28 21:32 ` Richard Henderson
2023-09-25 5:03 ` [PATCH 4/8] target/sparc: Fix VIS fmuld8sux16 instruction Nick Bowler
2023-09-28 21:33 ` Richard Henderson
2023-09-25 5:03 ` [PATCH 5/8] target/sparc: Fix VIS fmuld8ulx16 instruction Nick Bowler
2023-09-28 21:34 ` Richard Henderson
2023-09-25 5:03 ` Nick Bowler [this message]
2023-09-28 21:35 ` [PATCH 6/8] target/sparc: Fix VIS fpmerge input registers Richard Henderson
2023-09-29 0:32 ` Nick Bowler
2023-09-25 5:03 ` [PATCH 7/8] target/sparc: Fix VIS fexpand input register Nick Bowler
2023-09-28 21:36 ` Richard Henderson
2023-09-25 5:03 ` [PATCH 8/8] target/sparc: Fix VIS subtraction instructions Nick Bowler
2023-09-28 21:40 ` Richard Henderson
2023-09-29 0:31 ` Nick Bowler
2023-09-28 20:05 ` [PATCH 0/8] SPARC VIS fixes Mark Cave-Ayland
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