* [PATCH v3 1/4] target/ppc: Add new hflags to support BHRB
2023-09-25 17:43 [PATCH v3 0/4] Add BHRB Facility Support Glenn Miles
@ 2023-09-25 17:43 ` Glenn Miles
2023-09-25 17:43 ` [PATCH v3 2/4] target/ppc: Add recording of taken branches to BHRB Glenn Miles
` (4 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Glenn Miles @ 2023-09-25 17:43 UTC (permalink / raw)
To: qemu-ppc
Cc: Glenn Miles, qemu-devel, Daniel Henrique Barboza,
Cédric Le Goater, Nicholas Piggin, David Gibson
This commit is preparatory to the addition of Branch History
Rolling Buffer (BHRB) functionality, which is being provided
today starting with the P8 processor.
BHRB uses several SPR register fields to control whether or not
a branch instruction's address (and sometimes target address)
should be recorded. Checking each of these fields with each
branch instruction using jitted code would lead to a significant
decrease in performance.
Therefore, it was decided that BHRB configuration bits that are
not expected to change frequently should have their state summarized
in an hflag so that the amount of checking done by jitted code can
be reduced.
This commit contains the changes for summarizing the state of the
following register fields in the HFLAGS_BHRB_ENABLE hflag:
MMCR0[FCP] - Determines if BHRB recording is frozen in the
problem state
MMCR0[FCPC] - A modifier for MMCR0[FCP]
MMCRA[BHRBRD] - Disables all BHRB recording for a thread
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
---
target/ppc/cpu.h | 5 +++++
target/ppc/cpu_init.c | 4 ++--
target/ppc/helper.h | 1 +
target/ppc/helper_regs.c | 35 ++++++++++++++++++++++++++++++++
target/ppc/machine.c | 2 +-
target/ppc/power8-pmu-regs.c.inc | 5 +++++
target/ppc/power8-pmu.c | 15 ++++++++++----
target/ppc/power8-pmu.h | 4 ++--
target/ppc/spr_common.h | 1 +
target/ppc/translate.c | 2 ++
10 files changed, 65 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 173e4c351a..55985fb84f 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -439,6 +439,8 @@ FIELD(MSR, LE, MSR_LE, 1)
#define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */
#define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */
#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */
+#define MMCR0_FCP PPC_BIT(34) /* Freeze Counters/BHRB if PR=1 */
+#define MMCR0_FCPC PPC_BIT(51) /* Condition for FCP bit */
/* MMCR0 userspace r/w mask */
#define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
/* MMCR2 userspace r/w mask */
@@ -451,6 +453,8 @@ FIELD(MSR, LE, MSR_LE, 1)
#define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \
MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0)
+#define MMCRA_BHRBRD PPC_BIT(26) /* BHRB Recording Disable */
+
#define MMCR1_EVT_SIZE 8
/* extract64() does a right shift before extracting */
#define MMCR1_PMC1SEL_START 32
@@ -703,6 +707,7 @@ enum {
HFLAGS_PMCJCE = 17, /* MMCR0 PMCjCE bit */
HFLAGS_PMC_OTHER = 18, /* PMC other than PMC5-6 is enabled */
HFLAGS_INSN_CNT = 19, /* PMU instruction count enabled */
+ HFLAGS_BHRB_ENABLE = 20, /* Summary flag for enabling BHRB */
HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 7ab5ee92d9..8c81a75416 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5152,7 +5152,7 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
KVM_REG_PPC_MMCR1, 0x00000000);
spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_MMCRA,
KVM_REG_PPC_MMCRA, 0x00000000);
spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
SPR_NOACCESS, SPR_NOACCESS,
@@ -7164,7 +7164,7 @@ static void ppc_cpu_reset_hold(Object *obj)
if (env->mmu_model != POWERPC_MMU_REAL) {
ppc_tlb_invalidate_all(env);
}
- pmu_mmcr01_updated(env);
+ pmu_mmcr01a_updated(env);
}
/* clean any pending stop state */
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 86f97ee1e7..3df360efe9 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -30,6 +30,7 @@ DEF_HELPER_2(store_dawr0, void, env, tl)
DEF_HELPER_2(store_dawrx0, void, env, tl)
DEF_HELPER_2(store_mmcr0, void, env, tl)
DEF_HELPER_2(store_mmcr1, void, env, tl)
+DEF_HELPER_2(store_mmcrA, void, env, tl)
DEF_HELPER_3(store_pmc, void, env, i32, i64)
DEF_HELPER_2(read_pmc, tl, env, i32)
DEF_HELPER_2(insns_inc, void, env, i32)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index f380342d4d..5696338137 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -47,6 +47,37 @@ void hreg_swap_gpr_tgpr(CPUPPCState *env)
env->tgpr[3] = tmp;
}
+static bool hreg_check_bhrb_enable(CPUPPCState *env)
+{
+ bool pr = !!(env->msr & (1 << MSR_PR));
+ target_long mmcr0;
+ bool fcp;
+ bool hv;
+
+ /* ISA 3.1 adds the PMCRA[BRHBRD] and problem state checks */
+ if ((env->insns_flags2 & PPC2_ISA310) &&
+ ((env->spr[SPR_POWER_MMCRA] & MMCRA_BHRBRD) || !pr)) {
+ return false;
+ }
+
+ /* Check for BHRB "frozen" conditions */
+ mmcr0 = env->spr[SPR_POWER_MMCR0];
+ fcp = !!(mmcr0 & MMCR0_FCP);
+ if (mmcr0 & MMCR0_FCPC) {
+ hv = !!(env->msr & (1ull << MSR_HV));
+ if (fcp) {
+ if (hv && pr) {
+ return false;
+ }
+ } else if (!hv && pr) {
+ return false;
+ }
+ } else if (fcp && pr) {
+ return false;
+ }
+ return true;
+}
+
static uint32_t hreg_compute_pmu_hflags_value(CPUPPCState *env)
{
uint32_t hflags = 0;
@@ -61,6 +92,9 @@ static uint32_t hreg_compute_pmu_hflags_value(CPUPPCState *env)
if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE) {
hflags |= 1 << HFLAGS_PMCJCE;
}
+ if (hreg_check_bhrb_enable(env)) {
+ hflags |= 1 << HFLAGS_BHRB_ENABLE;
+ }
#ifndef CONFIG_USER_ONLY
if (env->pmc_ins_cnt) {
@@ -85,6 +119,7 @@ static uint32_t hreg_compute_pmu_hflags_mask(CPUPPCState *env)
hflags_mask |= 1 << HFLAGS_PMCJCE;
hflags_mask |= 1 << HFLAGS_INSN_CNT;
hflags_mask |= 1 << HFLAGS_PMC_OTHER;
+ hflags_mask |= 1 << HFLAGS_BHRB_ENABLE;
#endif
return hflags_mask;
}
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 68cbdffecd..d42e475bfb 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -333,7 +333,7 @@ static int cpu_post_load(void *opaque, int version_id)
* triggered types (including HDEC) would need to carry more state.
*/
cpu_ppc_store_decr(env, env->spr[SPR_DECR]);
- pmu_mmcr01_updated(env);
+ pmu_mmcr01a_updated(env);
}
return 0;
diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc
index c82feedaff..cab488918a 100644
--- a/target/ppc/power8-pmu-regs.c.inc
+++ b/target/ppc/power8-pmu-regs.c.inc
@@ -175,6 +175,11 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn)
gen_store_spr(SPR_POWER_MMCR2, masked_gprn);
}
+void spr_write_MMCRA(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_mmcrA(cpu_env, cpu_gpr[gprn]);
+}
+
void spr_read_PMC(DisasContext *ctx, int gprn, int sprn)
{
TCGv_i32 t_sprn = tcg_constant_i32(sprn);
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index cbc5889d91..6f5d4e1256 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -82,7 +82,7 @@ static void pmu_update_summaries(CPUPPCState *env)
env->pmc_cyc_cnt = cyc_cnt;
}
-void pmu_mmcr01_updated(CPUPPCState *env)
+void pmu_mmcr01a_updated(CPUPPCState *env)
{
PowerPCCPU *cpu = env_archcpu(env);
@@ -260,7 +260,7 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
env->spr[SPR_POWER_MMCR0] = value;
- pmu_mmcr01_updated(env);
+ pmu_mmcr01a_updated(env);
/* Update cycle overflow timers with the current MMCR0 state */
pmu_update_overflow_timers(env);
@@ -272,7 +272,14 @@ void helper_store_mmcr1(CPUPPCState *env, uint64_t value)
env->spr[SPR_POWER_MMCR1] = value;
- pmu_mmcr01_updated(env);
+ pmu_mmcr01a_updated(env);
+}
+
+void helper_store_mmcrA(CPUPPCState *env, uint64_t value)
+{
+ env->spr[SPR_POWER_MMCRA] = value;
+
+ pmu_mmcr01a_updated(env);
}
target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn)
@@ -301,7 +308,7 @@ static void perfm_alert(PowerPCCPU *cpu)
env->spr[SPR_POWER_MMCR0] |= MMCR0_FC;
/* Changing MMCR0_FC requires summaries and hflags update */
- pmu_mmcr01_updated(env);
+ pmu_mmcr01a_updated(env);
/*
* Delete all pending timers if we need to freeze
diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h
index 775e640053..87fa8c9334 100644
--- a/target/ppc/power8-pmu.h
+++ b/target/ppc/power8-pmu.h
@@ -18,10 +18,10 @@
#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL
void cpu_ppc_pmu_init(CPUPPCState *env);
-void pmu_mmcr01_updated(CPUPPCState *env);
+void pmu_mmcr01a_updated(CPUPPCState *env);
#else
static inline void cpu_ppc_pmu_init(CPUPPCState *env) { }
-static inline void pmu_mmcr01_updated(CPUPPCState *env) { }
+static inline void pmu_mmcr01a_updated(CPUPPCState *env) { }
#endif
#endif
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index 8a9d6cd994..eb2561f593 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -85,6 +85,7 @@ void spr_write_generic32(DisasContext *ctx, int sprn, int gprn);
void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn);
+void spr_write_MMCRA(DisasContext *ctx, int sprn, int gprn);
void spr_write_PMC(DisasContext *ctx, int sprn, int gprn);
void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn);
void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5c28afbbb8..6bf2fb46d5 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -194,6 +194,7 @@ struct DisasContext {
bool mmcr0_pmcjce;
bool pmc_other;
bool pmu_insn_cnt;
+ bool bhrb_enable;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
uint32_t flags;
@@ -7354,6 +7355,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1;
ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1;
ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1;
+ ctx->bhrb_enable = (hflags >> HFLAGS_BHRB_ENABLE) & 1;
ctx->singlestep_enabled = 0;
if ((hflags >> HFLAGS_SE) & 1) {
--
2.31.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 2/4] target/ppc: Add recording of taken branches to BHRB
2023-09-25 17:43 [PATCH v3 0/4] Add BHRB Facility Support Glenn Miles
2023-09-25 17:43 ` [PATCH v3 1/4] target/ppc: Add new hflags to support BHRB Glenn Miles
@ 2023-09-25 17:43 ` Glenn Miles
2024-02-05 8:37 ` Nicholas Piggin
2023-09-25 17:43 ` [PATCH v3 3/4] target/ppc: Add clrbhrb and mfbhrbe instructions Glenn Miles
` (3 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Glenn Miles @ 2023-09-25 17:43 UTC (permalink / raw)
To: qemu-ppc
Cc: Glenn Miles, qemu-devel, Daniel Henrique Barboza,
Cédric Le Goater, Nicholas Piggin, David Gibson
This commit continues adding support for the Branch History
Rolling Buffer (BHRB) as is provided starting with the P8
processor and continuing with its successors. This commit
is limited to the recording and filtering of taken branches.
The following changes were made:
- Enabled functionality on P10 processors only due to
performance impact seen with P8 and P9 where it is not
disabled for non problem state branches.
- Added a BHRB buffer for storing branch instruction and
target addresses for taken branches
- Renamed gen_update_cfar to gen_update_branch_history and
added a 'target' parameter to hold the branch target
address and 'inst_type' parameter to use for filtering
- Added TCG code to gen_update_branch_history that stores
data to the BHRB and updates the BHRB offset.
- Added BHRB resource initialization and reset functions
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
---
target/ppc/cpu.h | 17 +++++
target/ppc/cpu_init.c | 35 +++++++++-
target/ppc/power8-pmu.c | 33 +++++++++
target/ppc/power8-pmu.h | 7 ++
target/ppc/translate.c | 97 ++++++++++++++++++++++++--
target/ppc/translate/branch-impl.c.inc | 2 +-
6 files changed, 183 insertions(+), 8 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 55985fb84f..396b1f1a6c 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -454,6 +454,8 @@ FIELD(MSR, LE, MSR_LE, 1)
MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0)
#define MMCRA_BHRBRD PPC_BIT(26) /* BHRB Recording Disable */
+#define MMCRA_IFM_MASK PPC_BITMASK(32, 33) /* BHRB Instruction Filtering */
+#define MMCRA_IFM_SHIFT PPC_BIT_NR(33)
#define MMCR1_EVT_SIZE 8
/* extract64() does a right shift before extracting */
@@ -680,6 +682,8 @@ enum {
POWERPC_FLAG_SMT = 0x00400000,
/* Using "LPAR per core" mode (as opposed to per-thread) */
POWERPC_FLAG_SMT_1LPAR = 0x00800000,
+ /* Has BHRB */
+ POWERPC_FLAG_BHRB = 0x01000000,
};
/*
@@ -1106,6 +1110,9 @@ DEXCR_ASPECT(PHIE, 6)
#define PPC_CPU_OPCODES_LEN 0x40
#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
+#define BHRB_MAX_NUM_ENTRIES_LOG2 (5)
+#define BHRB_MAX_NUM_ENTRIES (1 << BHRB_MAX_NUM_ENTRIES_LOG2)
+
struct CPUArchState {
/* Most commonly used resources during translated code execution first */
target_ulong gpr[32]; /* general purpose registers */
@@ -1196,6 +1203,16 @@ struct CPUArchState {
int dcache_line_size;
int icache_line_size;
+#ifdef TARGET_PPC64
+ /* Branch History Rolling Buffer (BHRB) resources */
+ target_ulong bhrb_num_entries;
+ target_ulong bhrb_base;
+ target_ulong bhrb_filter;
+ target_ulong bhrb_offset;
+ target_ulong bhrb_offset_mask;
+ uint64_t bhrb[BHRB_MAX_NUM_ENTRIES];
+#endif
+
/* These resources are used during exception processing */
/* CPU model definition */
target_ulong msr_mask;
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 8c81a75416..3c326b54ac 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6110,6 +6110,28 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->l1_icache_size = 0x8000;
}
+static void bhrb_init_state(CPUPPCState *env, target_long num_entries_log2)
+{
+ if (env->flags & POWERPC_FLAG_BHRB) {
+ if (num_entries_log2 > BHRB_MAX_NUM_ENTRIES_LOG2) {
+ num_entries_log2 = BHRB_MAX_NUM_ENTRIES_LOG2;
+ }
+ env->bhrb_num_entries = 1 << num_entries_log2;
+ env->bhrb_base = (target_long)&env->bhrb[0];
+ env->bhrb_offset_mask = (env->bhrb_num_entries * sizeof(uint64_t)) - 1;
+ }
+}
+
+static void bhrb_reset_state(CPUPPCState *env)
+{
+ if (env->flags & POWERPC_FLAG_BHRB) {
+ env->bhrb_offset = 0;
+ env->bhrb_filter = 0;
+ memset(env->bhrb, 0, sizeof(env->bhrb));
+ }
+}
+
+#define POWER8_BHRB_ENTRIES_LOG2 5
static void init_proc_POWER8(CPUPPCState *env)
{
/* Common Registers */
@@ -6151,6 +6173,8 @@ static void init_proc_POWER8(CPUPPCState *env)
env->dcache_line_size = 128;
env->icache_line_size = 128;
+ bhrb_init_state(env, POWER8_BHRB_ENTRIES_LOG2);
+
/* Allocate hardware IRQ controller */
init_excp_POWER8(env);
ppcPOWER7_irq_init(env_archcpu(env));
@@ -6275,6 +6299,7 @@ static struct ppc_radix_page_info POWER9_radix_page_info = {
};
#endif /* CONFIG_USER_ONLY */
+#define POWER9_BHRB_ENTRIES_LOG2 5
static void init_proc_POWER9(CPUPPCState *env)
{
/* Common Registers */
@@ -6325,6 +6350,8 @@ static void init_proc_POWER9(CPUPPCState *env)
env->dcache_line_size = 128;
env->icache_line_size = 128;
+ bhrb_init_state(env, POWER9_BHRB_ENTRIES_LOG2);
+
/* Allocate hardware IRQ controller */
init_excp_POWER9(env);
ppcPOWER9_irq_init(env_archcpu(env));
@@ -6468,6 +6495,7 @@ static struct ppc_radix_page_info POWER10_radix_page_info = {
};
#endif /* !CONFIG_USER_ONLY */
+#define POWER10_BHRB_ENTRIES_LOG2 5
static void init_proc_POWER10(CPUPPCState *env)
{
/* Common Registers */
@@ -6515,6 +6543,8 @@ static void init_proc_POWER10(CPUPPCState *env)
env->dcache_line_size = 128;
env->icache_line_size = 128;
+ bhrb_init_state(env, POWER10_BHRB_ENTRIES_LOG2);
+
/* Allocate hardware IRQ controller */
init_excp_POWER10(env);
ppcPOWER9_irq_init(env_archcpu(env));
@@ -6620,7 +6650,8 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
- POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
+ POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV |
+ POWERPC_FLAG_BHRB;
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
}
@@ -7190,6 +7221,8 @@ static void ppc_cpu_reset_hold(Object *obj)
}
env->spr[i] = spr->default_value;
}
+
+ bhrb_reset_state(env);
}
#ifndef CONFIG_USER_ONLY
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index 6f5d4e1256..db9ee8e96b 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -82,6 +82,37 @@ static void pmu_update_summaries(CPUPPCState *env)
env->pmc_cyc_cnt = cyc_cnt;
}
+static void hreg_bhrb_filter_update(CPUPPCState *env)
+{
+ target_long ifm;
+
+ if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE)) {
+ /* disable recording to BHRB */
+ env->bhrb_filter = BHRB_TYPE_NORECORD;
+ return;
+ }
+
+ ifm = (env->spr[SPR_POWER_MMCRA] & MMCRA_IFM_MASK) >> MMCRA_IFM_SHIFT;
+ switch (ifm) {
+ case 0:
+ /* record all branches */
+ env->bhrb_filter = -1;
+ break;
+ case 1:
+ /* only record calls (LK = 1) */
+ env->bhrb_filter = BHRB_TYPE_CALL;
+ break;
+ case 2:
+ /* only record indirect branches */
+ env->bhrb_filter = BHRB_TYPE_INDIRECT;
+ break;
+ case 3:
+ /* only record conditional branches */
+ env->bhrb_filter = BHRB_TYPE_COND;
+ break;
+ }
+}
+
void pmu_mmcr01a_updated(CPUPPCState *env)
{
PowerPCCPU *cpu = env_archcpu(env);
@@ -95,6 +126,8 @@ void pmu_mmcr01a_updated(CPUPPCState *env)
ppc_set_irq(cpu, PPC_INTERRUPT_PERFM, 0);
}
+ hreg_bhrb_filter_update(env);
+
/*
* Should this update overflow timers (if mmcr0 is updated) so they
* get set in cpu_post_load?
diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h
index 87fa8c9334..a887094045 100644
--- a/target/ppc/power8-pmu.h
+++ b/target/ppc/power8-pmu.h
@@ -17,6 +17,13 @@
#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL
+#define BHRB_TYPE_NORECORD 0x00
+#define BHRB_TYPE_CALL 0x01
+#define BHRB_TYPE_INDIRECT 0x02
+#define BHRB_TYPE_COND 0x04
+#define BHRB_TYPE_OTHER 0x08
+#define BHRB_TYPE_XL_FORM 0x10
+
void cpu_ppc_pmu_init(CPUPPCState *env);
void pmu_mmcr01a_updated(CPUPPCState *env);
#else
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 6bf2fb46d5..5f0c79923f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -181,6 +181,7 @@ struct DisasContext {
#if defined(TARGET_PPC64)
bool sf_mode;
bool has_cfar;
+ bool has_bhrb;
#endif
bool fpu_enabled;
bool altivec_enabled;
@@ -4130,12 +4131,83 @@ static void gen_rvwinkle(DisasContext *ctx)
}
#endif /* #if defined(TARGET_PPC64) */
-static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
+static inline TCGv gen_write_bhrb(TCGv base, TCGv offset, TCGv mask, TCGv value)
+{
+ TCGv tmp = tcg_temp_new();
+
+ /* add base and offset to get address of bhrb entry */
+ tcg_gen_add_tl(tmp, base, offset);
+
+ /* store value into bhrb at bhrb_offset */
+ tcg_gen_st_i64(value, (TCGv_ptr)tmp, 0);
+
+ /* add 8 to current bhrb_offset */
+ tcg_gen_addi_tl(offset, offset, 8);
+
+ /* apply offset mask */
+ tcg_gen_and_tl(offset, offset, mask);
+
+ return offset;
+}
+
+static inline void gen_update_branch_history(DisasContext *ctx,
+ target_ulong nip,
+ TCGv target,
+ target_long inst_type)
{
#if defined(TARGET_PPC64)
+ TCGv base;
+ TCGv tmp;
+ TCGv offset;
+ TCGv mask;
+ TCGLabel *no_update;
+
if (ctx->has_cfar) {
tcg_gen_movi_tl(cpu_cfar, nip);
}
+
+ if (!ctx->has_bhrb ||
+ !ctx->bhrb_enable ||
+ inst_type == BHRB_TYPE_NORECORD) {
+ return;
+ }
+
+ tmp = tcg_temp_new();
+ no_update = gen_new_label();
+
+ /* check for bhrb filtering */
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUPPCState, bhrb_filter));
+ tcg_gen_andi_tl(tmp, tmp, inst_type);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, 0, no_update);
+
+ base = tcg_temp_new();
+ offset = tcg_temp_new();
+ mask = tcg_temp_new();
+
+ /* load bhrb base address */
+ tcg_gen_ld_tl(base, cpu_env, offsetof(CPUPPCState, bhrb_base));
+
+ /* load current bhrb_offset */
+ tcg_gen_ld_tl(offset, cpu_env, offsetof(CPUPPCState, bhrb_offset));
+
+ /* load a BHRB offset mask */
+ tcg_gen_ld_tl(mask, cpu_env, offsetof(CPUPPCState, bhrb_offset_mask));
+
+ offset = gen_write_bhrb(base, offset, mask, tcg_constant_i64(nip));
+
+ /* Also record the target address for XL-Form branches */
+ if (inst_type & BHRB_TYPE_XL_FORM) {
+
+ /* Set the 'T' bit for target entries */
+ tcg_gen_ori_tl(tmp, target, 0x2);
+
+ offset = gen_write_bhrb(base, offset, mask, tmp);
+ }
+
+ /* save updated bhrb_offset for next time */
+ tcg_gen_st_tl(offset, cpu_env, offsetof(CPUPPCState, bhrb_offset));
+
+ gen_set_label(no_update);
#endif
}
@@ -4265,8 +4337,10 @@ static void gen_b(DisasContext *ctx)
}
if (LK(ctx->opcode)) {
gen_setlr(ctx, ctx->base.pc_next);
+ gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL);
+ } else {
+ gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER);
}
- gen_update_cfar(ctx, ctx->cia);
gen_goto_tb(ctx, 0, target);
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -4281,6 +4355,7 @@ static void gen_bcond(DisasContext *ctx, int type)
uint32_t bo = BO(ctx->opcode);
TCGLabel *l1;
TCGv target;
+ target_long bhrb_type = BHRB_TYPE_OTHER;
if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
target = tcg_temp_new();
@@ -4291,11 +4366,16 @@ static void gen_bcond(DisasContext *ctx, int type)
} else {
tcg_gen_mov_tl(target, cpu_lr);
}
+ if (!LK(ctx->opcode)) {
+ bhrb_type |= BHRB_TYPE_INDIRECT;
+ }
+ bhrb_type |= BHRB_TYPE_XL_FORM;
} else {
target = NULL;
}
if (LK(ctx->opcode)) {
gen_setlr(ctx, ctx->base.pc_next);
+ bhrb_type |= BHRB_TYPE_CALL;
}
l1 = gen_new_label();
if ((bo & 0x4) == 0) {
@@ -4346,6 +4426,7 @@ static void gen_bcond(DisasContext *ctx, int type)
tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
}
}
+ bhrb_type |= BHRB_TYPE_COND;
}
if ((bo & 0x10) == 0) {
/* Test CR */
@@ -4360,8 +4441,11 @@ static void gen_bcond(DisasContext *ctx, int type)
tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
}
+ bhrb_type |= BHRB_TYPE_COND;
}
- gen_update_cfar(ctx, ctx->cia);
+
+ gen_update_branch_history(ctx, ctx->cia, target, bhrb_type);
+
if (type == BCOND_IM) {
target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
if (likely(AA(ctx->opcode) == 0)) {
@@ -4477,7 +4561,7 @@ static void gen_rfi(DisasContext *ctx)
/* Restore CPU state */
CHK_SV(ctx);
translator_io_start(&ctx->base);
- gen_update_cfar(ctx, ctx->cia);
+ gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD);
gen_helper_rfi(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
#endif
@@ -4492,7 +4576,7 @@ static void gen_rfid(DisasContext *ctx)
/* Restore CPU state */
CHK_SV(ctx);
translator_io_start(&ctx->base);
- gen_update_cfar(ctx, ctx->cia);
+ gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD);
gen_helper_rfid(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
#endif
@@ -4507,7 +4591,7 @@ static void gen_rfscv(DisasContext *ctx)
/* Restore CPU state */
CHK_SV(ctx);
translator_io_start(&ctx->base);
- gen_update_cfar(ctx, ctx->cia);
+ gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD);
gen_helper_rfscv(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
#endif
@@ -7339,6 +7423,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
#if defined(TARGET_PPC64)
ctx->sf_mode = (hflags >> HFLAGS_64) & 1;
ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
+ ctx->has_bhrb = !!(env->flags & POWERPC_FLAG_BHRB);
#endif
ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
|| env->mmu_model & POWERPC_MMU_64;
diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/branch-impl.c.inc
index f9931b9d73..a76ec6f77e 100644
--- a/target/ppc/translate/branch-impl.c.inc
+++ b/target/ppc/translate/branch-impl.c.inc
@@ -17,7 +17,7 @@ static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg)
REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
translator_io_start(&ctx->base);
- gen_update_cfar(ctx, ctx->cia);
+ gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD);
gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]);
ctx->base.is_jmp = DISAS_CHAIN;
--
2.31.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 2/4] target/ppc: Add recording of taken branches to BHRB
2023-09-25 17:43 ` [PATCH v3 2/4] target/ppc: Add recording of taken branches to BHRB Glenn Miles
@ 2024-02-05 8:37 ` Nicholas Piggin
0 siblings, 0 replies; 11+ messages in thread
From: Nicholas Piggin @ 2024-02-05 8:37 UTC (permalink / raw)
To: Glenn Miles, qemu-ppc
Cc: qemu-devel, Daniel Henrique Barboza, Cédric Le Goater,
David Gibson
On Tue Sep 26, 2023 at 3:43 AM AEST, Glenn Miles wrote:
> This commit continues adding support for the Branch History
> Rolling Buffer (BHRB) as is provided starting with the P8
> processor and continuing with its successors. This commit
> is limited to the recording and filtering of taken branches.
>
> The following changes were made:
>
> - Enabled functionality on P10 processors only due to
> performance impact seen with P8 and P9 where it is not
> disabled for non problem state branches.
> - Added a BHRB buffer for storing branch instruction and
> target addresses for taken branches
> - Renamed gen_update_cfar to gen_update_branch_history and
> added a 'target' parameter to hold the branch target
> address and 'inst_type' parameter to use for filtering
> - Added TCG code to gen_update_branch_history that stores
> data to the BHRB and updates the BHRB offset.
> - Added BHRB resource initialization and reset functions
>
> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
> ---
> +static inline void gen_update_branch_history(DisasContext *ctx,
> + target_ulong nip,
> + TCGv target,
> + target_long inst_type)
> {
> #if defined(TARGET_PPC64)
> + TCGv base;
> + TCGv tmp;
> + TCGv offset;
> + TCGv mask;
> + TCGLabel *no_update;
> +
> if (ctx->has_cfar) {
> tcg_gen_movi_tl(cpu_cfar, nip);
> }
> +
> + if (!ctx->has_bhrb ||
> + !ctx->bhrb_enable ||
> + inst_type == BHRB_TYPE_NORECORD) {
> + return;
> + }
BTW while debugging what turned out to be a mismerge, I removed has_bhrb
because bhrb_enable is always a subset. Shout if you have an objection.
Thanks,
Nick
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 3/4] target/ppc: Add clrbhrb and mfbhrbe instructions
2023-09-25 17:43 [PATCH v3 0/4] Add BHRB Facility Support Glenn Miles
2023-09-25 17:43 ` [PATCH v3 1/4] target/ppc: Add new hflags to support BHRB Glenn Miles
2023-09-25 17:43 ` [PATCH v3 2/4] target/ppc: Add recording of taken branches to BHRB Glenn Miles
@ 2023-09-25 17:43 ` Glenn Miles
2023-09-25 17:43 ` [PATCH v3 4/4] target/ppc: Add migration support for BHRB Glenn Miles
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Glenn Miles @ 2023-09-25 17:43 UTC (permalink / raw)
To: qemu-ppc
Cc: Glenn Miles, qemu-devel, Daniel Henrique Barboza,
Cédric Le Goater, Nicholas Piggin, David Gibson
Add support for the clrbhrb and mfbhrbe instructions.
Since neither instruction is believed to be critical to
performance, both instructions were implemented using helper
functions.
Access to both instructions is controlled by bits in the
HFSCR (for privileged state) and MMCR0 (for problem state).
A new function, helper_mmcr0_facility_check, was added for
checking MMCR0[BHRBA] and raising a facility_unavailable exception
if required.
NOTE: For P8 and P9, due to a performance issue, branch history will
not be kept, but the instructions will be allowed to execute
as normal with the exception that the mfbhrbe instruction will
always return a zero value.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
---
target/ppc/cpu.h | 2 ++
target/ppc/helper.h | 4 +++
target/ppc/insn32.decode | 8 +++++
target/ppc/misc_helper.c | 46 ++++++++++++++++++++++++++++
target/ppc/translate.c | 2 ++
target/ppc/translate/bhrb-impl.c.inc | 43 ++++++++++++++++++++++++++
6 files changed, 105 insertions(+)
create mode 100644 target/ppc/translate/bhrb-impl.c.inc
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 396b1f1a6c..15326c4d40 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -441,6 +441,7 @@ FIELD(MSR, LE, MSR_LE, 1)
#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */
#define MMCR0_FCP PPC_BIT(34) /* Freeze Counters/BHRB if PR=1 */
#define MMCR0_FCPC PPC_BIT(51) /* Condition for FCP bit */
+#define MMCR0_BHRBA_NR PPC_BIT_NR(42) /* BHRB Available */
/* MMCR0 userspace r/w mask */
#define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
/* MMCR2 userspace r/w mask */
@@ -540,6 +541,7 @@ FIELD(MSR, LE, MSR_LE, 1)
/* HFSCR bits */
#define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
+#define HFSCR_BHRB PPC_BIT(59) /* BHRB Instructions */
#define HFSCR_IC_MSGP 0xA
#define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 3df360efe9..a62d32d786 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -820,3 +820,7 @@ DEF_HELPER_4(DSCLIQ, void, env, fprp, fprp, i32)
DEF_HELPER_1(tbegin, void, env)
DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, env)
+
+DEF_HELPER_1(clrbhrb, void, env)
+DEF_HELPER_FLAGS_2(mfbhrbe, TCG_CALL_NO_WG, i64, env, i32)
+
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 4fcf3af8d0..00d3ddda02 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -972,3 +972,11 @@ MSGSND 011111 ----- ----- ..... 0011001110 - @X_rb
MSGCLRP 011111 ----- ----- ..... 0010101110 - @X_rb
MSGSNDP 011111 ----- ----- ..... 0010001110 - @X_rb
MSGSYNC 011111 ----- ----- ----- 1101110110 -
+
+# Branch History Rolling Buffer (BHRB) Instructions
+
+&XFX_bhrbe rt bhrbe
+@XFX_bhrbe ...... rt:5 bhrbe:10 .......... - &XFX_bhrbe
+
+MFBHRBE 011111 ..... ..... ..... 0100101110 - @XFX_bhrbe
+CLRBHRB 011111 ----- ----- ----- 0110101110 -
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index a05bdf78c9..866b064b3d 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -139,6 +139,17 @@ void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
#endif
}
+static void helper_mmcr0_facility_check(CPUPPCState *env, uint32_t bit,
+ uint32_t sprn, uint32_t cause)
+{
+#ifdef TARGET_PPC64
+ if (FIELD_EX64(env->msr, MSR, PR) &&
+ !(env->spr[SPR_POWER_MMCR0] & (1ULL << bit))) {
+ raise_fu_exception(env, bit, sprn, cause, GETPC());
+ }
+#endif
+}
+
void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
uint32_t sprn, uint32_t cause)
{
@@ -366,3 +377,38 @@ void helper_fixup_thrm(CPUPPCState *env)
env->spr[i] = v;
}
}
+
+void helper_clrbhrb(CPUPPCState *env)
+{
+ helper_hfscr_facility_check(env, HFSCR_BHRB, "clrbhrb", FSCR_IC_BHRB);
+
+ helper_mmcr0_facility_check(env, MMCR0_BHRBA_NR, 0, FSCR_IC_BHRB);
+
+ if (env->flags & POWERPC_FLAG_BHRB) {
+ memset(env->bhrb, 0, sizeof(env->bhrb));
+ }
+}
+
+uint64_t helper_mfbhrbe(CPUPPCState *env, uint32_t bhrbe)
+{
+ unsigned int index;
+
+ helper_hfscr_facility_check(env, HFSCR_BHRB, "mfbhrbe", FSCR_IC_BHRB);
+
+ helper_mmcr0_facility_check(env, MMCR0_BHRBA_NR, 0, FSCR_IC_BHRB);
+
+ if (!(env->flags & POWERPC_FLAG_BHRB) ||
+ (bhrbe >= env->bhrb_num_entries) ||
+ (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE)) {
+ return 0;
+ }
+
+ /*
+ * Note: bhrb_offset is the byte offset for writing the
+ * next entry (over the oldest entry), which is why we
+ * must offset bhrbe by 1 to get to the 0th entry.
+ */
+ index = ((env->bhrb_offset / sizeof(uint64_t)) - (bhrbe + 1)) %
+ env->bhrb_num_entries;
+ return env->bhrb[index];
+}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5f0c79923f..68a8395a23 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6505,6 +6505,8 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
#include "translate/storage-ctrl-impl.c.inc"
+#include "translate/bhrb-impl.c.inc"
+
/* Handles lfdp */
static void gen_dform39(DisasContext *ctx)
{
diff --git a/target/ppc/translate/bhrb-impl.c.inc b/target/ppc/translate/bhrb-impl.c.inc
new file mode 100644
index 0000000000..fd09f444f5
--- /dev/null
+++ b/target/ppc/translate/bhrb-impl.c.inc
@@ -0,0 +1,43 @@
+/*
+ * Power ISA Decode For BHRB Instructions
+ *
+ * Copyright IBM Corp. 2023
+ *
+ * Authors:
+ * Glenn Miles <milesg@linux.vnet.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+
+static bool trans_MFBHRBE(DisasContext *ctx, arg_XFX_bhrbe *arg)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
+ TCGv_i32 bhrbe = tcg_constant_i32(arg->bhrbe);
+ gen_helper_mfbhrbe(cpu_gpr[arg->rt], cpu_env, bhrbe);
+ return true;
+}
+
+static bool trans_CLRBHRB(DisasContext *ctx, arg_CLRBHRB *arg)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
+ gen_helper_clrbhrb(cpu_env);
+ return true;
+}
+
+#else
+
+static bool trans_MFBHRBE(DisasContext *ctx, arg_XFX_bhrbe *arg)
+{
+ gen_invalid(ctx);
+ return true;
+}
+
+static bool trans_CLRBHRB(DisasContext *ctx, arg_CLRBHRB *arg)
+{
+ gen_invalid(ctx);
+ return true;
+}
+#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 4/4] target/ppc: Add migration support for BHRB
2023-09-25 17:43 [PATCH v3 0/4] Add BHRB Facility Support Glenn Miles
` (2 preceding siblings ...)
2023-09-25 17:43 ` [PATCH v3 3/4] target/ppc: Add clrbhrb and mfbhrbe instructions Glenn Miles
@ 2023-09-25 17:43 ` Glenn Miles
2023-10-18 15:06 ` [PATCH v3 0/4] Add BHRB Facility Support Nicholas Piggin
2024-02-05 8:05 ` Nicholas Piggin
5 siblings, 0 replies; 11+ messages in thread
From: Glenn Miles @ 2023-09-25 17:43 UTC (permalink / raw)
To: qemu-ppc
Cc: Glenn Miles, qemu-devel, Daniel Henrique Barboza,
Cédric Le Goater, Nicholas Piggin, David Gibson
Adds migration support for Branch History Rolling
Buffer (BHRB) internal state.
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
---
target/ppc/machine.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index d42e475bfb..ba328ad5e2 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -711,6 +711,26 @@ static const VMStateDescription vmstate_reservation = {
}
};
+#ifdef TARGET_PPC64
+static bool bhrb_needed(void *opaque)
+{
+ PowerPCCPU *cpu = opaque;
+ return (cpu->env.flags & POWERPC_FLAG_BHRB) != 0;
+}
+
+static const VMStateDescription vmstate_bhrb = {
+ .name = "cpu/bhrb",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = bhrb_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(env.bhrb_offset, PowerPCCPU),
+ VMSTATE_UINT64_ARRAY(env.bhrb, PowerPCCPU, BHRB_MAX_NUM_ENTRIES),
+ VMSTATE_END_OF_LIST()
+ }
+};
+#endif
+
const VMStateDescription vmstate_ppc_cpu = {
.name = "cpu",
.version_id = 5,
@@ -756,6 +776,7 @@ const VMStateDescription vmstate_ppc_cpu = {
#ifdef TARGET_PPC64
&vmstate_tm,
&vmstate_slb,
+ &vmstate_bhrb,
#endif /* TARGET_PPC64 */
&vmstate_tlb6xx,
&vmstate_tlbemb,
--
2.31.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 0/4] Add BHRB Facility Support
2023-09-25 17:43 [PATCH v3 0/4] Add BHRB Facility Support Glenn Miles
` (3 preceding siblings ...)
2023-09-25 17:43 ` [PATCH v3 4/4] target/ppc: Add migration support for BHRB Glenn Miles
@ 2023-10-18 15:06 ` Nicholas Piggin
2023-10-18 15:59 ` Miles Glenn
2024-02-05 8:05 ` Nicholas Piggin
5 siblings, 1 reply; 11+ messages in thread
From: Nicholas Piggin @ 2023-10-18 15:06 UTC (permalink / raw)
To: Glenn Miles, qemu-ppc
Cc: qemu-devel, Daniel Henrique Barboza, Cédric Le Goater,
David Gibson
On Tue Sep 26, 2023 at 3:43 AM AEST, Glenn Miles wrote:
> This is a series of patches for adding support for the Branch History
> Rolling Buffer (BHRB) facility. This was added to the Power ISA
> starting with version 2.07. Changes were subsequently made in version
> 3.1 to limit BHRB recording to instructions run in problem state only
> and to add a control bit to disable recording (MMCRA[BHRBRD]).
>
> Version 3 of this series disables branch recording on P8 and P9 due
> to a drop in performance caused by recording branches outside of
> problem state.
Thanks for these, they all look good to me.
With P10 CPU, Linux perf branch recording appears to work with this
series, and I confirmed that Linux does disable BHRB in MMCRA at
boot, so it should not take the performance hit.
It had a couple of compile bugs, no matter I fixed them, but I often
trip overppc32 and user-mode when working on TCG too, so building
with --target-list including ppc64-softmmu,ppc-softmmu,
ppc64-linux-user,ppc64le-linux-user,ppc-linux-user is good to catch
those.
Thanks,
Nick
>
> Glenn Miles (4):
> target/ppc: Add new hflags to support BHRB
> target/ppc: Add recording of taken branches to BHRB
> target/ppc: Add clrbhrb and mfbhrbe instructions
> target/ppc: Add migration support for BHRB
>
> target/ppc/cpu.h | 24 ++++++
> target/ppc/cpu_init.c | 39 +++++++++-
> target/ppc/helper.h | 5 ++
> target/ppc/helper_regs.c | 35 +++++++++
> target/ppc/insn32.decode | 8 ++
> target/ppc/machine.c | 23 +++++-
> target/ppc/misc_helper.c | 46 +++++++++++
> target/ppc/power8-pmu-regs.c.inc | 5 ++
> target/ppc/power8-pmu.c | 48 +++++++++++-
> target/ppc/power8-pmu.h | 11 ++-
> target/ppc/spr_common.h | 1 +
> target/ppc/translate.c | 101 +++++++++++++++++++++++--
> target/ppc/translate/bhrb-impl.c.inc | 43 +++++++++++
> target/ppc/translate/branch-impl.c.inc | 2 +-
> 14 files changed, 374 insertions(+), 17 deletions(-)
> create mode 100644 target/ppc/translate/bhrb-impl.c.inc
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v3 0/4] Add BHRB Facility Support
2023-10-18 15:06 ` [PATCH v3 0/4] Add BHRB Facility Support Nicholas Piggin
@ 2023-10-18 15:59 ` Miles Glenn
2023-11-27 20:51 ` Miles Glenn
0 siblings, 1 reply; 11+ messages in thread
From: Miles Glenn @ 2023-10-18 15:59 UTC (permalink / raw)
To: Nicholas Piggin, qemu-ppc
Cc: qemu-devel, Daniel Henrique Barboza, Cédric Le Goater,
David Gibson
On Thu, 2023-10-19 at 01:06 +1000, Nicholas Piggin wrote:
> On Tue Sep 26, 2023 at 3:43 AM AEST, Glenn Miles wrote:
> > This is a series of patches for adding support for the Branch
> > History
> > Rolling Buffer (BHRB) facility. This was added to the Power ISA
> > starting with version 2.07. Changes were subsequently made in
> > version
> > 3.1 to limit BHRB recording to instructions run in problem state
> > only
> > and to add a control bit to disable recording (MMCRA[BHRBRD]).
> >
> > Version 3 of this series disables branch recording on P8 and P9 due
> > to a drop in performance caused by recording branches outside of
> > problem state.
>
> Thanks for these, they all look good to me.
>
> With P10 CPU, Linux perf branch recording appears to work with this
> series, and I confirmed that Linux does disable BHRB in MMCRA at
> boot, so it should not take the performance hit.
>
> It had a couple of compile bugs, no matter I fixed them, but I often
> trip overppc32 and user-mode when working on TCG too, so building
> with --target-list including ppc64-softmmu,ppc-softmmu,
> ppc64-linux-user,ppc64le-linux-user,ppc-linux-user is good to catch
> those.
>
> Thanks,
> Nick
>
Thanks, Nick. I'll have to remember that for next time!
Glenn
> > Glenn Miles (4):
> > target/ppc: Add new hflags to support BHRB
> > target/ppc: Add recording of taken branches to BHRB
> > target/ppc: Add clrbhrb and mfbhrbe instructions
> > target/ppc: Add migration support for BHRB
> >
> > target/ppc/cpu.h | 24 ++++++
> > target/ppc/cpu_init.c | 39 +++++++++-
> > target/ppc/helper.h | 5 ++
> > target/ppc/helper_regs.c | 35 +++++++++
> > target/ppc/insn32.decode | 8 ++
> > target/ppc/machine.c | 23 +++++-
> > target/ppc/misc_helper.c | 46 +++++++++++
> > target/ppc/power8-pmu-regs.c.inc | 5 ++
> > target/ppc/power8-pmu.c | 48 +++++++++++-
> > target/ppc/power8-pmu.h | 11 ++-
> > target/ppc/spr_common.h | 1 +
> > target/ppc/translate.c | 101
> > +++++++++++++++++++++++--
> > target/ppc/translate/bhrb-impl.c.inc | 43 +++++++++++
> > target/ppc/translate/branch-impl.c.inc | 2 +-
> > 14 files changed, 374 insertions(+), 17 deletions(-)
> > create mode 100644 target/ppc/translate/bhrb-impl.c.inc
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 0/4] Add BHRB Facility Support
2023-10-18 15:59 ` Miles Glenn
@ 2023-11-27 20:51 ` Miles Glenn
2023-11-28 1:50 ` Nicholas Piggin
0 siblings, 1 reply; 11+ messages in thread
From: Miles Glenn @ 2023-11-27 20:51 UTC (permalink / raw)
To: Nicholas Piggin, qemu-ppc
Cc: qemu-devel, Daniel Henrique Barboza, Cédric Le Goater,
David Gibson
On Wed, 2023-10-18 at 10:59 -0500, Miles Glenn wrote:
> On Thu, 2023-10-19 at 01:06 +1000, Nicholas Piggin wrote:
> > On Tue Sep 26, 2023 at 3:43 AM AEST, Glenn Miles wrote:
> > > This is a series of patches for adding support for the Branch
> > > History
> > > Rolling Buffer (BHRB) facility. This was added to the Power ISA
> > > starting with version 2.07. Changes were subsequently made in
> > > version
> > > 3.1 to limit BHRB recording to instructions run in problem state
> > > only
> > > and to add a control bit to disable recording (MMCRA[BHRBRD]).
> > >
> > > Version 3 of this series disables branch recording on P8 and P9
> > > due
> > > to a drop in performance caused by recording branches outside of
> > > problem state.
> >
> > Thanks for these, they all look good to me.
> >
> > With P10 CPU, Linux perf branch recording appears to work with this
> > series, and I confirmed that Linux does disable BHRB in MMCRA at
> > boot, so it should not take the performance hit.
> >
> > It had a couple of compile bugs, no matter I fixed them, but I
> > often
> > trip overppc32 and user-mode when working on TCG too, so building
> > with --target-list including ppc64-softmmu,ppc-softmmu,
> > ppc64-linux-user,ppc64le-linux-user,ppc-linux-user is good to catch
> > those.
> >
> > Thanks,
> > Nick
> >
>
> Thanks, Nick. I'll have to remember that for next time!
>
> Glenn
>
Hi Nick,
Is there anything else you need me to do for this series to be merged?
Thanks,
Glenn
> > > Glenn Miles (4):
> > > target/ppc: Add new hflags to support BHRB
> > > target/ppc: Add recording of taken branches to BHRB
> > > target/ppc: Add clrbhrb and mfbhrbe instructions
> > > target/ppc: Add migration support for BHRB
> > >
> > > target/ppc/cpu.h | 24 ++++++
> > > target/ppc/cpu_init.c | 39 +++++++++-
> > > target/ppc/helper.h | 5 ++
> > > target/ppc/helper_regs.c | 35 +++++++++
> > > target/ppc/insn32.decode | 8 ++
> > > target/ppc/machine.c | 23 +++++-
> > > target/ppc/misc_helper.c | 46 +++++++++++
> > > target/ppc/power8-pmu-regs.c.inc | 5 ++
> > > target/ppc/power8-pmu.c | 48 +++++++++++-
> > > target/ppc/power8-pmu.h | 11 ++-
> > > target/ppc/spr_common.h | 1 +
> > > target/ppc/translate.c | 101
> > > +++++++++++++++++++++++--
> > > target/ppc/translate/bhrb-impl.c.inc | 43 +++++++++++
> > > target/ppc/translate/branch-impl.c.inc | 2 +-
> > > 14 files changed, 374 insertions(+), 17 deletions(-)
> > > create mode 100644 target/ppc/translate/bhrb-impl.c.inc
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 0/4] Add BHRB Facility Support
2023-11-27 20:51 ` Miles Glenn
@ 2023-11-28 1:50 ` Nicholas Piggin
0 siblings, 0 replies; 11+ messages in thread
From: Nicholas Piggin @ 2023-11-28 1:50 UTC (permalink / raw)
To: Miles Glenn, qemu-ppc
Cc: qemu-devel, Daniel Henrique Barboza, Cédric Le Goater,
David Gibson
On Tue Nov 28, 2023 at 6:51 AM AEST, Miles Glenn wrote:
> On Wed, 2023-10-18 at 10:59 -0500, Miles Glenn wrote:
> > On Thu, 2023-10-19 at 01:06 +1000, Nicholas Piggin wrote:
> > > On Tue Sep 26, 2023 at 3:43 AM AEST, Glenn Miles wrote:
> > > > This is a series of patches for adding support for the Branch
> > > > History
> > > > Rolling Buffer (BHRB) facility. This was added to the Power ISA
> > > > starting with version 2.07. Changes were subsequently made in
> > > > version
> > > > 3.1 to limit BHRB recording to instructions run in problem state
> > > > only
> > > > and to add a control bit to disable recording (MMCRA[BHRBRD]).
> > > >
> > > > Version 3 of this series disables branch recording on P8 and P9
> > > > due
> > > > to a drop in performance caused by recording branches outside of
> > > > problem state.
> > >
> > > Thanks for these, they all look good to me.
> > >
> > > With P10 CPU, Linux perf branch recording appears to work with this
> > > series, and I confirmed that Linux does disable BHRB in MMCRA at
> > > boot, so it should not take the performance hit.
> > >
> > > It had a couple of compile bugs, no matter I fixed them, but I
> > > often
> > > trip overppc32 and user-mode when working on TCG too, so building
> > > with --target-list including ppc64-softmmu,ppc-softmmu,
> > > ppc64-linux-user,ppc64le-linux-user,ppc-linux-user is good to catch
> > > those.
> > >
> > > Thanks,
> > > Nick
> > >
> >
> > Thanks, Nick. I'll have to remember that for next time!
> >
> > Glenn
> >
>
> Hi Nick,
>
> Is there anything else you need me to do for this series to be merged?
Hey Glenn,
No, sorry I just missed this cycle. I have it queued up, it'll have to
go in after 8.2 release.
Thanks,
Nick
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3 0/4] Add BHRB Facility Support
2023-09-25 17:43 [PATCH v3 0/4] Add BHRB Facility Support Glenn Miles
` (4 preceding siblings ...)
2023-10-18 15:06 ` [PATCH v3 0/4] Add BHRB Facility Support Nicholas Piggin
@ 2024-02-05 8:05 ` Nicholas Piggin
5 siblings, 0 replies; 11+ messages in thread
From: Nicholas Piggin @ 2024-02-05 8:05 UTC (permalink / raw)
To: Glenn Miles, qemu-ppc
Cc: qemu-devel, Daniel Henrique Barboza, Cédric Le Goater,
David Gibson
On Tue Sep 26, 2023 at 3:43 AM AEST, Glenn Miles wrote:
> This is a series of patches for adding support for the Branch History
> Rolling Buffer (BHRB) facility. This was added to the Power ISA
> starting with version 2.07. Changes were subsequently made in version
> 3.1 to limit BHRB recording to instructions run in problem state only
> and to add a control bit to disable recording (MMCRA[BHRBRD]).
>
> Version 3 of this series disables branch recording on P8 and P9 due
> to a drop in performance caused by recording branches outside of
> problem state.
For this series,
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
I finally got around to adding powerpc MMU support to kvm unit tests,
so userspace and basic BHRB tests weren't much more work. Easier than
testing it with perf in Linux!
https://gitlab.com/npiggin/kvm-unit-tests.git powerpc
Thanks,
Nick
>
> Glenn Miles (4):
> target/ppc: Add new hflags to support BHRB
> target/ppc: Add recording of taken branches to BHRB
> target/ppc: Add clrbhrb and mfbhrbe instructions
> target/ppc: Add migration support for BHRB
>
> target/ppc/cpu.h | 24 ++++++
> target/ppc/cpu_init.c | 39 +++++++++-
> target/ppc/helper.h | 5 ++
> target/ppc/helper_regs.c | 35 +++++++++
> target/ppc/insn32.decode | 8 ++
> target/ppc/machine.c | 23 +++++-
> target/ppc/misc_helper.c | 46 +++++++++++
> target/ppc/power8-pmu-regs.c.inc | 5 ++
> target/ppc/power8-pmu.c | 48 +++++++++++-
> target/ppc/power8-pmu.h | 11 ++-
> target/ppc/spr_common.h | 1 +
> target/ppc/translate.c | 101 +++++++++++++++++++++++--
> target/ppc/translate/bhrb-impl.c.inc | 43 +++++++++++
> target/ppc/translate/branch-impl.c.inc | 2 +-
> 14 files changed, 374 insertions(+), 17 deletions(-)
> create mode 100644 target/ppc/translate/bhrb-impl.c.inc
^ permalink raw reply [flat|nested] 11+ messages in thread