From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: kbastian@mail.uni-paderborn.de,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PULL 09/21] target/tricore: Swap src and dst reg for RCRR_INSERT
Date: Wed, 27 Sep 2023 11:35:40 +0200 [thread overview]
Message-ID: <20230927093552.493279-10-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20230927093552.493279-1-kbastian@mail.uni-paderborn.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-10-kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 8 ++++----
tests/tcg/tricore/asm/macros.h | 9 +++++++++
tests/tcg/tricore/asm/test_insert.S | 5 +++++
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 3f950ae33b..7aba7b067c 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8223,12 +8223,12 @@ static void decode_32Bit_opc(DisasContext *ctx)
temp2 = tcg_temp_new(); /* width*/
temp3 = tcg_temp_new(); /* pos */
- CHECK_REG_PAIR(r3);
+ CHECK_REG_PAIR(r2);
- tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
- tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
+ tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f);
+ tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f);
- gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
+ gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3);
break;
/* RCRW Format */
case OPCM_32_RCRW_MASK_INSERT:
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 51f6191ef2..17e696bef5 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -169,6 +169,15 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2; \
)
+#define TEST_D_DIE(insn, num, result, rs1, imm1, rs2_lo, rs2_hi)\
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(EREG_RS2_LO, rs2_lo); \
+ LI(EREG_RS2_HI, rs2_hi); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, imm1, EREG_RS2; \
+ )
+
#define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
diff --git a/tests/tcg/tricore/asm/test_insert.S b/tests/tcg/tricore/asm/test_insert.S
index 3978810121..223d7ce796 100644
--- a/tests/tcg/tricore/asm/test_insert.S
+++ b/tests/tcg/tricore/asm/test_insert.S
@@ -15,4 +15,9 @@ _start:
# | | | | | | |
TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
+# insn num result rs1 imm1 rs2_h rs2_l
+# | | | | | | |
+ TEST_D_DIE(insert, 5, 0xe30c308d, 0xe30c308d ,0x3 , 0x00000000 ,0x00000000)
+ TEST_D_DIE(insert, 6, 0x669b0120, 0x669b2820 ,0x2 , 0x5530a1c7 ,0x3a2b0f67)
+
TEST_PASSFAIL
--
2.42.0
next prev parent reply other threads:[~2023-09-27 9:38 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-27 9:35 [PULL 00/21] tricore queue Bastian Koppelmann
2023-09-27 9:35 ` [PULL 01/21] tests/tcg/tricore: Bump cpu to tc37x Bastian Koppelmann
2023-09-27 9:35 ` [PULL 02/21] target/tricore: Implement CRCN insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 03/21] target/tricore: Correctly handle FPU RM from PSW Bastian Koppelmann
2023-09-27 9:35 ` [PULL 04/21] target/tricore: Implement FTOU insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 05/21] target/tricore: Clarify special case for FTOUZ insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 06/21] target/tricore: Implement ftohp insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 07/21] target/tricore: Implement hptof insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 08/21] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 Bastian Koppelmann
2023-09-27 9:35 ` Bastian Koppelmann [this message]
2023-09-27 9:35 ` [PULL 10/21] target/tricore: Replace cpu_*_code with translator_* Bastian Koppelmann
2023-09-27 9:35 ` [PULL 11/21] target/tricore: Fix FTOUZ being ISA v1.3.1 up Bastian Koppelmann
2023-09-27 9:35 ` [PULL 12/21] tests/tcg/tricore: Extended and non-extened regs now match Bastian Koppelmann
2023-09-27 9:35 ` [PULL 13/21] hw/tricore: Log failing test in testdevice Bastian Koppelmann
2023-09-27 9:35 ` [PULL 14/21] tests/tcg: Reset result register after each test Bastian Koppelmann
2023-09-27 9:35 ` [PULL 15/21] tests/tcg/tricore: Add test for all arith insns up to addx Bastian Koppelmann
2023-09-27 9:35 ` [PULL 16/21] tests/tcg/tricore: Add test from 'and' to 'csub' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 17/21] tests/tcg/tricore: Add test from 'dextr' to 'lt' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 18/21] tests/tcg/tricore: Add test from 'max' to 'shas' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 19/21] tests/tcg/tricore: Add test from 'shuffle' to 'xor.t' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 20/21] target/tricore: Remove CSFRs from cpu.h Bastian Koppelmann
2023-09-27 9:35 ` [PULL 21/21] target/tricore: Change effective address (ea) to target_ulong Bastian Koppelmann
2023-09-27 17:40 ` [PULL 00/21] tricore queue Bastian Koppelmann
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