[PULL 00/21] tricore queue

[PULL 00/21] tricore queue

[Bastian Koppelmann]

The following changes since commit 11a629d246e4e7785a6f0efb99bd15a32c04feda:

  Merge tag 'pull-nbd-2023-09-25' of https://repo.or.cz/qemu/ericb into staging (2023-09-26 09:04:23 -0400)

are available in the Git repository at:

  https://github.com/bkoppelmann/qemu.git tags/pull-tricore-20230927

for you to fetch changes up to 32dd1f0b4bf5f38f37434b0c8fe6c8d86e093b2b:

  target/tricore: Change effective address (ea) to target_ulong (2023-09-27 11:22:42 +0200)

----------------------------------------------------------------
- Add FTOU, CRCN, FTOHP, and HPTOF insns
- Add test for arithmetic TriCore insns

----------------------------------------------------------------
Bastian Koppelmann (21):
      tests/tcg/tricore: Bump cpu to tc37x
      target/tricore: Implement CRCN insn
      target/tricore: Correctly handle FPU RM from PSW
      target/tricore: Implement FTOU insn
      target/tricore: Clarify special case for FTOUZ insn
      target/tricore: Implement ftohp insn
      target/tricore: Implement hptof insn
      target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
      target/tricore: Swap src and dst reg for RCRR_INSERT
      target/tricore: Replace cpu_*_code with translator_*
      target/tricore: Fix FTOUZ being ISA v1.3.1 up
      tests/tcg/tricore: Extended and non-extened regs now match
      hw/tricore: Log failing test in testdevice
      tests/tcg: Reset result register after each test
      tests/tcg/tricore: Add test for all arith insns up to addx
      tests/tcg/tricore: Add test from 'and' to 'csub'
      tests/tcg/tricore: Add test from 'dextr' to 'lt'
      tests/tcg/tricore: Add test from 'max' to 'shas'
      tests/tcg/tricore: Add test from 'shuffle' to 'xor.t'
      target/tricore: Remove CSFRs from cpu.h
      target/tricore: Change effective address (ea) to target_ulong

 hw/tricore/tricore_testdevice.c           |   4 +
 target/tricore/cpu.h                      | 143 +--------------
 target/tricore/fpu_helper.c               | 111 ++++++++++++
 target/tricore/helper.c                   |  19 +-
 target/tricore/helper.h                   |   4 +
 target/tricore/op_helper.c                |  79 ++++++++-
 target/tricore/translate.c                |  56 ++++--
 target/tricore/tricore-opcodes.h          |   3 +
 tests/tcg/tricore/Makefile.softmmu-target |   7 +-
 tests/tcg/tricore/asm/macros.h            | 190 +++++++++++++++++---
 tests/tcg/tricore/asm/sas.py              |  21 +++
 tests/tcg/tricore/asm/test_arith.S        | 280 ++++++++++++++++++++++++++++++
 tests/tcg/tricore/asm/test_crcn.S         |   9 +
 tests/tcg/tricore/asm/test_ftohp.S        |  14 ++
 tests/tcg/tricore/asm/test_ftou.S         |  12 ++
 tests/tcg/tricore/asm/test_hptof.S        |  12 ++
 tests/tcg/tricore/asm/test_insert.S       |  14 ++
 17 files changed, 801 insertions(+), 177 deletions(-)
 create mode 100644 tests/tcg/tricore/asm/sas.py
 create mode 100644 tests/tcg/tricore/asm/test_arith.S
 create mode 100644 tests/tcg/tricore/asm/test_crcn.S
 create mode 100644 tests/tcg/tricore/asm/test_ftohp.S
 create mode 100644 tests/tcg/tricore/asm/test_ftou.S
 create mode 100644 tests/tcg/tricore/asm/test_hptof.S

[PULL 01/21] tests/tcg/tricore: Bump cpu to tc37x

[Bastian Koppelmann]

we don't want to exclude ISA v1.6.2 insns from our tests.

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230828112651.522058-2-kbastian@mail.uni-paderborn.de>
---
 tests/tcg/tricore/Makefile.softmmu-target | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index 2ec0bd3622..d556201b07 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -25,7 +25,7 @@ TESTS += test_muls.asm.tst
 TESTS += test_boot_to_main.c.tst
 TESTS += test_context_save_areas.c.tst
 
-QEMU_OPTS += -M tricore_testboard -cpu tc27x -nographic -kernel
+QEMU_OPTS += -M tricore_testboard -cpu tc37x -nographic -kernel
 
 %.pS: $(ASM_TESTS_PATH)/%.S
 	$(CC) -E -o $@ $<
-- 
2.42.0

[PULL 02/21] target/tricore: Implement CRCN insn

[Bastian Koppelmann]

reported in https://gitlab.com/qemu-project/qemu/-/issues/1667

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-3-kbastian@mail.uni-paderborn.de>
---
 target/tricore/helper.h                   |  1 +
 target/tricore/op_helper.c                | 63 +++++++++++++++++++++++
 target/tricore/translate.c                |  8 +++
 target/tricore/tricore-opcodes.h          |  1 +
 tests/tcg/tricore/Makefile.softmmu-target |  1 +
 tests/tcg/tricore/asm/test_crcn.S         |  9 ++++
 6 files changed, 83 insertions(+)
 create mode 100644 tests/tcg/tricore/asm/test_crcn.S

diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 31d71eac7a..190645413a 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -134,6 +134,7 @@ DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32, i32)
 DEF_HELPER_FLAGS_2(crc32b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
 DEF_HELPER_FLAGS_2(crc32_be, TCG_CALL_NO_RWG_SE, i32, i32, i32)
 DEF_HELPER_FLAGS_2(crc32_le, TCG_CALL_NO_RWG_SE, i32, i32, i32)
+DEF_HELPER_FLAGS_3(crcn, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
 DEF_HELPER_FLAGS_2(shuffle, TCG_CALL_NO_RWG_SE, i32, i32, i32)
 /* CSA */
 DEF_HELPER_2(call, void, env, i32)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 89be1ed648..0cf8eb50bd 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2308,6 +2308,69 @@ uint32_t helper_crc32_le(uint32_t arg0, uint32_t arg1)
     return crc32(arg1, buf, 4);
 }
 
+static uint32_t crc_div(uint32_t crc_in, uint32_t data, uint32_t gen,
+                        uint32_t n, uint32_t m)
+{
+    uint32_t i;
+
+    data = data << n;
+    for (i = 0; i < m; i++) {
+        if (crc_in & (1u << (n - 1))) {
+            crc_in <<= 1;
+            if (data & (1u << (m - 1))) {
+                crc_in++;
+            }
+            crc_in ^= gen;
+        } else {
+            crc_in <<= 1;
+            if (data & (1u << (m - 1))) {
+                crc_in++;
+            }
+        }
+        data <<= 1;
+    }
+
+    return crc_in;
+}
+
+uint32_t helper_crcn(uint32_t arg0, uint32_t arg1, uint32_t arg2)
+{
+    uint32_t crc_out, crc_in;
+    uint32_t n = extract32(arg0, 12, 4) + 1;
+    uint32_t gen = extract32(arg0, 16, n);
+    uint32_t inv = extract32(arg0, 9, 1);
+    uint32_t le = extract32(arg0, 8, 1);
+    uint32_t m = extract32(arg0, 0, 3) + 1;
+    uint32_t data = extract32(arg1, 0, m);
+    uint32_t seed = extract32(arg2, 0, n);
+
+    if (le == 1) {
+        if (m == 0) {
+            data = 0;
+        } else {
+            data = revbit32(data) >> (32 - m);
+        }
+    }
+
+    if (inv == 1) {
+        seed = ~seed;
+    }
+
+    if (m > n) {
+        crc_in = (data >> (m - n)) ^ seed;
+    } else {
+        crc_in = (data << (n - m)) ^ seed;
+    }
+
+    crc_out = crc_div(crc_in, data, gen, n, m);
+
+    if (inv) {
+        crc_out = ~crc_out;
+    }
+
+    return extract32(crc_out, 0, n);
+}
+
 uint32_t helper_shuffle(uint32_t arg0, uint32_t arg1)
 {
     uint32_t resb;
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 6ae5ccbf72..4e7e18f985 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6669,6 +6669,14 @@ static void decode_rrr_divide(DisasContext *ctx)
         gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
                         cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
         break;
+    case OPC2_32_RRR_CRCN:
+        if (has_feature(ctx, TRICORE_FEATURE_162)) {
+            gen_helper_crcn(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2],
+                            cpu_gpr_d[r3]);
+        } else {
+            generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+        }
+        break;
     case OPC2_32_RRR_ADD_F:
         gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
         break;
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index bc62b73173..f070571665 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1247,6 +1247,7 @@ enum {
     OPC2_32_RRR_SUB_F                            = 0x03,
     OPC2_32_RRR_MADD_F                           = 0x06,
     OPC2_32_RRR_MSUB_F                           = 0x07,
+    OPC2_32_RRR_CRCN                             = 0x01, /* 1.6.2 up */
 };
 /*
  * RRR1 Format
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index d556201b07..b8d9b33933 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -9,6 +9,7 @@ CFLAGS = -mtc162 -c -I$(TESTS_PATH)
 TESTS += test_abs.asm.tst
 TESTS += test_bmerge.asm.tst
 TESTS += test_clz.asm.tst
+TESTS += test_crcn.asm.tst
 TESTS += test_dextr.asm.tst
 TESTS += test_dvstep.asm.tst
 TESTS += test_fadd.asm.tst
diff --git a/tests/tcg/tricore/asm/test_crcn.S b/tests/tcg/tricore/asm/test_crcn.S
new file mode 100644
index 0000000000..51a22722a3
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_crcn.S
@@ -0,0 +1,9 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+#                insn num    result   rs1    rs2     rs3
+#                 |     |      |      |       |       |
+    TEST_D_DDD(crcn, 1, 0x00002bed, 0x0, 0xa10ddeed, 0x0)
+
+    TEST_PASSFAIL
-- 
2.42.0

[PULL 03/21] target/tricore: Correctly handle FPU RM from PSW

[Bastian Koppelmann]

when we reconstructed PSW using psw_read(), we were trying to clear the
cached USB bits out of env->PSW. The mask was wrong and we would clear
PSW.RM as well.

when we write the PSW using psw_write() we update the rounding modes in
env->fp_status for softfloat. The order of bits used by TriCore is not
the one used by softfloat.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-4-kbastian@mail.uni-paderborn.de>
---
 target/tricore/helper.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 6d076ac36f..e615c3d6d4 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -120,7 +120,21 @@ void tricore_cpu_list(void)
 
 void fpu_set_state(CPUTriCoreState *env)
 {
-    set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status);
+    switch (extract32(env->PSW, 24, 2)) {
+    case 0:
+        set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
+        break;
+    case 1:
+        set_float_rounding_mode(float_round_up, &env->fp_status);
+        break;
+    case 2:
+        set_float_rounding_mode(float_round_down, &env->fp_status);
+        break;
+    case 3:
+        set_float_rounding_mode(float_round_to_zero, &env->fp_status);
+        break;
+    }
+
     set_flush_inputs_to_zero(1, &env->fp_status);
     set_flush_to_zero(1, &env->fp_status);
     set_default_nan_mode(1, &env->fp_status);
@@ -129,7 +143,7 @@ void fpu_set_state(CPUTriCoreState *env)
 uint32_t psw_read(CPUTriCoreState *env)
 {
     /* clear all USB bits */
-    env->PSW &= 0x6ffffff;
+    env->PSW &= 0x7ffffff;
     /* now set them from the cache */
     env->PSW |= ((env->PSW_USB_C != 0) << 31);
     env->PSW |= ((env->PSW_USB_V   & (1 << 31))  >> 1);
-- 
2.42.0

[PULL 04/21] target/tricore: Implement FTOU insn

[Bastian Koppelmann]

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-5-kbastian@mail.uni-paderborn.de>
---
 target/tricore/fpu_helper.c               | 32 +++++++++++++++++++++++
 target/tricore/helper.h                   |  1 +
 target/tricore/translate.c                |  3 +++
 tests/tcg/tricore/Makefile.softmmu-target |  1 +
 tests/tcg/tricore/asm/test_ftou.S         | 12 +++++++++
 5 files changed, 49 insertions(+)
 create mode 100644 tests/tcg/tricore/asm/test_ftou.S

diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index cb7ee7dd35..3aefeb776e 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -429,6 +429,38 @@ uint32_t helper_ftoiz(CPUTriCoreState *env, uint32_t arg)
     return result;
 }
 
+uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg)
+{
+    float32 f_arg = make_float32(arg);
+    uint32_t result;
+    int32_t flags = 0;
+
+    result = float32_to_uint32(f_arg, &env->fp_status);
+
+    flags = f_get_excp_flags(env);
+    if (flags & float_flag_invalid) {
+        flags &= ~float_flag_inexact;
+        if (float32_is_any_nan(f_arg)) {
+            result = 0;
+        }
+    /*
+     * we need to check arg < 0.0 before rounding as TriCore needs to raise
+     * float_flag_invalid as well. For instance, when we have a negative
+     * exponent and sign, softfloat would only raise float_flat_inexact.
+     */
+    } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
+        flags = float_flag_invalid;
+        result = 0;
+    }
+
+    if (flags) {
+        f_update_psw_flags(env, flags);
+    } else {
+        env->FPU_FS = 0;
+    }
+    return result;
+}
+
 uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
 {
     float32 f_arg = make_float32(arg);
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 190645413a..827fbaa692 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -114,6 +114,7 @@ DEF_HELPER_2(ftoi, i32, env, i32)
 DEF_HELPER_2(itof, i32, env, i32)
 DEF_HELPER_2(utof, i32, env, i32)
 DEF_HELPER_2(ftoiz, i32, env, i32)
+DEF_HELPER_2(ftou, i32, env, i32)
 DEF_HELPER_2(ftouz, i32, env, i32)
 DEF_HELPER_2(updfl, void, env, i32)
 /* dvinit */
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 4e7e18f985..382ecf4775 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6269,6 +6269,9 @@ static void decode_rr_divide(DisasContext *ctx)
     case OPC2_32_RR_ITOF:
         gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
         break;
+    case OPC2_32_RR_FTOU:
+        gen_helper_ftou(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+        break;
     case OPC2_32_RR_FTOUZ:
         gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
         break;
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index b8d9b33933..91ae129a83 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -15,6 +15,7 @@ TESTS += test_dvstep.asm.tst
 TESTS += test_fadd.asm.tst
 TESTS += test_fmul.asm.tst
 TESTS += test_ftoi.asm.tst
+TESTS += test_ftou.asm.tst
 TESTS += test_imask.asm.tst
 TESTS += test_insert.asm.tst
 TESTS += test_ld_bu.asm.tst
diff --git a/tests/tcg/tricore/asm/test_ftou.S b/tests/tcg/tricore/asm/test_ftou.S
new file mode 100644
index 0000000000..10f106ad62
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_ftou.S
@@ -0,0 +1,12 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+    TEST_D_D(ftou, 1, 0x00000000, 0x1733f6c2)
+    TEST_D_D(ftou, 2, 0x00000000, 0x2c9d9cdc)
+    TEST_D_D(ftou, 3, 0xffffffff, 0x56eb7395)
+    TEST_D_D(ftou, 4, 0x79900800, 0x4ef32010)
+    TEST_D_D(ftou, 5, 0x0353f510, 0x4c54fd44)
+
+    TEST_PASSFAIL
+
-- 
2.42.0

[PULL 05/21] target/tricore: Clarify special case for FTOUZ insn

[Bastian Koppelmann]

this is not something other ISAs do, so clarify it with a comment.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-6-kbastian@mail.uni-paderborn.de>
---
 target/tricore/fpu_helper.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index 3aefeb776e..d0c474c5f3 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -475,6 +475,11 @@ uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
         if (float32_is_any_nan(f_arg)) {
             result = 0;
         }
+    /*
+     * we need to check arg < 0.0 before rounding as TriCore needs to raise
+     * float_flag_invalid as well. For instance, when we have a negative
+     * exponent and sign, softfloat would only raise float_flat_inexact.
+     */
     } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
         flags = float_flag_invalid;
         result = 0;
-- 
2.42.0

[PULL 06/21] target/tricore: Implement ftohp insn

[Bastian Koppelmann]

reported in https://gitlab.com/qemu-project/qemu/-/issues/1667

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-7-kbastian@mail.uni-paderborn.de>
---
 target/tricore/fpu_helper.c               | 38 +++++++++++++++++++++++
 target/tricore/helper.c                   |  1 +
 target/tricore/helper.h                   |  1 +
 target/tricore/translate.c                |  7 +++++
 target/tricore/tricore-opcodes.h          |  1 +
 tests/tcg/tricore/Makefile.softmmu-target |  1 +
 tests/tcg/tricore/asm/test_ftohp.S        | 14 +++++++++
 7 files changed, 63 insertions(+)
 create mode 100644 tests/tcg/tricore/asm/test_ftohp.S

diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index d0c474c5f3..848c4a40a0 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -373,6 +373,44 @@ uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
     return (uint32_t)result;
 }
 
+uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
+{
+    float32 f_arg = make_float32(arg);
+    uint32_t result = 0;
+    int32_t flags = 0;
+
+    /*
+     * if we have any NAN we need to move the top 2 and lower 8 input mantissa
+     * bits to the top 2 and lower 8 output mantissa bits respectively.
+     * Softfloat on the other hand uses the top 10 mantissa bits.
+     */
+    if (float32_is_any_nan(f_arg)) {
+        if (float32_is_signaling_nan(f_arg, &env->fp_status)) {
+            flags |= float_flag_invalid;
+        }
+        result = float16_set_sign(result, arg >> 31);
+        result = deposit32(result, 10, 5, 0x1f);
+        result = deposit32(result, 8, 2, extract32(arg, 21, 2));
+        result = deposit32(result, 0, 8, extract32(arg, 0, 8));
+        if (extract32(result, 0, 10) == 0) {
+            result |= (1 << 8);
+        }
+    } else {
+        set_flush_to_zero(0, &env->fp_status);
+        result = float32_to_float16(f_arg, true, &env->fp_status);
+        set_flush_to_zero(1, &env->fp_status);
+        flags = f_get_excp_flags(env);
+    }
+
+    if (flags) {
+        f_update_psw_flags(env, flags);
+    } else {
+        env->FPU_FS = 0;
+    }
+
+    return result;
+}
+
 uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
 {
     float32 f_result;
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index e615c3d6d4..7e5da3cb23 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -137,6 +137,7 @@ void fpu_set_state(CPUTriCoreState *env)
 
     set_flush_inputs_to_zero(1, &env->fp_status);
     set_flush_to_zero(1, &env->fp_status);
+    set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
     set_default_nan_mode(1, &env->fp_status);
 }
 
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 827fbaa692..dcc5a492b3 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -111,6 +111,7 @@ DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)
 DEF_HELPER_3(fcmp, i32, env, i32, i32)
 DEF_HELPER_2(qseed, i32, env, i32)
 DEF_HELPER_2(ftoi, i32, env, i32)
+DEF_HELPER_2(ftohp, i32, env, i32)
 DEF_HELPER_2(itof, i32, env, i32)
 DEF_HELPER_2(utof, i32, env, i32)
 DEF_HELPER_2(ftoiz, i32, env, i32)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 382ecf4775..d76b6475f1 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6260,6 +6260,13 @@ static void decode_rr_divide(DisasContext *ctx)
     case OPC2_32_RR_DIV_F:
         gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
         break;
+    case OPC2_32_RR_FTOHP:
+        if (has_feature(ctx, TRICORE_FEATURE_162)) {
+            gen_helper_ftohp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+        } else {
+            generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+        }
+        break;
     case OPC2_32_RR_CMP_F:
         gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
         break;
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index f070571665..29e655a667 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1152,6 +1152,7 @@ enum {
     OPC2_32_RR_ITOF                              = 0x14,
     OPC2_32_RR_CMP_F                             = 0x00,
     OPC2_32_RR_FTOIZ                             = 0x13,
+    OPC2_32_RR_FTOHP                             = 0x25, /* 1.6.2 only */
     OPC2_32_RR_FTOQ31                            = 0x11,
     OPC2_32_RR_FTOQ31Z                           = 0x18,
     OPC2_32_RR_FTOU                              = 0x12,
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index 91ae129a83..fc545d45ae 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -14,6 +14,7 @@ TESTS += test_dextr.asm.tst
 TESTS += test_dvstep.asm.tst
 TESTS += test_fadd.asm.tst
 TESTS += test_fmul.asm.tst
+TESTS += test_ftohp.asm.tst
 TESTS += test_ftoi.asm.tst
 TESTS += test_ftou.asm.tst
 TESTS += test_imask.asm.tst
diff --git a/tests/tcg/tricore/asm/test_ftohp.S b/tests/tcg/tricore/asm/test_ftohp.S
new file mode 100644
index 0000000000..9e23141c1e
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_ftohp.S
@@ -0,0 +1,14 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+    TEST_D_D(ftohp, 1, 0xffff, 0xffffffff)
+    TEST_D_D(ftohp, 2, 0xfc00, 0xff800000)
+    TEST_D_D(ftohp, 3, 0x7c00, 0x7f800000)
+    TEST_D_D(ftohp, 4, 0x0, 0x0)
+    TEST_D_D(ftohp, 5, 0x5, 0x34a43580)
+
+    #TEST_D_D_PSW(ftohp, 6, 0x400, 0x8c000b80, 0x387fee74)
+
+    TEST_PASSFAIL
+
-- 
2.42.0

[PULL 07/21] target/tricore: Implement hptof insn

[Bastian Koppelmann]

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-8-kbastian@mail.uni-paderborn.de>
---
 target/tricore/fpu_helper.c               | 36 +++++++++++++++++++++++
 target/tricore/helper.h                   |  1 +
 target/tricore/translate.c                |  7 +++++
 target/tricore/tricore-opcodes.h          |  1 +
 tests/tcg/tricore/Makefile.softmmu-target |  1 +
 tests/tcg/tricore/asm/test_hptof.S        | 12 ++++++++
 6 files changed, 58 insertions(+)
 create mode 100644 tests/tcg/tricore/asm/test_hptof.S

diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index 848c4a40a0..5d38aea143 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -373,6 +373,42 @@ uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
     return (uint32_t)result;
 }
 
+uint32_t helper_hptof(CPUTriCoreState *env, uint32_t arg)
+{
+    float16 f_arg = make_float16(arg);
+    uint32_t result = 0;
+    int32_t flags = 0;
+
+    /*
+     * if we have any NAN we need to move the top 2 and lower 8 input mantissa
+     * bits to the top 2 and lower 8 output mantissa bits respectively.
+     * Softfloat on the other hand uses the top 10 mantissa bits.
+     */
+    if (float16_is_any_nan(f_arg)) {
+        if (float16_is_signaling_nan(f_arg, &env->fp_status)) {
+            flags |= float_flag_invalid;
+        }
+        result = 0;
+        result = float32_set_sign(result, f_arg >> 15);
+        result = deposit32(result, 23, 8, 0xff);
+        result = deposit32(result, 21, 2, extract32(f_arg, 8, 2));
+        result = deposit32(result, 0, 8, extract32(f_arg, 0, 8));
+    } else {
+        set_flush_inputs_to_zero(0, &env->fp_status);
+        result = float16_to_float32(f_arg, true, &env->fp_status);
+        set_flush_inputs_to_zero(1, &env->fp_status);
+        flags = f_get_excp_flags(env);
+    }
+
+    if (flags) {
+        f_update_psw_flags(env, flags);
+    } else {
+        env->FPU_FS = 0;
+    }
+
+    return result;
+}
+
 uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
 {
     float32 f_arg = make_float32(arg);
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index dcc5a492b3..1d97d078b0 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -112,6 +112,7 @@ DEF_HELPER_3(fcmp, i32, env, i32, i32)
 DEF_HELPER_2(qseed, i32, env, i32)
 DEF_HELPER_2(ftoi, i32, env, i32)
 DEF_HELPER_2(ftohp, i32, env, i32)
+DEF_HELPER_2(hptof, i32, env, i32)
 DEF_HELPER_2(itof, i32, env, i32)
 DEF_HELPER_2(utof, i32, env, i32)
 DEF_HELPER_2(ftoiz, i32, env, i32)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index d76b6475f1..c9823ee32a 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6267,6 +6267,13 @@ static void decode_rr_divide(DisasContext *ctx)
             generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
         }
         break;
+   case OPC2_32_RR_HPTOF:
+        if (has_feature(ctx, TRICORE_FEATURE_162)) {
+            gen_helper_hptof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+        } else {
+            generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+        }
+        break;
     case OPC2_32_RR_CMP_F:
         gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
         break;
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index 29e655a667..60d2402b6e 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1153,6 +1153,7 @@ enum {
     OPC2_32_RR_CMP_F                             = 0x00,
     OPC2_32_RR_FTOIZ                             = 0x13,
     OPC2_32_RR_FTOHP                             = 0x25, /* 1.6.2 only */
+    OPC2_32_RR_HPTOF                             = 0x24, /* 1.6.2 only */
     OPC2_32_RR_FTOQ31                            = 0x11,
     OPC2_32_RR_FTOQ31Z                           = 0x18,
     OPC2_32_RR_FTOU                              = 0x12,
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index fc545d45ae..258aeb40ae 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -17,6 +17,7 @@ TESTS += test_fmul.asm.tst
 TESTS += test_ftohp.asm.tst
 TESTS += test_ftoi.asm.tst
 TESTS += test_ftou.asm.tst
+TESTS += test_hptof.asm.tst
 TESTS += test_imask.asm.tst
 TESTS += test_insert.asm.tst
 TESTS += test_ld_bu.asm.tst
diff --git a/tests/tcg/tricore/asm/test_hptof.S b/tests/tcg/tricore/asm/test_hptof.S
new file mode 100644
index 0000000000..8adc5e5273
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_hptof.S
@@ -0,0 +1,12 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+    TEST_D_D(hptof, 1, 0xba190000, 0xcc0e90c8)
+    TEST_D_D(hptof, 2, 0x3eaea000, 0x8be23575)
+    TEST_D_D(hptof, 3, 0xc33b8000, 0xcc48d9dc)
+    TEST_D_D(hptof, 4, 0x43e2a000, 0xaef95f15)
+    TEST_D_D(hptof, 5, 0x3d55e000, 0x04932aaf)
+
+    TEST_PASSFAIL
+
-- 
2.42.0

[PULL 08/21] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0

[Bastian Koppelmann]

we would crash if width was 0 for these insns, as tcg_gen_deposit() is
undefined for that case. For TriCore, width = 0 is a mov from the src reg
to the dst reg, so we special case this here.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-9-kbastian@mail.uni-paderborn.de>
---
 target/tricore/translate.c          | 10 ++++++++--
 tests/tcg/tricore/asm/macros.h      | 15 +++++++++++++++
 tests/tcg/tricore/asm/test_insert.S |  9 +++++++++
 3 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index c9823ee32a..3f950ae33b 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -5310,8 +5310,11 @@ static void decode_rcpw_insert(DisasContext *ctx)
         }
         break;
     case OPC2_32_RCPW_INSERT:
+        /* tcg_gen_deposit_tl() does not handle the case of width = 0 */
+        if (width == 0) {
+            tcg_gen_mov_tl(cpu_gpr_d[r2], cpu_gpr_d[r1]);
         /* if pos + width > 32 undefined result */
-        if (pos + width <= 32) {
+        } else if (pos + width <= 32) {
             temp = tcg_constant_i32(const4);
             tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
         }
@@ -6571,7 +6574,10 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
 
         break;
     case OPC2_32_RRPW_INSERT:
-        if (pos + width <= 32) {
+        /* tcg_gen_deposit_tl() does not handle the case of width = 0 */
+        if (width == 0) {
+            tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+        } else if (pos + width <= 32) {
             tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
                                pos, width);
         }
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index b5087b5c97..51f6191ef2 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -161,6 +161,21 @@ test_ ## num:                                                    \
     insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2;   \
     )
 
+#define TEST_D_DDII(insn, num, result, rs1, rs2, imm1, imm2) \
+    TEST_CASE(num, DREG_CALC_RESULT, result,                 \
+    LI(DREG_RS1, rs1);                                       \
+    LI(DREG_RS2, rs2);                                       \
+    rstv;                                                    \
+    insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2;   \
+    )
+
+#define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
+    TEST_CASE(num, DREG_CALC_RESULT, result,                 \
+    LI(DREG_RS1, rs1);                                       \
+    rstv;                                                    \
+    insn DREG_CALC_RESULT, DREG_RS1, imm1, imm2, imm3;       \
+    )
+
 #define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
     TEST_CASE_E(num, res_lo, res_hi,                              \
     LI(EREG_RS1_LO, rs1_lo);                                      \
diff --git a/tests/tcg/tricore/asm/test_insert.S b/tests/tcg/tricore/asm/test_insert.S
index d5fd2237e1..3978810121 100644
--- a/tests/tcg/tricore/asm/test_insert.S
+++ b/tests/tcg/tricore/asm/test_insert.S
@@ -6,4 +6,13 @@ _start:
 #                 |     |      |            |       |     |    |
     TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8)
 
+#                insn num    result        rs1    imm1   imm2 imm3
+#                 |     |      |            |       |     |    |
+    TEST_D_DIII(insert, 2, 0xd38fe370, 0xd38fe370, 0x4, 0x4 , 0x0)
+    TEST_D_DIII(insert, 3, 0xd38fe374, 0xd38fe370, 0x4, 0x0 , 0x4)
+
+#                insn  num   result       rs1         rs2      pos  width
+#                 |     |      |           |           |        |    |
+    TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
+
     TEST_PASSFAIL
-- 
2.42.0

[PULL 09/21] target/tricore: Swap src and dst reg for RCRR_INSERT

[Bastian Koppelmann]

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-10-kbastian@mail.uni-paderborn.de>
---
 target/tricore/translate.c          | 8 ++++----
 tests/tcg/tricore/asm/macros.h      | 9 +++++++++
 tests/tcg/tricore/asm/test_insert.S | 5 +++++
 3 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 3f950ae33b..7aba7b067c 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8223,12 +8223,12 @@ static void decode_32Bit_opc(DisasContext *ctx)
         temp2 = tcg_temp_new(); /* width*/
         temp3 = tcg_temp_new(); /* pos */
 
-        CHECK_REG_PAIR(r3);
+        CHECK_REG_PAIR(r2);
 
-        tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
-        tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
+        tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f);
+        tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f);
 
-        gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
+        gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3);
         break;
 /* RCRW Format */
     case OPCM_32_RCRW_MASK_INSERT:
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 51f6191ef2..17e696bef5 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -169,6 +169,15 @@ test_ ## num:                                                    \
     insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2;   \
     )
 
+#define TEST_D_DIE(insn, num, result, rs1, imm1, rs2_lo, rs2_hi)\
+    TEST_CASE(num, DREG_CALC_RESULT, result,                    \
+    LI(DREG_RS1, rs1);                                          \
+    LI(EREG_RS2_LO, rs2_lo);                                    \
+    LI(EREG_RS2_HI, rs2_hi);                                    \
+    rstv;                                                       \
+    insn DREG_CALC_RESULT, DREG_RS1, imm1, EREG_RS2;            \
+    )
+
 #define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
     TEST_CASE(num, DREG_CALC_RESULT, result,                 \
     LI(DREG_RS1, rs1);                                       \
diff --git a/tests/tcg/tricore/asm/test_insert.S b/tests/tcg/tricore/asm/test_insert.S
index 3978810121..223d7ce796 100644
--- a/tests/tcg/tricore/asm/test_insert.S
+++ b/tests/tcg/tricore/asm/test_insert.S
@@ -15,4 +15,9 @@ _start:
 #                 |     |      |           |           |        |    |
     TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
 
+#                insn num   result       rs1     imm1      rs2_h       rs2_l
+#                 |    |      |           |        |         |           |
+    TEST_D_DIE(insert, 5, 0xe30c308d, 0xe30c308d ,0x3 , 0x00000000 ,0x00000000)
+    TEST_D_DIE(insert, 6, 0x669b0120, 0x669b2820 ,0x2 , 0x5530a1c7 ,0x3a2b0f67)
+
     TEST_PASSFAIL
-- 
2.42.0

[PULL 10/21] target/tricore: Replace cpu_*_code with translator_*

[Bastian Koppelmann]

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-11-kbastian@mail.uni-paderborn.de>
---
 target/tricore/translate.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 7aba7b067c..2107d1fdd4 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8398,7 +8398,7 @@ static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx)
      * 4 bytes from the page boundary, so we cross the page if the first
      * 16 bits indicate that this is a 32 bit insn.
      */
-    uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next);
+    uint16_t insn = translator_lduw(env, &ctx->base, ctx->base.pc_next);
 
     return !tricore_insn_is_16bit(insn);
 }
@@ -8411,14 +8411,15 @@ static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     uint16_t insn_lo;
     bool is_16bit;
 
-    insn_lo = cpu_lduw_code(env, ctx->base.pc_next);
+    insn_lo = translator_lduw(env, &ctx->base, ctx->base.pc_next);
     is_16bit = tricore_insn_is_16bit(insn_lo);
     if (is_16bit) {
         ctx->opcode = insn_lo;
         ctx->pc_succ_insn = ctx->base.pc_next + 2;
         decode_16Bit_opc(ctx);
     } else {
-        uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2);
+        uint32_t insn_hi = translator_lduw(env, &ctx->base,
+                                           ctx->base.pc_next + 2);
         ctx->opcode = insn_hi << 16 | insn_lo;
         ctx->pc_succ_insn = ctx->base.pc_next + 4;
         decode_32Bit_opc(ctx);
-- 
2.42.0

[PULL 11/21] target/tricore: Fix FTOUZ being ISA v1.3.1 up

[Bastian Koppelmann]

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-12-kbastian@mail.uni-paderborn.de>
---
 target/tricore/translate.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 2107d1fdd4..7b53307eff 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6290,7 +6290,11 @@ static void decode_rr_divide(DisasContext *ctx)
         gen_helper_ftou(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
         break;
     case OPC2_32_RR_FTOUZ:
-        gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+        if (has_feature(ctx, TRICORE_FEATURE_131)) {
+            gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+        } else {
+            generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+        }
         break;
     case OPC2_32_RR_UPDFL:
         gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
-- 
2.42.0

[PULL 12/21] tests/tcg/tricore: Extended and non-extened regs now match

[Bastian Koppelmann]

RSx for d regs and e regs now use the same numbering. This makes sure
that mixing d and e registers in an insn test will not overwrite data
between registers.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-2-kbastian@mail.uni-paderborn.de>
---
 tests/tcg/tricore/asm/macros.h | 38 +++++++++++++++++-----------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 17e696bef5..0f349dbf1e 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -12,31 +12,31 @@
 #define TESTDEV_ADDR 0xf0000000
 /* Register definitions */
 #define DREG_RS1 %d0
-#define DREG_RS2 %d1
-#define DREG_RS3 %d2
-#define DREG_CALC_RESULT %d3
-#define DREG_CALC_PSW %d4
-#define DREG_CORRECT_PSW %d5
-#define DREG_TEMP_LI %d10
-#define DREG_TEMP %d11
-#define DREG_TEST_NUM %d14
-#define DREG_CORRECT_RESULT %d15
-#define DREG_CORRECT_RESULT_2 %d13
+#define DREG_RS2 %d2
+#define DREG_RS3 %d4
+#define DREG_CALC_RESULT %d5
+#define DREG_CALC_PSW %d6
+#define DREG_CORRECT_PSW %d7
+#define DREG_TEMP_LI %d13
+#define DREG_TEMP %d14
+#define DREG_TEST_NUM %d8
+#define DREG_CORRECT_RESULT %d9
+#define DREG_CORRECT_RESULT_2 %d10
 
 #define AREG_ADDR %a0
 #define AREG_CORRECT_RESULT %a3
 
 #define DREG_DEV_ADDR %a15
 
-#define EREG_RS1 %e6
-#define EREG_RS1_LO %d6
-#define EREG_RS1_HI %d7
-#define EREG_RS2 %e8
-#define EREG_RS2_LO %d8
-#define EREG_RS2_HI %d9
-#define EREG_CALC_RESULT %e8
-#define EREG_CALC_RESULT_HI %d9
-#define EREG_CALC_RESULT_LO %d8
+#define EREG_RS1 %e0
+#define EREG_RS1_LO %d0
+#define EREG_RS1_HI %d1
+#define EREG_RS2 %e2
+#define EREG_RS2_LO %d2
+#define EREG_RS2_HI %d3
+#define EREG_CALC_RESULT %e6
+#define EREG_CALC_RESULT_LO %d6
+#define EREG_CALC_RESULT_HI %d7
 #define EREG_CORRECT_RESULT_LO %d0
 #define EREG_CORRECT_RESULT_HI %d1
 
-- 
2.42.0

[PULL 13/21] hw/tricore: Log failing test in testdevice

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-3-kbastian@mail.uni-paderborn.de>
---
 hw/tricore/tricore_testdevice.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/tricore/tricore_testdevice.c b/hw/tricore/tricore_testdevice.c
index a1563aa568..d0f8db9089 100644
--- a/hw/tricore/tricore_testdevice.c
+++ b/hw/tricore/tricore_testdevice.c
@@ -16,6 +16,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/log.h"
 #include "hw/sysbus.h"
 #include "hw/qdev-properties.h"
 #include "hw/tricore/tricore_testdevice.h"
@@ -23,6 +24,9 @@
 static void tricore_testdevice_write(void *opaque, hwaddr offset,
                                       uint64_t value, unsigned size)
 {
+    if (value != 0) {
+        qemu_log_mask(LOG_GUEST_ERROR, "Test %ld failed!\n", value);
+    }
     exit(value);
 }
 
-- 
2.42.0

[PULL 14/21] tests/tcg: Reset result register after each test

[Bastian Koppelmann]

some insns use the result register implicitly as an input. Thus, we
could end up with data from the previous insn spilling over.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-4-kbastian@mail.uni-paderborn.de>
---
 tests/tcg/tricore/asm/macros.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 0f349dbf1e..e831f73721 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -46,7 +46,8 @@ test_ ## num:                                     \
     code;                                         \
     LI(DREG_CORRECT_RESULT, correct)              \
     mov DREG_TEST_NUM, num;                       \
-    jne testreg, DREG_CORRECT_RESULT, fail        \
+    jne testreg, DREG_CORRECT_RESULT, fail;       \
+    mov testreg, 0
 
 #define TEST_CASE_E(num, correct_lo, correct_hi, code...)  \
 test_ ## num:                                              \
-- 
2.42.0

[PULL 15/21] tests/tcg/tricore: Add test for all arith insns up to addx

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-5-kbastian@mail.uni-paderborn.de>
---
 tests/tcg/tricore/Makefile.softmmu-target |  3 +-
 tests/tcg/tricore/asm/macros.h            | 50 +++++++++++++++++++++++
 tests/tcg/tricore/asm/sas.py              | 21 ++++++++++
 tests/tcg/tricore/asm/test_arith.S        | 41 +++++++++++++++++++
 4 files changed, 114 insertions(+), 1 deletion(-)
 create mode 100644 tests/tcg/tricore/asm/sas.py
 create mode 100644 tests/tcg/tricore/asm/test_arith.S

diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index 258aeb40ae..82ed9fa7e2 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -6,6 +6,7 @@ LDFLAGS = -T$(TESTS_PATH)/link.ld --mcpu=tc162
 ASFLAGS = -mtc162
 CFLAGS = -mtc162 -c -I$(TESTS_PATH)
 
+TESTS += test_arith.asm.tst
 TESTS += test_abs.asm.tst
 TESTS += test_bmerge.asm.tst
 TESTS += test_clz.asm.tst
@@ -29,7 +30,7 @@ TESTS += test_muls.asm.tst
 TESTS += test_boot_to_main.c.tst
 TESTS += test_context_save_areas.c.tst
 
-QEMU_OPTS += -M tricore_testboard -cpu tc37x -nographic -kernel
+QEMU_OPTS += -M tricore_testboard -cpu tc37x -nographic -d guest_errors -kernel
 
 %.pS: $(ASM_TESTS_PATH)/%.S
 	$(CC) -E -o $@ $<
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index e831f73721..8ed2249b0d 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -112,6 +112,11 @@ test_ ## num:                                                    \
     insn DREG_CORRECT_RESULT, DREG_RS1;               \
     )
 
+#define TEST_D_I(insn, num, result, imm)      \
+    TEST_CASE(num, DREG_CALC_RESULT, result,  \
+    insn DREG_CALC_RESULT, imm;               \
+    )
+
 #define TEST_D_DDD(insn, num, result, rs1, rs2, rs3)        \
     TEST_CASE(num, DREG_CALC_RESULT, result,                \
     LI(DREG_RS1, rs1);                                      \
@@ -129,6 +134,51 @@ test_ ## num:                                                    \
     insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2;          \
     )
 
+#define TEST_D_DI(insn, num, result, rs1, imm1) \
+    TEST_CASE(num, DREG_CALC_RESULT, result,     \
+    LI(DREG_RS1, rs1);                          \
+    rstv;                                       \
+    insn DREG_CALC_RESULT, DREG_RS1, imm1;      \
+    )
+
+#define TEST_D_D15I(insn, num, result, rs1, imm1) \
+    TEST_CASE(num, DREG_CALC_RESULT, result,       \
+    LI(%d15, rs1);                                \
+    rstv;                                         \
+    insn DREG_CALC_RESULT, %d15, imm1;            \
+    )
+
+#define TEST_D15_DD(insn, num, result, rs1, rs2) \
+    TEST_CASE(num, %d15, result,                 \
+    LI(DREG_RS1, rs1);                           \
+    LI(DREG_RS2, rs2);                           \
+    rstv;                                        \
+    insn %d15, DREG_RS1, DREG_RS2;               \
+    )
+
+#define TEST_D15_DI(insn, num, result, rs1, imm) \
+    TEST_CASE(num, %d15, result,                 \
+    LI(DREG_RS1, rs1);                           \
+    rstv;                                        \
+    insn %d15, DREG_RS1, imm;                    \
+    )
+
+#define TEST_D_DD(insn, num, result, rs1, rs2) \
+    TEST_CASE(num, DREG_CALC_RESULT, result,   \
+    LI(DREG_RS1, rs1);                         \
+    LI(DREG_RS2, rs2);                         \
+    rstv;                                      \
+    insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2; \
+    )
+
+#define TEST_D_D15D(insn, num, result, rs1, rs2) \
+    TEST_CASE(num, DREG_CALC_RESULT, result,   \
+    LI(%d15, rs1);                             \
+    LI(DREG_RS2, rs2);                         \
+    rstv;                                      \
+    insn DREG_CALC_RESULT, %d15, DREG_RS2;     \
+    )
+
 #define TEST_D_DDD_PSW(insn, num, result, psw, rs1, rs2, rs3) \
     TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw,         \
     LI(DREG_RS1, rs1);                                        \
diff --git a/tests/tcg/tricore/asm/sas.py b/tests/tcg/tricore/asm/sas.py
new file mode 100644
index 0000000000..ed6b8f3871
--- /dev/null
+++ b/tests/tcg/tricore/asm/sas.py
@@ -0,0 +1,21 @@
+
+with open('test_arith.S', 'r') as f:
+    out = ""
+    lines = f.readlines()
+    num = 1
+    start = False
+    for line in lines:
+        if start:
+            toks = line.split(",")
+            if len(toks) == 1:
+                out += line
+                continue
+            out += toks[0] + ", " + str(num) + "," + ",".join(toks[2:])
+            num += 1
+        else:
+            out += line
+
+        if line.startswith("_start:"):
+            start = True
+
+    print(out)
diff --git a/tests/tcg/tricore/asm/test_arith.S b/tests/tcg/tricore/asm/test_arith.S
new file mode 100644
index 0000000000..07c4b876e9
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_arith.S
@@ -0,0 +1,41 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+    TEST_D_D(abs, 1, 0x778636a7, 0x778636a7 )
+    TEST_D_D(abs.b, 2, 0x497a4902, 0xb786b702 )
+    TEST_D_D(abs.h, 3, 0x48331698, 0xb7cde968 )
+    TEST_D_DI(absdif, 4, 0x22a52402, 0xdd5adc1a ,0x1c )
+    TEST_D_DD(absdif, 5, 0x1e106273, 0x56f0cea3 ,0x75013116 )
+    TEST_D_DD(absdif.b, 6, 0xa650a3b, 0xa7ee8b2a ,0x9d899565 )
+    TEST_D_DD(absdif.h, 7, 0x7dd06888, 0x88292922 ,0x5f9c09a )
+    TEST_D_DI(absdifs, 8, 0x79adddf7, 0x865222d1 ,0xc8 )
+    TEST_D_DD(absdifs, 9, 0x7fffffff, 0x2ac1008b ,0x80032055 )
+    TEST_D_DD(absdifs.h, 10, 0x65ae7fff, 0xf70a7a05 ,0x915cc1b3 )
+    TEST_D_D(abss, 11, 0x2a671868, 0xd598e798 )
+    TEST_D_D(abss.h, 12, 0x60fc7ce5, 0x9f04831b )
+    TEST_D_DI(add, 13, 0x951ce738, 0x951ce6b4 ,0x84 )
+    TEST_D_DD(add, 14, 0x53975df5, 0xc003e25a ,0x93937b9b )
+    TEST_D_I(add, 15, 0x5, 0x5 )
+    TEST_D_D15I(add, 16, 0x3c330214, 0x3c33020f ,0x5 )
+    TEST_D15_DI(add, 17, 0x55eb1b8, 0x55eb1b8 ,0x0 )
+    TEST_D_D(add, 18, 0xe66ead54, 0xe66ead54 )
+    TEST_D_D15D(add, 19, 0xe450f787, 0xc7100fee ,0x1d40e799 )
+    TEST_D15_DD(add, 20, 0x73f6d886, 0x27ca8a80 ,0x4c2c4e06 )
+    TEST_D_DD(add.b, 21, 0x631bd462, 0xf9702965 ,0x6aababfd )
+    TEST_D_DD(add.h, 22, 0x76ce127a, 0xf5402796 ,0x818eeae4 )
+    TEST_D_DI(addc, 23, 0xcf8399c3, 0xcf839920 ,0xa3 )
+    TEST_D_DD(addc, 24, 0xa455054c, 0x85d0b9ed ,0x1e844b5f )
+    TEST_D_DI(addi, 25, 0xbf202fe6, 0xbf1fd903 ,0x56e3 )
+    TEST_D_DI(addih, 26, 0xf28a99cc, 0xc10499cc ,12678 )
+    TEST_D_DI(adds, 27, 0x233892ad, 0x233892ad ,0x0 )
+    TEST_D_DD(adds, 28, 0xc1b1184d, 0x100a2339 ,0xb1a6f514 )
+    TEST_D_D(adds, 29, 0x19143e9a, 0x19143e9a )
+    TEST_D_DD(adds.h, 30, 0x7fff9de3, 0x668ebcc8 ,0x7462e11b )
+    TEST_D_DD(adds.hu, 31, 0xffffffff, 0xbe0776eb ,0x5d69b388 )
+    TEST_D_DI(adds.u, 32, 0x84c176ba, 0x84c176a9 ,0x11 )
+    TEST_D_DD(adds.u, 33, 0xffffffff, 0xd4a91e39 ,0x55b1baed )
+    TEST_D_DI(addx, 34, 0x38f63b5, 0x38f632b ,0x8a )
+    TEST_D_DD(addx, 35, 0x8b9da5a4, 0x16e32e7 ,0x8a2f72bd )
+
+    TEST_PASSFAIL
-- 
2.42.0

[PULL 16/21] tests/tcg/tricore: Add test from 'and' to 'csub'

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-6-kbastian@mail.uni-paderborn.de>
---
 tests/tcg/tricore/asm/macros.h     | 11 +++++++
 tests/tcg/tricore/asm/test_arith.S | 47 ++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 8ed2249b0d..3000e15590 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -117,6 +117,11 @@ test_ ## num:                                                    \
     insn DREG_CALC_RESULT, imm;               \
     )
 
+#define TEST_D15_I(insn, num, result, imm)      \
+    TEST_CASE(num, %d15, result,  \
+    insn %d15, imm;               \
+    )
+
 #define TEST_D_DDD(insn, num, result, rs1, rs2, rs3)        \
     TEST_CASE(num, DREG_CALC_RESULT, result,                \
     LI(DREG_RS1, rs1);                                      \
@@ -236,6 +241,12 @@ test_ ## num:                                                    \
     insn DREG_CALC_RESULT, DREG_RS1, imm1, imm2, imm3;       \
     )
 
+#define TEST_E_D(insn, num, res_lo, res_hi, rs1) \
+    TEST_CASE_E(num, res_lo, res_hi,             \
+    LI(DREG_RS1, rs1);                           \
+    insn EREG_CALC_RESULT, DREG_RS1;             \
+    )
+
 #define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
     TEST_CASE_E(num, res_lo, res_hi,                              \
     LI(EREG_RS1_LO, rs1_lo);                                      \
diff --git a/tests/tcg/tricore/asm/test_arith.S b/tests/tcg/tricore/asm/test_arith.S
index 07c4b876e9..ec87413777 100644
--- a/tests/tcg/tricore/asm/test_arith.S
+++ b/tests/tcg/tricore/asm/test_arith.S
@@ -37,5 +37,52 @@ _start:
     TEST_D_DD(adds.u, 33, 0xffffffff, 0xd4a91e39 ,0x55b1baed )
     TEST_D_DI(addx, 34, 0x38f63b5, 0x38f632b ,0x8a )
     TEST_D_DD(addx, 35, 0x8b9da5a4, 0x16e32e7 ,0x8a2f72bd )
+    TEST_D_DI(and, 36, 0x1, 0xf9683907 ,0x69 )
+    TEST_D_DD(and, 37, 0x40102090, 0x48d86c91 ,0x511123d0 )
+    TEST_D15_I(and, 38, 0x0, 0x1a )
+    TEST_D_D(and, 39, 0x0, 0x551343d6 )
+    TEST_D_DIDI(and.and.t, 40, 0x0, 0x60343d14 ,0x4 ,0x922020d8 ,0x3 )
+    TEST_D_DIDI(and.andn.t, 41, 0x0, 0xd4f95dad ,0x5 ,0xb9fff576 ,0x3 )
+    TEST_D_DI(and.eq, 42, 0x0, 0x9945aaf ,0xf )
+    TEST_D_DD(and.eq, 43, 0x0, 0x32a94b38 ,0xf53b9463 )
+    TEST_D_DI(and.ge, 44, 0x0, 0xe66d0f6e ,0x55 )
+    TEST_D_DD(and.ge, 45, 0x0, 0x43ea87d0 ,0x5adacf4d )
+    TEST_D_DI(and.ge.u, 46, 0x0, 0x4bef5bd1 ,0xb3 )
+    TEST_D_DD(and.ge.u, 47, 0x0, 0x9b5504c2 ,0x3787f19 )
+    TEST_D_DI(and.lt, 48, 0x0, 0x36daf216 ,0xc8 )
+    TEST_D_DD(and.lt, 49, 0x0, 0x6bf175f7 ,0x769bc7db )
+    TEST_D_DI(and.lt.u, 50, 0x0, 0xbef4b04a ,0x1d )
+    TEST_D_DD(and.lt.u, 51, 0x0, 0xa89ea455 ,0x84dc9898 )
+    TEST_D_DI(and.ne, 52, 0x0, 0xf3bb3559 ,0x5e )
+    TEST_D_DD(and.ne, 53, 0x0, 0xa05258eb ,0x50c5b0e4 )
+    TEST_D_DIDI(and.nor.t, 54, 0x0, 0xd7534767 ,0x1 ,0x5fac529f ,0x6 )
+    TEST_D_DIDI(and.or.t, 55, 0x0, 0xa3dd1690 ,0x7 ,0xe25f7361 ,0x4 )
+    TEST_D_DIDI(and.t, 56, 0x0, 0x9f6f71d5 ,0x1 ,0xe9dfe144 ,0x2 )
+    TEST_D_DI(andn, 57, 0xb2ed0c01, 0xb2ed0cf1 ,0xfc )
+    TEST_D_DD(andn, 58, 0x102d884, 0x494ad98c ,0xf87d077a )
+    TEST_D_DIDI(andn.t, 59, 0x0, 0x24ef957a ,0x5 ,0xaf95e01e ,0x4 )
+    TEST_D_DD(bmerge, 60, 0xbfe56f84, 0x2a0fc78 ,0xf7127bb2 )
+    TEST_E_D(bsplit, 61, 0x1ae2, 0xef60, 0xa9ee7c04 )
+    TEST_D_DDI(cadd, 62, 0x3ac01dec, 0x7770d9a ,0x3ac01d3d ,0xaf )
+    TEST_D_DDD(cadd, 63, 0x48a771b4, 0xdf020dda ,0xb81cdead ,0x908a9307 )
+    TEST_D_D15I(cadd, 64, 0x4, 0x6a766c11 ,0x4 )
+    TEST_D_DDI(caddn, 65, 0xdc0cd85d, 0xfe1fbf45 ,0xdc0cd85d ,0x1c )
+    TEST_D_DDD(caddn, 66, 0xd7bd5cb5, 0x70a930bd ,0xd7bd5cb5 ,0xb5dce80d )
+    TEST_D_D15I(caddn, 67, 0x0, 0xb6051252 ,0x4 )
+    TEST_D_D(clo, 68, 0x1, 0xa15f7ebc )
+    TEST_D_D(clo.h, 69, 0x0, 0x2bf418ef )
+    TEST_D_D(cls, 70, 0x1, 0xcbda5b50 )
+    TEST_D_D(cls.h, 71, 0x10001, 0xd15ac540 )
+    TEST_D_D(clz, 72, 0x1, 0x62ddf743 )
+    TEST_D_D(clz.h, 73, 0x0, 0xa859df54 )
+    TEST_D_D15I(cmov, 74, 0x5, 0x7d06b438 ,0x5 )
+    TEST_D_D15D(cmov, 75, 0x4d24e162, 0xd07651a5 ,0x4d24e162 )
+    TEST_D_D15I(cmovn, 76, 0x0, 0xea576d5 ,0x6 )
+    TEST_D_D15D(cmovn, 77, 0x0, 0x6a1d2b48 ,0xb28bc831 )
+    TEST_D_DD(crc32.b, 78, 0x3baca290, 0xcde828a2 ,0x869b2ea4 )
+    TEST_D_DD(crc32b.w, 79, 0x7f9d8908, 0xdaf396a5 ,0xa9011cf2 )
+    TEST_D_DD(crc32l.w, 80, 0x1707579b, 0x87572060 ,0x8cdfa395 )
+    TEST_D_DDD(csub, 81, 0xf389f12f, 0xae9c7e04 ,0x63247211 ,0x6f9a80e2 )
+    TEST_D_DDD(csubn, 82, 0x2a7dd20d, 0xc39caf46 ,0x2a7dd20d ,0xa8ab6269 )
 
     TEST_PASSFAIL
-- 
2.42.0

[PULL 17/21] tests/tcg/tricore: Add test from 'dextr' to 'lt'

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-7-kbastian@mail.uni-paderborn.de>
---
 tests/tcg/tricore/asm/macros.h     | 51 ++++++++++++++++++++++++++--
 tests/tcg/tricore/asm/test_arith.S | 53 ++++++++++++++++++++++++++++++
 2 files changed, 102 insertions(+), 2 deletions(-)

diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 3000e15590..92f0f7b22b 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -34,6 +34,9 @@
 #define EREG_RS2 %e2
 #define EREG_RS2_LO %d2
 #define EREG_RS2_HI %d3
+#define EREG_RS3 %e4
+#define EREG_RS3_LO %d4
+#define EREG_RS3_HI %d5
 #define EREG_CALC_RESULT %e6
 #define EREG_CALC_RESULT_LO %d6
 #define EREG_CALC_RESULT_HI %d7
@@ -131,6 +134,26 @@ test_ ## num:                                                    \
     insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3; \
     )
 
+#define TEST_D_DDDI(insn, num, result, rs1, rs2, rs3, imm)    \
+    TEST_CASE(num, DREG_CALC_RESULT, result,                  \
+    LI(DREG_RS1, rs1);                                        \
+    LI(DREG_RS2, rs2);                                        \
+    LI(DREG_RS3, rs3);                                        \
+    rstv;                                                     \
+    insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3, imm; \
+    )
+
+
+#define TEST_D_DDE(insn, num, result, rs1, rs2, rs3_lo, rs3_hi) \
+    TEST_CASE(num, DREG_CALC_RESULT, result,                    \
+    LI(DREG_RS1, rs1);                                          \
+    LI(DREG_RS2, rs2);                                          \
+    LI(EREG_RS3_LO, rs3_lo);                                    \
+    LI(EREG_RS3_HI, rs3_hi);                                    \
+    rstv;                                                       \
+    insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, EREG_RS3;        \
+    )
+
 #define TEST_D_DD_PSW(insn, num, result, psw, rs1, rs2) \
     TEST_CASE_PSW(num, DREG_CALC_RESULT, result, psw,   \
     LI(DREG_RS1, rs1);                                  \
@@ -209,6 +232,12 @@ test_ ## num:                                                    \
     insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm;           \
     )
 
+#define TEST_E_DII(insn, num, res_lo, res_hi, rs1, imm1, imm2) \
+    TEST_CASE_E(num, res_lo, res_hi,                           \
+    LI(DREG_RS1, rs1);                                         \
+    insn EREG_CALC_RESULT, DREG_RS1, imm1, imm2;               \
+    )
+
 #define TEST_D_DIDI(insn, num, result, rs1, imm1, rs2, imm2) \
     TEST_CASE(num, DREG_CALC_RESULT, result,                 \
     LI(DREG_RS1, rs1);                                       \
@@ -247,7 +276,7 @@ test_ ## num:                                                    \
     insn EREG_CALC_RESULT, DREG_RS1;             \
     )
 
-#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
+#define TEST_E_ED(insn, num, res_lo, res_hi, rs1_lo, rs1_hi, rs2) \
     TEST_CASE_E(num, res_lo, res_hi,                              \
     LI(EREG_RS1_LO, rs1_lo);                                      \
     LI(EREG_RS1_HI, rs1_hi);                                      \
@@ -255,14 +284,32 @@ test_ ## num:                                                    \
     insn EREG_CALC_RESULT, EREG_RS1, DREG_RS2;                    \
     )
 
-#define TEST_E_IDI(insn, num, res_hi, res_lo, imm1, rs1, imm2) \
+#define TEST_E_IDI(insn, num, res_lo, res_hi, imm1, rs1, imm2) \
     TEST_CASE_E(num, res_lo, res_hi,                           \
     LI(DREG_RS1, rs1);                                         \
     rstv;                                                      \
     insn EREG_CALC_RESULT, imm1, DREG_RS1, imm2;               \
     )
 
+#define TEST_E_DD(insn, num, res_lo, res_hi, rs1, rs2) \
+    TEST_CASE_E(num, res_lo, res_hi,                   \
+    LI(DREG_RS1, rs1);                                 \
+    LI(DREG_RS2, rs2);                                 \
+    insn EREG_CALC_RESULT, DREG_RS1, DREG_RS2;         \
+    )
 
+#define TEST_E_DDI(insn, num, res_lo, res_hi, rs1, rs2, imm) \
+    TEST_CASE_E(num, res_lo, res_hi,                         \
+    LI(DREG_RS1, rs1);                                       \
+    LI(DREG_RS2, rs2);                                       \
+    insn EREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm;          \
+    )
+
+#define TEST_E_III(insn, num, res_lo, res_hi, imm1, imm2, imm3) \
+    TEST_CASE_E(num, res_lo, res_hi,                            \
+    rstv;                                                       \
+    insn EREG_CALC_RESULT, imm1, imm2, imm3;                    \
+    )
 
 /* Pass/Fail handling part */
 #define TEST_PASSFAIL                       \
diff --git a/tests/tcg/tricore/asm/test_arith.S b/tests/tcg/tricore/asm/test_arith.S
index ec87413777..68b6715cb9 100644
--- a/tests/tcg/tricore/asm/test_arith.S
+++ b/tests/tcg/tricore/asm/test_arith.S
@@ -84,5 +84,58 @@ _start:
     TEST_D_DD(crc32l.w, 80, 0x1707579b, 0x87572060 ,0x8cdfa395 )
     TEST_D_DDD(csub, 81, 0xf389f12f, 0xae9c7e04 ,0x63247211 ,0x6f9a80e2 )
     TEST_D_DDD(csubn, 82, 0x2a7dd20d, 0xc39caf46 ,0x2a7dd20d ,0xa8ab6269 )
+    TEST_D_DDI(dextr, 83, 0x6b245592, 0x90d648ab ,0x2436a08d ,0x7 )
+    TEST_D_DDD(dextr, 84, 0x4e9d8172, 0x6b8c6274 ,0xec0b9772 ,0x7ab0d8f5 )
+    TEST_E_ED(dvadj, 85, 0xfb793929 ,0xf15f4ecc, 0xfb793928 ,0xf15f4ecc ,0x5de9a7b4 )
+    TEST_E_DD(dvinit, 86, 0xbbd99367 ,0xffffffff, 0xbbd99367 ,0xa248dff9 )
+    TEST_E_DD(dvinit.b, 87, 0x58ffffff ,0x1f3f20, 0x1f3f2058 ,0xfed6c3ec )
+    TEST_E_DD(dvinit.bu, 88, 0xa000000 ,0x8bbf54, 0x8bbf540a ,0xa0bcfdde )
+    TEST_E_DD(dvinit.h, 89, 0xfe59ffff ,0x6d07, 0x6d07fe59 ,0xe4a6e12c )
+    TEST_E_DD(dvinit.hu, 90, 0x8e5d0000 ,0x37bd, 0x37bd8e5d ,0x38c0be4c )
+    TEST_E_DD(dvinit.u, 91, 0x613ca148 ,0x0, 0x613ca148 ,0x79e89e70 )
+    TEST_E_ED(dvstep.u, 92, 0x90388180 ,0x356c3f47, 0x47903881 ,0xd5b131ef ,0xa8f78b60 )
+    TEST_D_DI(eq, 93, 0x0, 0x22cf24bc ,0x3c )
+    TEST_D_DD(eq, 94, 0x0, 0x1b220983 ,0x60d6182 )
+    TEST_D15_DI(eq, 95, 0x0, 0x66b1313e ,0x1 )
+    TEST_D15_DD(eq, 96, 0x0, 0x3a6b6484 ,0xe1bdc794 )
+    TEST_D_DD(eq.b, 97, 0x0, 0x1413e6a2 ,0x8237ab11 )
+    TEST_D_DD(eq.h, 98, 0x0, 0xc2d2cdd3 ,0xfd8576be )
+    TEST_D_DD(eq.w, 99, 0x0, 0x1b6f66d7 ,0x738035d1 )
+    TEST_D_DI(eqany.b, 100, 0x0, 0xfb630c56 ,0x9f )
+    TEST_D_DD(eqany.b, 101, 0x0, 0x5cdbbb44 ,0xf7911917 )
+    TEST_D_DI(eqany.h, 102, 0x0, 0xd31af4d0 ,0xc )
+    TEST_D_DD(eqany.h, 103, 0x0, 0x6bd800e2 ,0x8bea6be7 )
+    TEST_D_DI(ge, 104, 0x1, 0x3d3d0f67 ,0x6d )
+    TEST_D_DD(ge, 105, 0x1, 0x7238ba92 ,0x3d6d3327 )
+    TEST_D_DI(ge.u, 106, 0x1, 0xc34402cb ,0xf2 )
+    TEST_D_DD(ge.u, 107, 0x1, 0xf44ec751 ,0x42f3f12d )
+    TEST_E_III(imask, 108, 0x1c0 ,0x1c0, 0x7 ,0x6 ,0x3 )
+    TEST_E_IDI(imask, 109, 0x1 ,0x7f, 0x1 ,0xa7390380 ,0x7 )
+    TEST_E_DII(imask, 110, 0x3fdaaa80 ,0x1fc0, 0x14ff6aaa ,0x6 ,0x7 )
+    TEST_E_DDI(imask, 111, 0xfc8a94c0 ,0x1f0, 0xafc8a94c ,0x37ceafe4 ,0x5 )
+    TEST_D_DIDI(ins.t, 112, 0x3991c755, 0x3991c755 ,0x2 ,0xa9b171ef ,0x4 )
+    TEST_D_DIII(insert, 113, 0x9997e4d7, 0x9997e497 ,0x6 ,0x5 ,0x2 )
+    TEST_D_DIE(insert, 114, 0x71169ed, 0xaf1169ed ,0x1 ,0xf5abe69a ,0xaef09348 )
+    TEST_D_DIDI(insert, 115, 0x8a228466, 0x8a2284e6 ,0x5 ,0x2c808a7f ,0x2 )
+    TEST_D_DDII(insert, 116, 0xeffef7ec, 0xeffef7e8 ,0xaa92b4ce ,0x1 ,0x3 )
+    TEST_D_DDE(insert, 117, 0x7948cba3, 0x818b7ba3 ,0x70bca465 ,0x47ede909 ,0xbf4f8afe )
+    TEST_D_DDDI(insert, 118, 0x5e974875, 0x5b774875 ,0x27f33374 ,0x4b417135 ,0x7 )
+    TEST_D_DIDI(insn.t, 119, 0xcbbe860a, 0xcbbe860a ,0x4 ,0xd2f483d9 ,0x3 )
+    TEST_E_ED(ixmax, 120, 0x48ef48f1 ,0x6e7e, 0x687e48ef ,0x9afdc6c8 ,0xbd066e7e )
+    TEST_E_ED(ixmax.u, 121, 0xac97ac98 ,0xd968, 0x67b7ac96 ,0x55371874 ,0xd968399e )
+    TEST_E_ED(ixmin, 122, 0x957f9580 ,0xa9de, 0x8ed957e ,0x9519d426 ,0xa9de69e1 )
+    TEST_E_ED(ixmin.u, 123, 0xde48de4a ,0x3660, 0x3dc4de48 ,0x1e5a559d ,0xdbc53660 )
+    TEST_D_DI(lt, 124, 0x1, 0xf156e5c0 ,0x40 )
+    TEST_D_DD(lt, 125, 0x0, 0x51c83765 ,0x1aa7292 )
+    TEST_D15_DI(lt, 126, 0x0, 0x31163fc9 ,0x5 )
+    TEST_D15_DD(lt, 127, 0x1, 0xf9e43e50 ,0x22a3f8d5 )
+    TEST_D_DD(lt.b, 128, 0xff0000, 0x4a374b04 ,0x4869ba92 )
+    TEST_D_DD(lt.bu, 129, 0xff00, 0x4c5bb0c7 ,0x4c3bd2a3 )
+    TEST_D_DD(lt.h, 130, 0xffff0000, 0x326e5bdc ,0x33e03761 )
+    TEST_D_DD(lt.hu, 131, 0x0, 0xf53b8e9b ,0x53cc7810 )
+    TEST_D_DI(lt.u, 132, 0x0, 0xf1f78a54 ,0x4d )
+    TEST_D_DD(lt.u, 133, 0x1, 0x10fedada ,0x265af026 )
+    TEST_D_DD(lt.w, 134, 0xffffffff, 0xbc8a0b22 ,0x3dd6d1a2 )
+    TEST_D_DD(lt.wu, 135, 0x0, 0xcc92a312 ,0x133c8a9d )
 
     TEST_PASSFAIL
-- 
2.42.0

[PULL 18/21] tests/tcg/tricore: Add test from 'max' to 'shas'

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-8-kbastian@mail.uni-paderborn.de>
---
 tests/tcg/tricore/asm/macros.h     |  13 ++++
 tests/tcg/tricore/asm/test_arith.S | 105 +++++++++++++++++++++++++++++
 2 files changed, 118 insertions(+)

diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 92f0f7b22b..5bba9dbbf6 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -143,6 +143,14 @@ test_ ## num:                                                    \
     insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, DREG_RS3, imm; \
     )
 
+#define TEST_D_ED(insn, num, result, rs1_lo, rs1_hi, rs2) \
+    TEST_CASE(num, DREG_CALC_RESULT, result,              \
+    LI(EREG_RS1_LO, rs1_lo);                              \
+    LI(EREG_RS1_HI, rs1_hi);                              \
+    LI(DREG_RS2, rs2);                                    \
+    rstv;                                                 \
+    insn DREG_CALC_RESULT, EREG_RS1, DREG_RS2;            \
+    )
 
 #define TEST_D_DDE(insn, num, result, rs1, rs2, rs3_lo, rs3_hi) \
     TEST_CASE(num, DREG_CALC_RESULT, result,                    \
@@ -284,6 +292,11 @@ test_ ## num:                                                    \
     insn EREG_CALC_RESULT, EREG_RS1, DREG_RS2;                    \
     )
 
+#define TEST_E_I(insn, num, res_lo, res_hi, imm) \
+    TEST_CASE_E(num, res_lo, res_hi,             \
+    insn EREG_CALC_RESULT, imm;                  \
+    )
+
 #define TEST_E_IDI(insn, num, res_lo, res_hi, imm1, rs1, imm2) \
     TEST_CASE_E(num, res_lo, res_hi,                           \
     LI(DREG_RS1, rs1);                                         \
diff --git a/tests/tcg/tricore/asm/test_arith.S b/tests/tcg/tricore/asm/test_arith.S
index 68b6715cb9..728509cfa9 100644
--- a/tests/tcg/tricore/asm/test_arith.S
+++ b/tests/tcg/tricore/asm/test_arith.S
@@ -137,5 +137,110 @@ _start:
     TEST_D_DD(lt.u, 133, 0x1, 0x10fedada ,0x265af026 )
     TEST_D_DD(lt.w, 134, 0xffffffff, 0xbc8a0b22 ,0x3dd6d1a2 )
     TEST_D_DD(lt.wu, 135, 0x0, 0xcc92a312 ,0x133c8a9d )
+    TEST_D_DI(max, 136, 0xe0d4d31, 0xe0d4d31 ,0x58 )
+    TEST_D_DD(max, 137, 0x787135d1, 0x787135d1 ,0x14c4da7b )
+    TEST_D_DD(max.b, 138, 0x316b2c0f, 0x316bd4cb ,0x2b2c0f )
+    TEST_D_DD(max.bu, 139, 0x5f88a94e, 0x4675a04e ,0x5f88a92b )
+    TEST_D_DD(max.h, 140, 0x532f72fd, 0x532fad08 ,0x4b1272fd )
+    TEST_D_DD(max.hu, 141, 0xeed88225, 0x116b7eea ,0xeed88225 )
+    TEST_D_DI(max.u, 142, 0xf342d496, 0xf342d496 ,0x38 )
+    TEST_D_DD(max.u, 143, 0xdd15066d, 0xdd15066d ,0xf556c66 )
+    TEST_D_DI(min, 144, 0xdd, 0x731a9dec ,0xdd )
+    TEST_D_DD(min, 145, 0x23ed2038, 0x2e3f1040 ,0x23ed2038 )
+    TEST_D_DD(min.b, 146, 0xf1aba6b6, 0x26aba6b6 ,0xf17eb628 )
+    TEST_D_DD(min.bu, 147, 0x3f500949, 0x8a500c52 ,0x3fe70949 )
+    TEST_D_DD(min.h, 148, 0xad296b7, 0xe917617 ,0xad296b7 )
+    TEST_D_DD(min.hu, 149, 0x859351e, 0xc6a351e ,0x8595c29 )
+    TEST_D_DI(min.u, 150, 0x3, 0x8e14bfbf ,0x3 )
+    TEST_D_DD(min.u, 151, 0x371cf628, 0x371cf628 ,0xe837ca8f )
+    TEST_D_I(mov, 152, 0x391, 0x391 )
+    TEST_E_I(mov, 153, 0x4612 ,0x0, 0x4612 )
+    TEST_D_D(mov, 154, 0x57de4d85, 0x57de4d85 )
+    TEST_E_D(mov, 155, 0x81fcfe47 ,0xffffffff, 0x81fcfe47 )
+    TEST_E_DD(mov, 156, 0xa33b7b80 ,0x8a2a74b7, 0x8a2a74b7 ,0xa33b7b80 )
+    TEST_D15_I(mov, 157, 0x3b, 0x3b )
+    TEST_D_I(mov, 158, 0x2, 0x2 )
+    TEST_E_I(mov, 159, 0x1 ,0x0, 0x1 )
+    TEST_D_D(mov, 160, 0x1557688b, 0x1557688b )
+    TEST_D_I(mov.u, 161, 0x502, 0x502 )
+    TEST_D_I(movh, 162, 0x60ea0000, 0x60ea)
+    TEST_D_DI(nand, 163, 0xfffffffe, 0x291af609 ,0xd7 )
+    TEST_D_DD(nand, 164, 0xfaffe4fe, 0x270e5faf ,0xcd613b01 )
+    TEST_D_DIDI(nand.t, 165, 0x1, 0xe10d5151 ,0x1 ,0x84f18d6b ,0x7 )
+    TEST_D_DI(ne, 166, 0x1, 0xed148b6 ,0x66 )
+    TEST_D_DD(ne, 167, 0x1, 0x9b38284a ,0x25948edd )
+    TEST_D_DI(nor, 168, 0x77f45c1a, 0x880ba324 ,0xe5 )
+    TEST_D_DD(nor, 169, 0x2c8103c0, 0x93382c3f ,0x5266d42b )
+    TEST_D_DIDI(nor.t, 170, 0x1, 0x3f964a10 ,0x7 ,0x54e26b8e ,0x3 )
+    TEST_D_DI(or, 171, 0xbf29afdf, 0xbf29afd3 ,0x4e )
+    TEST_D_DD(or, 172, 0xfbefe7cf, 0x2a896747 ,0xdb66a2ce )
+    TEST_D15_I(or, 173, 0xb, 0xb )
+    TEST_D_D(or, 174, 0x3ef404a0, 0x3ef404a0 )
+    TEST_D_DIDI(or.and.t, 175, 0x1, 0x1e09424a ,0x3 ,0xe427b416 ,0x3 )
+    TEST_D_DIDI(or.andn.t, 176, 0x0, 0x4a560efb ,0x1 ,0xf0596f84 ,0x3 )
+    TEST_D_DI(or.eq, 177, 0x0, 0xee8c7017 ,0xcf )
+    TEST_D_DD(or.eq, 178, 0x0, 0xc33e8cf0 ,0x139c3f75 )
+    TEST_D_DI(or.ge, 179, 0x1, 0x4845ad04 ,0xf1 )
+    TEST_D_DD(or.ge, 180, 0x1, 0x687040a1 ,0xf61bdd8c )
+    TEST_D_DI(or.ge.u, 181, 0x1, 0x55edca06 ,0xa1 )
+    TEST_D_DD(or.ge.u, 182, 0x0, 0x8c975e46 ,0xd26c95ea )
+    TEST_D_DI(or.lt, 183, 0x1, 0xbcb87506 ,0x43 )
+    TEST_D_DD(or.lt, 184, 0x0, 0x2c9ea431 ,0x1d1515 )
+    TEST_D_DI(or.lt.u, 185, 0x0, 0x7bbfdf3b ,0xe7 )
+    TEST_D_DD(or.lt.u, 186, 0x1, 0x2f71485e ,0xe9219409 )
+    TEST_D_DI(or.ne, 187, 0x1, 0xc9b87ffc ,0x65 )
+    TEST_D_DD(or.ne, 188, 0x1, 0xd5746862 ,0x72d5cbc1 )
+    TEST_D_DIDI(or.nor.t, 189, 0x0, 0xa0d6cc1 ,0x7 ,0x38e6fc83 ,0x1 )
+    TEST_D_DIDI(or.or.t, 190, 0x1, 0x85546ea7 ,0x4 ,0xffd58bc6 ,0x2 )
+    TEST_D_DIDI(or.t, 191, 0x0, 0xd594ef27 ,0x3 ,0xdb878237 ,0x4 )
+    TEST_D_DI(orn, 192, 0xffffffdf, 0xc8b4cb5d ,0x64 )
+    TEST_D_DD(orn, 193, 0xf2ffd5eb, 0xe2ef556a ,0xaf6d3a3e )
+    TEST_D_DIDI(orn.t, 194, 0x1, 0xb511c09 ,0x3 ,0x209bbd86 ,0x7 )
+    TEST_D_ED(pack, 195, 0x803d04a8, 0x3d04a871 ,0x50637a2d ,0x86ec2f85 )
+    TEST_D_D(parity, 196, 0x101, 0x6033fd4c )
+    TEST_D_D(popcnt.w, 197, 0x15, 0xed7dcbc6 )
+    TEST_D_DI(rsub, 198, 0x4ee91cd3, 0xb116e3bc ,0x8f )
+    TEST_D_DI(rsubs, 199, 0x923eddd7, 0x6dc122fb ,0xd2 )
+    TEST_D_DI(rsubs.u, 200, 0x0, 0xeea32363 ,0xae )
+    TEST_D_D(sat.b, 201, 0xffffff80, 0x9933174e )
+    TEST_D_D(sat.bu, 202, 0xff, 0x917808d7 )
+    TEST_D_D(sat.h, 203, 0xffff8000, 0xa6d33749 )
+    TEST_D_D(sat.hu, 204, 0xffff, 0x534af788 )
+    TEST_D_DDI(sel, 205, 0x620aac73, 0xf617d4dc ,0x620aac73 ,0x53 )
+    TEST_D_DDD(sel, 206, 0x133a028, 0xb8a3faae ,0x133a028 ,0x9042e62e )
+    TEST_D_DDI(seln, 207, 0x8, 0x4a449741 ,0x5354950a ,0x8 )
+    TEST_D_DDD(seln, 208, 0x4f8b1cda, 0x9e3173c3 ,0x4a6f65e9 ,0x4f8b1cda )
+    TEST_D_DI(sh, 209, 0x97000000, 0x56ffbcb8 ,0xd5 )
+    TEST_D_DD(sh, 210, 0x225, 0x112c2fff ,0x5f7f64ad )
+    TEST_D_I(sh, 211, 0x0, 0x6 )
+    TEST_D_DIDI(sh.and.t, 212, 0x1, 0xfba22cf9 ,0x5 ,0xfda859c ,0x6 )
+    TEST_D_DIDI(sh.andn.t, 213, 0x1, 0xf22e1491 ,0x7 ,0x23ac3c36 ,0x3 )
+    TEST_D_DI(sh.eq, 214, 0x0, 0xda3960 ,0x9d )
+    TEST_D_DD(sh.eq, 215, 0x0, 0xf76d811e ,0x6eaa1a5e )
+    TEST_D_DI(sh.ge, 216, 0x0, 0xbb006b34 ,0x4 )
+    TEST_D_DD(sh.ge, 217, 0x0, 0xee02bc23 ,0xdaf2111 )
+    TEST_D_DI(sh.ge.u, 218, 0x1, 0xc8909dce ,0x53 )
+    TEST_D_DD(sh.ge.u, 219, 0x1, 0x5ebe1b63 ,0x2c380da6 )
+    TEST_D_DI(sh.h, 220, 0x32002d00, 0x6032a92d ,0xc8 )
+    TEST_D_DD(sh.h, 221, 0x780878, 0xc00fc10f ,0x670e07a3 )
+    TEST_D_DI(sh.lt, 222, 0x1, 0xd55620a0 ,0x28 )
+    TEST_D_DD(sh.lt, 223, 0x1, 0xbab4c4f8 ,0xd6b23303 )
+    TEST_D_DI(sh.lt.u, 224, 0x0, 0x6d1e8ad ,0xbb )
+    TEST_D_DD(sh.lt.u, 225, 0x1, 0xbdc4998 ,0x660a4b5f )
+    TEST_D_DIDI(sh.nand.t, 226, 0x1, 0xfb3bb8d0 ,0x3 ,0x237800c5 ,0x3 )
+    TEST_D_DI(sh.ne, 227, 0x1, 0x5e6bff56 ,0x83 )
+    TEST_D_DD(sh.ne, 228, 0x1, 0x5f53e44b ,0x4aaa9437 )
+    TEST_D_DIDI(sh.nor.t, 229, 0x0, 0x6ee37832 ,0x6 ,0x6296e652 ,0x5 )
+    TEST_D_DIDI(sh.or.t, 230, 0x1, 0xc6079a4e ,0x6 ,0xa81b155a ,0x1 )
+    TEST_D_DIDI(sh.orn.t, 231, 0x1, 0x188eb9ff ,0x6 ,0x35916e9 ,0x2 )
+    TEST_D_DIDI(sh.xnor.t, 232, 0x1, 0x4babd924 ,0x1 ,0x6f28e657 ,0x6 )
+    TEST_D_DIDI(sh.xor.t, 233, 0x0, 0x759dfc75 ,0x3 ,0xac541f56 ,0x3 )
+    TEST_D_DI(sha, 234, 0xb69145c0, 0x62da4517 ,0x46 )
+    TEST_D_DD(sha, 235, 0xccd8e400, 0x25333639 ,0xb4e65a0a )
+    TEST_D_I(sha, 236, 0x0, 0x5 )
+    TEST_D_DI(sha.h, 237, 0xf8404f80, 0x8fe1d53e ,0x6 )
+    TEST_D_DD(sha.h, 238, 0x10006000, 0x84010b96 ,0xc20875ac )
+    TEST_D_DI(shas, 239, 0x7fffffff, 0x539952ab ,0x1f )
+    TEST_D_DD(shas, 240, 0x20b5a5, 0x416b4be8 ,0x11eb83b7 )
 
     TEST_PASSFAIL
-- 
2.42.0

[PULL 19/21] tests/tcg/tricore: Add test from 'shuffle' to 'xor.t'

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-9-kbastian@mail.uni-paderborn.de>
---
 tests/tcg/tricore/asm/test_arith.S | 34 ++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/tests/tcg/tricore/asm/test_arith.S b/tests/tcg/tricore/asm/test_arith.S
index 728509cfa9..02637f89f9 100644
--- a/tests/tcg/tricore/asm/test_arith.S
+++ b/tests/tcg/tricore/asm/test_arith.S
@@ -242,5 +242,39 @@ _start:
     TEST_D_DD(sha.h, 238, 0x10006000, 0x84010b96 ,0xc20875ac )
     TEST_D_DI(shas, 239, 0x7fffffff, 0x539952ab ,0x1f )
     TEST_D_DD(shas, 240, 0x20b5a5, 0x416b4be8 ,0x11eb83b7 )
+    TEST_D_DI(shuffle, 241, 0xed28c9ed, 0x28e9edc9 ,0x71 )
+    TEST_D_DD(sub, 242, 0x3806b676, 0x56f5e4bc ,0x1eef2e46 )
+    TEST_D_D(sub, 243, 0xc98e16b7, 0x3671e949 )
+    TEST_D_D15D(sub, 244, 0xf5bbbabd, 0x6a8db6c ,0x10ed20af )
+    TEST_D15_DD(sub, 245, 0x5618f5a0, 0xa6342636 ,0x501b3096 )
+    TEST_D_DD(sub.b, 246, 0x9ced6d25, 0x28dbb9ee ,0x8cee4cc9 )
+    TEST_D_DD(sub.h, 247, 0xc80b12d0, 0xbe0897d3 ,0xf5fd8503 )
+    TEST_D_DD(subc, 248, 0xbeeccedb, 0x2164d45a ,0x6278057e )
+    TEST_D_DD(subs, 249, 0x90d370bc, 0x95060d13 ,0x4329c57 )
+    TEST_D_D(subs, 250, 0xd89c4149, 0x2763beb7 )
+    TEST_D_DD(subs.h, 251, 0xad93dfea, 0x2c97e0d1 ,0x7f0400e7 )
+    TEST_D_DD(subs.hu, 252, 0x33f6, 0xa768372d ,0xc80b0337 )
+    TEST_D_DD(subs.u, 253, 0x0, 0x7084c694 ,0x90c2f594 )
+    TEST_D_DD(subx, 254, 0xd19a2948, 0x7c40dcf9 ,0xaaa6b3b1 )
+    TEST_E_D(unpack, 255, 0x6405b000 ,0xffffffa5, 0x12480b60 )
+    TEST_D_DI(xnor, 256, 0x83b45e8d, 0x7c4ba167 ,0x15 )
+    TEST_D_DD(xnor, 257, 0x6808b995, 0x2fdb8402 ,0xb82cc268 )
+    TEST_D_DIDI(xnor.t, 258, 0x1, 0x490ac395 ,0x6 ,0x6c41105b ,0x6 )
+    TEST_D_DI(xor, 259, 0x2f27c804, 0x2f27c860 ,0x64 )
+    TEST_D_DD(xor, 260, 0xa020af5b, 0x67f62bea ,0xc7d684b1 )
+    TEST_D_D(xor, 261, 0xbc28874, 0xbc28874 )
+    TEST_D_DI(xor.eq, 262, 0x0, 0xee9e03cc ,0x7b )
+    TEST_D_DD(xor.eq, 263, 0x0, 0x74f79928 ,0x2d3ec476 )
+    TEST_D_DI(xor.ge, 264, 0x0, 0xcf2296f1 ,0xf0 )
+    TEST_D_DD(xor.ge, 265, 0x0, 0xf9915543 ,0x20cb6ab7 )
+    TEST_D_DI(xor.ge.u, 266, 0x1, 0xaa8a78f6 ,0xce )
+    TEST_D_DD(xor.ge.u, 267, 0x0, 0x94e9f87 ,0xab43f3ce )
+    TEST_D_DI(xor.lt, 268, 0x0, 0x3412e315 ,0xcb )
+    TEST_D_DD(xor.lt, 269, 0x1, 0x5571b703 ,0x6a9008a3 )
+    TEST_D_DI(xor.lt.u, 270, 0x0, 0x66a0a3c0 ,0xe1 )
+    TEST_D_DD(xor.lt.u, 271, 0x0, 0xa66deb02 ,0x7dd7b425 )
+    TEST_D_DI(xor.ne, 272, 0x1, 0x147b3e3a ,0xfa )
+    TEST_D_DD(xor.ne, 273, 0x1, 0x92147ec0 ,0xa697f601 )
+    TEST_D_DIDI(xor.t, 274, 0x0, 0xed9ea075 ,0x7 ,0x13f5d03c ,0x7 )
 
     TEST_PASSFAIL
-- 
2.42.0

[PULL 20/21] target/tricore: Remove CSFRs from cpu.h

[Bastian Koppelmann]

these are already defined in 'csfr.h.inc'. We don't need to duplicate
these registers.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-10-kbastian@mail.uni-paderborn.de>
---
 target/tricore/cpu.h | 143 +++----------------------------------------
 1 file changed, 9 insertions(+), 134 deletions(-)

diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 3708405be8..1cace96b01 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -30,150 +30,25 @@ typedef struct CPUArchState {
     /* GPR Register */
     uint32_t gpr_a[16];
     uint32_t gpr_d[16];
-    /* CSFR Register */
-    uint32_t PCXI;
 /* Frequently accessed PSW_USB bits are stored separately for efficiency.
        This contains all the other bits.  Use psw_{read,write} to access
        the whole PSW.  */
     uint32_t PSW;
-
-    /* PSW flag cache for faster execution
-    */
+    /* PSW flag cache for faster execution */
     uint32_t PSW_USB_C;
     uint32_t PSW_USB_V;   /* Only if bit 31 set, then flag is set  */
     uint32_t PSW_USB_SV;  /* Only if bit 31 set, then flag is set  */
     uint32_t PSW_USB_AV;  /* Only if bit 31 set, then flag is set. */
     uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
 
-    uint32_t PC;
-    uint32_t SYSCON;
-    uint32_t CPU_ID;
-    uint32_t CORE_ID;
-    uint32_t BIV;
-    uint32_t BTV;
-    uint32_t ISP;
-    uint32_t ICR;
-    uint32_t FCX;
-    uint32_t LCX;
-    uint32_t COMPAT;
-
-    /* Mem Protection Register */
-    uint32_t DPR0_0L;
-    uint32_t DPR0_0U;
-    uint32_t DPR0_1L;
-    uint32_t DPR0_1U;
-    uint32_t DPR0_2L;
-    uint32_t DPR0_2U;
-    uint32_t DPR0_3L;
-    uint32_t DPR0_3U;
-
-    uint32_t DPR1_0L;
-    uint32_t DPR1_0U;
-    uint32_t DPR1_1L;
-    uint32_t DPR1_1U;
-    uint32_t DPR1_2L;
-    uint32_t DPR1_2U;
-    uint32_t DPR1_3L;
-    uint32_t DPR1_3U;
-
-    uint32_t DPR2_0L;
-    uint32_t DPR2_0U;
-    uint32_t DPR2_1L;
-    uint32_t DPR2_1U;
-    uint32_t DPR2_2L;
-    uint32_t DPR2_2U;
-    uint32_t DPR2_3L;
-    uint32_t DPR2_3U;
-
-    uint32_t DPR3_0L;
-    uint32_t DPR3_0U;
-    uint32_t DPR3_1L;
-    uint32_t DPR3_1U;
-    uint32_t DPR3_2L;
-    uint32_t DPR3_2U;
-    uint32_t DPR3_3L;
-    uint32_t DPR3_3U;
-
-    uint32_t CPR0_0L;
-    uint32_t CPR0_0U;
-    uint32_t CPR0_1L;
-    uint32_t CPR0_1U;
-    uint32_t CPR0_2L;
-    uint32_t CPR0_2U;
-    uint32_t CPR0_3L;
-    uint32_t CPR0_3U;
-
-    uint32_t CPR1_0L;
-    uint32_t CPR1_0U;
-    uint32_t CPR1_1L;
-    uint32_t CPR1_1U;
-    uint32_t CPR1_2L;
-    uint32_t CPR1_2U;
-    uint32_t CPR1_3L;
-    uint32_t CPR1_3U;
-
-    uint32_t CPR2_0L;
-    uint32_t CPR2_0U;
-    uint32_t CPR2_1L;
-    uint32_t CPR2_1U;
-    uint32_t CPR2_2L;
-    uint32_t CPR2_2U;
-    uint32_t CPR2_3L;
-    uint32_t CPR2_3U;
-
-    uint32_t CPR3_0L;
-    uint32_t CPR3_0U;
-    uint32_t CPR3_1L;
-    uint32_t CPR3_1U;
-    uint32_t CPR3_2L;
-    uint32_t CPR3_2U;
-    uint32_t CPR3_3L;
-    uint32_t CPR3_3U;
-
-    uint32_t DPM0;
-    uint32_t DPM1;
-    uint32_t DPM2;
-    uint32_t DPM3;
-
-    uint32_t CPM0;
-    uint32_t CPM1;
-    uint32_t CPM2;
-    uint32_t CPM3;
-
-    /* Memory Management Registers */
-    uint32_t MMU_CON;
-    uint32_t MMU_ASI;
-    uint32_t MMU_TVA;
-    uint32_t MMU_TPA;
-    uint32_t MMU_TPX;
-    uint32_t MMU_TFA;
-    /* {1.3.1 only */
-    uint32_t BMACON;
-    uint32_t SMACON;
-    uint32_t DIEAR;
-    uint32_t DIETR;
-    uint32_t CCDIER;
-    uint32_t MIECON;
-    uint32_t PIEAR;
-    uint32_t PIETR;
-    uint32_t CCPIER;
-    /*} */
-    /* Debug Registers */
-    uint32_t DBGSR;
-    uint32_t EXEVT;
-    uint32_t CREVT;
-    uint32_t SWEVT;
-    uint32_t TR0EVT;
-    uint32_t TR1EVT;
-    uint32_t DMS;
-    uint32_t DCX;
-    uint32_t DBGTCR;
-    uint32_t CCTRL;
-    uint32_t CCNT;
-    uint32_t ICNT;
-    uint32_t M1CNT;
-    uint32_t M2CNT;
-    uint32_t M3CNT;
+#define R(ADDR, NAME, FEATURE) uint32_t NAME;
+#define A(ADDR, NAME, FEATURE) uint32_t NAME;
+#define E(ADDR, NAME, FEATURE) uint32_t NAME;
+#include "csfr.h.inc"
+#undef R
+#undef A
+#undef E
+
     /* Floating Point Registers */
     float_status fp_status;
 
-- 
2.42.0

[PULL 21/21] target/tricore: Change effective address (ea) to target_ulong

[Bastian Koppelmann]

as this is an effective address and those cannot be signed,
it should not be a signed integer.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-11-kbastian@mail.uni-paderborn.de>
---
 target/tricore/op_helper.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 0cf8eb50bd..ba9c4444b3 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2458,7 +2458,7 @@ static bool cdc_zero(target_ulong *psw)
     return count == 0;
 }
 
-static void save_context_upper(CPUTriCoreState *env, int ea)
+static void save_context_upper(CPUTriCoreState *env, target_ulong ea)
 {
     cpu_stl_data(env, ea, env->PCXI);
     cpu_stl_data(env, ea+4, psw_read(env));
@@ -2478,7 +2478,7 @@ static void save_context_upper(CPUTriCoreState *env, int ea)
     cpu_stl_data(env, ea+60, env->gpr_d[15]);
 }
 
-static void save_context_lower(CPUTriCoreState *env, int ea)
+static void save_context_lower(CPUTriCoreState *env, target_ulong ea)
 {
     cpu_stl_data(env, ea, env->PCXI);
     cpu_stl_data(env, ea+4, env->gpr_a[11]);
@@ -2498,7 +2498,7 @@ static void save_context_lower(CPUTriCoreState *env, int ea)
     cpu_stl_data(env, ea+60, env->gpr_d[7]);
 }
 
-static void restore_context_upper(CPUTriCoreState *env, int ea,
+static void restore_context_upper(CPUTriCoreState *env, target_ulong ea,
                                   target_ulong *new_PCXI, target_ulong *new_PSW)
 {
     *new_PCXI = cpu_ldl_data(env, ea);
@@ -2519,7 +2519,7 @@ static void restore_context_upper(CPUTriCoreState *env, int ea,
     env->gpr_d[15] = cpu_ldl_data(env, ea+60);
 }
 
-static void restore_context_lower(CPUTriCoreState *env, int ea,
+static void restore_context_lower(CPUTriCoreState *env, target_ulong ea,
                                   target_ulong *ra, target_ulong *pcxi)
 {
     *pcxi = cpu_ldl_data(env, ea);
@@ -2763,26 +2763,26 @@ void helper_rfm(CPUTriCoreState *env)
     }
 }
 
-void helper_ldlcx(CPUTriCoreState *env, uint32_t ea)
+void helper_ldlcx(CPUTriCoreState *env, target_ulong ea)
 {
     uint32_t dummy;
     /* insn doesn't load PCXI and RA */
     restore_context_lower(env, ea, &dummy, &dummy);
 }
 
-void helper_lducx(CPUTriCoreState *env, uint32_t ea)
+void helper_lducx(CPUTriCoreState *env, target_ulong ea)
 {
     uint32_t dummy;
     /* insn doesn't load PCXI and PSW */
     restore_context_upper(env, ea, &dummy, &dummy);
 }
 
-void helper_stlcx(CPUTriCoreState *env, uint32_t ea)
+void helper_stlcx(CPUTriCoreState *env, target_ulong ea)
 {
     save_context_lower(env, ea);
 }
 
-void helper_stucx(CPUTriCoreState *env, uint32_t ea)
+void helper_stucx(CPUTriCoreState *env, target_ulong ea)
 {
     save_context_upper(env, ea);
 }
-- 
2.42.0

Re: [PULL 00/21] tricore queue

[Bastian Koppelmann]

On Wed, Sep 27, 2023 at 11:35:31AM +0200, Bastian Koppelmann wrote:
> The following changes since commit 11a629d246e4e7785a6f0efb99bd15a32c04feda:
> 
>   Merge tag 'pull-nbd-2023-09-25' of https://repo.or.cz/qemu/ericb into staging (2023-09-26 09:04:23 -0400)
> 
> are available in the Git repository at:
> 
>   https://github.com/bkoppelmann/qemu.git tags/pull-tricore-20230927
> 
> for you to fetch changes up to 32dd1f0b4bf5f38f37434b0c8fe6c8d86e093b2b:
> 
>   target/tricore: Change effective address (ea) to target_ulong (2023-09-27 11:22:42 +0200)
> 
> ----------------------------------------------------------------
> - Add FTOU, CRCN, FTOHP, and HPTOF insns
> - Add test for arithmetic TriCore insns
> 
> ----------------------------------------------------------------
> Bastian Koppelmann (21):
>       tests/tcg/tricore: Bump cpu to tc37x
>       target/tricore: Implement CRCN insn
>       target/tricore: Correctly handle FPU RM from PSW
>       target/tricore: Implement FTOU insn
>       target/tricore: Clarify special case for FTOUZ insn
>       target/tricore: Implement ftohp insn
>       target/tricore: Implement hptof insn
>       target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
>       target/tricore: Swap src and dst reg for RCRR_INSERT
>       target/tricore: Replace cpu_*_code with translator_*
>       target/tricore: Fix FTOUZ being ISA v1.3.1 up
>       tests/tcg/tricore: Extended and non-extened regs now match
>       hw/tricore: Log failing test in testdevice
>       tests/tcg: Reset result register after each test
>       tests/tcg/tricore: Add test for all arith insns up to addx
>       tests/tcg/tricore: Add test from 'and' to 'csub'
>       tests/tcg/tricore: Add test from 'dextr' to 'lt'
>       tests/tcg/tricore: Add test from 'max' to 'shas'
>       tests/tcg/tricore: Add test from 'shuffle' to 'xor.t'
>       target/tricore: Remove CSFRs from cpu.h
>       target/tricore: Change effective address (ea) to target_ulong
> 
>  hw/tricore/tricore_testdevice.c           |   4 +
>  target/tricore/cpu.h                      | 143 +--------------
>  target/tricore/fpu_helper.c               | 111 ++++++++++++
>  target/tricore/helper.c                   |  19 +-
>  target/tricore/helper.h                   |   4 +
>  target/tricore/op_helper.c                |  79 ++++++++-
>  target/tricore/translate.c                |  56 ++++--
>  target/tricore/tricore-opcodes.h          |   3 +
>  tests/tcg/tricore/Makefile.softmmu-target |   7 +-
>  tests/tcg/tricore/asm/macros.h            | 190 +++++++++++++++++---
>  tests/tcg/tricore/asm/sas.py              |  21 +++

Don't merge this one. Somehow a file slipped in, that should not have been in
the merge. Sorry for the inconvenience. I'll respin.

Cheers,
Bastian