From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: kbastian@mail.uni-paderborn.de
Subject: [PULL 12/21] tests/tcg/tricore: Extended and non-extened regs now match
Date: Wed, 27 Sep 2023 11:35:43 +0200 [thread overview]
Message-ID: <20230927093552.493279-13-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20230927093552.493279-1-kbastian@mail.uni-paderborn.de>
RSx for d regs and e regs now use the same numbering. This makes sure
that mixing d and e registers in an insn test will not overwrite data
between registers.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-2-kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 38 +++++++++++++++++-----------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 17e696bef5..0f349dbf1e 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -12,31 +12,31 @@
#define TESTDEV_ADDR 0xf0000000
/* Register definitions */
#define DREG_RS1 %d0
-#define DREG_RS2 %d1
-#define DREG_RS3 %d2
-#define DREG_CALC_RESULT %d3
-#define DREG_CALC_PSW %d4
-#define DREG_CORRECT_PSW %d5
-#define DREG_TEMP_LI %d10
-#define DREG_TEMP %d11
-#define DREG_TEST_NUM %d14
-#define DREG_CORRECT_RESULT %d15
-#define DREG_CORRECT_RESULT_2 %d13
+#define DREG_RS2 %d2
+#define DREG_RS3 %d4
+#define DREG_CALC_RESULT %d5
+#define DREG_CALC_PSW %d6
+#define DREG_CORRECT_PSW %d7
+#define DREG_TEMP_LI %d13
+#define DREG_TEMP %d14
+#define DREG_TEST_NUM %d8
+#define DREG_CORRECT_RESULT %d9
+#define DREG_CORRECT_RESULT_2 %d10
#define AREG_ADDR %a0
#define AREG_CORRECT_RESULT %a3
#define DREG_DEV_ADDR %a15
-#define EREG_RS1 %e6
-#define EREG_RS1_LO %d6
-#define EREG_RS1_HI %d7
-#define EREG_RS2 %e8
-#define EREG_RS2_LO %d8
-#define EREG_RS2_HI %d9
-#define EREG_CALC_RESULT %e8
-#define EREG_CALC_RESULT_HI %d9
-#define EREG_CALC_RESULT_LO %d8
+#define EREG_RS1 %e0
+#define EREG_RS1_LO %d0
+#define EREG_RS1_HI %d1
+#define EREG_RS2 %e2
+#define EREG_RS2_LO %d2
+#define EREG_RS2_HI %d3
+#define EREG_CALC_RESULT %e6
+#define EREG_CALC_RESULT_LO %d6
+#define EREG_CALC_RESULT_HI %d7
#define EREG_CORRECT_RESULT_LO %d0
#define EREG_CORRECT_RESULT_HI %d1
--
2.42.0
next prev parent reply other threads:[~2023-09-27 9:39 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-27 9:35 [PULL 00/21] tricore queue Bastian Koppelmann
2023-09-27 9:35 ` [PULL 01/21] tests/tcg/tricore: Bump cpu to tc37x Bastian Koppelmann
2023-09-27 9:35 ` [PULL 02/21] target/tricore: Implement CRCN insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 03/21] target/tricore: Correctly handle FPU RM from PSW Bastian Koppelmann
2023-09-27 9:35 ` [PULL 04/21] target/tricore: Implement FTOU insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 05/21] target/tricore: Clarify special case for FTOUZ insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 06/21] target/tricore: Implement ftohp insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 07/21] target/tricore: Implement hptof insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 08/21] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 Bastian Koppelmann
2023-09-27 9:35 ` [PULL 09/21] target/tricore: Swap src and dst reg for RCRR_INSERT Bastian Koppelmann
2023-09-27 9:35 ` [PULL 10/21] target/tricore: Replace cpu_*_code with translator_* Bastian Koppelmann
2023-09-27 9:35 ` [PULL 11/21] target/tricore: Fix FTOUZ being ISA v1.3.1 up Bastian Koppelmann
2023-09-27 9:35 ` Bastian Koppelmann [this message]
2023-09-27 9:35 ` [PULL 13/21] hw/tricore: Log failing test in testdevice Bastian Koppelmann
2023-09-27 9:35 ` [PULL 14/21] tests/tcg: Reset result register after each test Bastian Koppelmann
2023-09-27 9:35 ` [PULL 15/21] tests/tcg/tricore: Add test for all arith insns up to addx Bastian Koppelmann
2023-09-27 9:35 ` [PULL 16/21] tests/tcg/tricore: Add test from 'and' to 'csub' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 17/21] tests/tcg/tricore: Add test from 'dextr' to 'lt' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 18/21] tests/tcg/tricore: Add test from 'max' to 'shas' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 19/21] tests/tcg/tricore: Add test from 'shuffle' to 'xor.t' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 20/21] target/tricore: Remove CSFRs from cpu.h Bastian Koppelmann
2023-09-27 9:35 ` [PULL 21/21] target/tricore: Change effective address (ea) to target_ulong Bastian Koppelmann
2023-09-27 17:40 ` [PULL 00/21] tricore queue Bastian Koppelmann
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