From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: kbastian@mail.uni-paderborn.de
Subject: [PULL 20/21] target/tricore: Remove CSFRs from cpu.h
Date: Wed, 27 Sep 2023 11:35:51 +0200 [thread overview]
Message-ID: <20230927093552.493279-21-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20230927093552.493279-1-kbastian@mail.uni-paderborn.de>
these are already defined in 'csfr.h.inc'. We don't need to duplicate
these registers.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-10-kbastian@mail.uni-paderborn.de>
---
target/tricore/cpu.h | 143 +++----------------------------------------
1 file changed, 9 insertions(+), 134 deletions(-)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 3708405be8..1cace96b01 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -30,150 +30,25 @@ typedef struct CPUArchState {
/* GPR Register */
uint32_t gpr_a[16];
uint32_t gpr_d[16];
- /* CSFR Register */
- uint32_t PCXI;
/* Frequently accessed PSW_USB bits are stored separately for efficiency.
This contains all the other bits. Use psw_{read,write} to access
the whole PSW. */
uint32_t PSW;
-
- /* PSW flag cache for faster execution
- */
+ /* PSW flag cache for faster execution */
uint32_t PSW_USB_C;
uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */
uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */
uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
- uint32_t PC;
- uint32_t SYSCON;
- uint32_t CPU_ID;
- uint32_t CORE_ID;
- uint32_t BIV;
- uint32_t BTV;
- uint32_t ISP;
- uint32_t ICR;
- uint32_t FCX;
- uint32_t LCX;
- uint32_t COMPAT;
-
- /* Mem Protection Register */
- uint32_t DPR0_0L;
- uint32_t DPR0_0U;
- uint32_t DPR0_1L;
- uint32_t DPR0_1U;
- uint32_t DPR0_2L;
- uint32_t DPR0_2U;
- uint32_t DPR0_3L;
- uint32_t DPR0_3U;
-
- uint32_t DPR1_0L;
- uint32_t DPR1_0U;
- uint32_t DPR1_1L;
- uint32_t DPR1_1U;
- uint32_t DPR1_2L;
- uint32_t DPR1_2U;
- uint32_t DPR1_3L;
- uint32_t DPR1_3U;
-
- uint32_t DPR2_0L;
- uint32_t DPR2_0U;
- uint32_t DPR2_1L;
- uint32_t DPR2_1U;
- uint32_t DPR2_2L;
- uint32_t DPR2_2U;
- uint32_t DPR2_3L;
- uint32_t DPR2_3U;
-
- uint32_t DPR3_0L;
- uint32_t DPR3_0U;
- uint32_t DPR3_1L;
- uint32_t DPR3_1U;
- uint32_t DPR3_2L;
- uint32_t DPR3_2U;
- uint32_t DPR3_3L;
- uint32_t DPR3_3U;
-
- uint32_t CPR0_0L;
- uint32_t CPR0_0U;
- uint32_t CPR0_1L;
- uint32_t CPR0_1U;
- uint32_t CPR0_2L;
- uint32_t CPR0_2U;
- uint32_t CPR0_3L;
- uint32_t CPR0_3U;
-
- uint32_t CPR1_0L;
- uint32_t CPR1_0U;
- uint32_t CPR1_1L;
- uint32_t CPR1_1U;
- uint32_t CPR1_2L;
- uint32_t CPR1_2U;
- uint32_t CPR1_3L;
- uint32_t CPR1_3U;
-
- uint32_t CPR2_0L;
- uint32_t CPR2_0U;
- uint32_t CPR2_1L;
- uint32_t CPR2_1U;
- uint32_t CPR2_2L;
- uint32_t CPR2_2U;
- uint32_t CPR2_3L;
- uint32_t CPR2_3U;
-
- uint32_t CPR3_0L;
- uint32_t CPR3_0U;
- uint32_t CPR3_1L;
- uint32_t CPR3_1U;
- uint32_t CPR3_2L;
- uint32_t CPR3_2U;
- uint32_t CPR3_3L;
- uint32_t CPR3_3U;
-
- uint32_t DPM0;
- uint32_t DPM1;
- uint32_t DPM2;
- uint32_t DPM3;
-
- uint32_t CPM0;
- uint32_t CPM1;
- uint32_t CPM2;
- uint32_t CPM3;
-
- /* Memory Management Registers */
- uint32_t MMU_CON;
- uint32_t MMU_ASI;
- uint32_t MMU_TVA;
- uint32_t MMU_TPA;
- uint32_t MMU_TPX;
- uint32_t MMU_TFA;
- /* {1.3.1 only */
- uint32_t BMACON;
- uint32_t SMACON;
- uint32_t DIEAR;
- uint32_t DIETR;
- uint32_t CCDIER;
- uint32_t MIECON;
- uint32_t PIEAR;
- uint32_t PIETR;
- uint32_t CCPIER;
- /*} */
- /* Debug Registers */
- uint32_t DBGSR;
- uint32_t EXEVT;
- uint32_t CREVT;
- uint32_t SWEVT;
- uint32_t TR0EVT;
- uint32_t TR1EVT;
- uint32_t DMS;
- uint32_t DCX;
- uint32_t DBGTCR;
- uint32_t CCTRL;
- uint32_t CCNT;
- uint32_t ICNT;
- uint32_t M1CNT;
- uint32_t M2CNT;
- uint32_t M3CNT;
+#define R(ADDR, NAME, FEATURE) uint32_t NAME;
+#define A(ADDR, NAME, FEATURE) uint32_t NAME;
+#define E(ADDR, NAME, FEATURE) uint32_t NAME;
+#include "csfr.h.inc"
+#undef R
+#undef A
+#undef E
+
/* Floating Point Registers */
float_status fp_status;
--
2.42.0
next prev parent reply other threads:[~2023-09-27 9:37 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-27 9:35 [PULL 00/21] tricore queue Bastian Koppelmann
2023-09-27 9:35 ` [PULL 01/21] tests/tcg/tricore: Bump cpu to tc37x Bastian Koppelmann
2023-09-27 9:35 ` [PULL 02/21] target/tricore: Implement CRCN insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 03/21] target/tricore: Correctly handle FPU RM from PSW Bastian Koppelmann
2023-09-27 9:35 ` [PULL 04/21] target/tricore: Implement FTOU insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 05/21] target/tricore: Clarify special case for FTOUZ insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 06/21] target/tricore: Implement ftohp insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 07/21] target/tricore: Implement hptof insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 08/21] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 Bastian Koppelmann
2023-09-27 9:35 ` [PULL 09/21] target/tricore: Swap src and dst reg for RCRR_INSERT Bastian Koppelmann
2023-09-27 9:35 ` [PULL 10/21] target/tricore: Replace cpu_*_code with translator_* Bastian Koppelmann
2023-09-27 9:35 ` [PULL 11/21] target/tricore: Fix FTOUZ being ISA v1.3.1 up Bastian Koppelmann
2023-09-27 9:35 ` [PULL 12/21] tests/tcg/tricore: Extended and non-extened regs now match Bastian Koppelmann
2023-09-27 9:35 ` [PULL 13/21] hw/tricore: Log failing test in testdevice Bastian Koppelmann
2023-09-27 9:35 ` [PULL 14/21] tests/tcg: Reset result register after each test Bastian Koppelmann
2023-09-27 9:35 ` [PULL 15/21] tests/tcg/tricore: Add test for all arith insns up to addx Bastian Koppelmann
2023-09-27 9:35 ` [PULL 16/21] tests/tcg/tricore: Add test from 'and' to 'csub' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 17/21] tests/tcg/tricore: Add test from 'dextr' to 'lt' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 18/21] tests/tcg/tricore: Add test from 'max' to 'shas' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 19/21] tests/tcg/tricore: Add test from 'shuffle' to 'xor.t' Bastian Koppelmann
2023-09-27 9:35 ` Bastian Koppelmann [this message]
2023-09-27 9:35 ` [PULL 21/21] target/tricore: Change effective address (ea) to target_ulong Bastian Koppelmann
2023-09-27 17:40 ` [PULL 00/21] tricore queue Bastian Koppelmann
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230927093552.493279-21-kbastian@mail.uni-paderborn.de \
--to=kbastian@mail.uni-paderborn.de \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).