From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: kbastian@mail.uni-paderborn.de,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PULL 02/21] target/tricore: Implement CRCN insn
Date: Wed, 27 Sep 2023 11:35:33 +0200 [thread overview]
Message-ID: <20230927093552.493279-3-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20230927093552.493279-1-kbastian@mail.uni-paderborn.de>
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-3-kbastian@mail.uni-paderborn.de>
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c | 63 +++++++++++++++++++++++
target/tricore/translate.c | 8 +++
target/tricore/tricore-opcodes.h | 1 +
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/asm/test_crcn.S | 9 ++++
6 files changed, 83 insertions(+)
create mode 100644 tests/tcg/tricore/asm/test_crcn.S
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 31d71eac7a..190645413a 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -134,6 +134,7 @@ DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32_be, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32_le, TCG_CALL_NO_RWG_SE, i32, i32, i32)
+DEF_HELPER_FLAGS_3(crcn, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
DEF_HELPER_FLAGS_2(shuffle, TCG_CALL_NO_RWG_SE, i32, i32, i32)
/* CSA */
DEF_HELPER_2(call, void, env, i32)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 89be1ed648..0cf8eb50bd 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2308,6 +2308,69 @@ uint32_t helper_crc32_le(uint32_t arg0, uint32_t arg1)
return crc32(arg1, buf, 4);
}
+static uint32_t crc_div(uint32_t crc_in, uint32_t data, uint32_t gen,
+ uint32_t n, uint32_t m)
+{
+ uint32_t i;
+
+ data = data << n;
+ for (i = 0; i < m; i++) {
+ if (crc_in & (1u << (n - 1))) {
+ crc_in <<= 1;
+ if (data & (1u << (m - 1))) {
+ crc_in++;
+ }
+ crc_in ^= gen;
+ } else {
+ crc_in <<= 1;
+ if (data & (1u << (m - 1))) {
+ crc_in++;
+ }
+ }
+ data <<= 1;
+ }
+
+ return crc_in;
+}
+
+uint32_t helper_crcn(uint32_t arg0, uint32_t arg1, uint32_t arg2)
+{
+ uint32_t crc_out, crc_in;
+ uint32_t n = extract32(arg0, 12, 4) + 1;
+ uint32_t gen = extract32(arg0, 16, n);
+ uint32_t inv = extract32(arg0, 9, 1);
+ uint32_t le = extract32(arg0, 8, 1);
+ uint32_t m = extract32(arg0, 0, 3) + 1;
+ uint32_t data = extract32(arg1, 0, m);
+ uint32_t seed = extract32(arg2, 0, n);
+
+ if (le == 1) {
+ if (m == 0) {
+ data = 0;
+ } else {
+ data = revbit32(data) >> (32 - m);
+ }
+ }
+
+ if (inv == 1) {
+ seed = ~seed;
+ }
+
+ if (m > n) {
+ crc_in = (data >> (m - n)) ^ seed;
+ } else {
+ crc_in = (data << (n - m)) ^ seed;
+ }
+
+ crc_out = crc_div(crc_in, data, gen, n, m);
+
+ if (inv) {
+ crc_out = ~crc_out;
+ }
+
+ return extract32(crc_out, 0, n);
+}
+
uint32_t helper_shuffle(uint32_t arg0, uint32_t arg1)
{
uint32_t resb;
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 6ae5ccbf72..4e7e18f985 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6669,6 +6669,14 @@ static void decode_rrr_divide(DisasContext *ctx)
gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
+ case OPC2_32_RRR_CRCN:
+ if (has_feature(ctx, TRICORE_FEATURE_162)) {
+ gen_helper_crcn(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ cpu_gpr_d[r3]);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
case OPC2_32_RRR_ADD_F:
gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
break;
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index bc62b73173..f070571665 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1247,6 +1247,7 @@ enum {
OPC2_32_RRR_SUB_F = 0x03,
OPC2_32_RRR_MADD_F = 0x06,
OPC2_32_RRR_MSUB_F = 0x07,
+ OPC2_32_RRR_CRCN = 0x01, /* 1.6.2 up */
};
/*
* RRR1 Format
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index d556201b07..b8d9b33933 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -9,6 +9,7 @@ CFLAGS = -mtc162 -c -I$(TESTS_PATH)
TESTS += test_abs.asm.tst
TESTS += test_bmerge.asm.tst
TESTS += test_clz.asm.tst
+TESTS += test_crcn.asm.tst
TESTS += test_dextr.asm.tst
TESTS += test_dvstep.asm.tst
TESTS += test_fadd.asm.tst
diff --git a/tests/tcg/tricore/asm/test_crcn.S b/tests/tcg/tricore/asm/test_crcn.S
new file mode 100644
index 0000000000..51a22722a3
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_crcn.S
@@ -0,0 +1,9 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+# insn num result rs1 rs2 rs3
+# | | | | | |
+ TEST_D_DDD(crcn, 1, 0x00002bed, 0x0, 0xa10ddeed, 0x0)
+
+ TEST_PASSFAIL
--
2.42.0
next prev parent reply other threads:[~2023-09-27 9:39 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-27 9:35 [PULL 00/21] tricore queue Bastian Koppelmann
2023-09-27 9:35 ` [PULL 01/21] tests/tcg/tricore: Bump cpu to tc37x Bastian Koppelmann
2023-09-27 9:35 ` Bastian Koppelmann [this message]
2023-09-27 9:35 ` [PULL 03/21] target/tricore: Correctly handle FPU RM from PSW Bastian Koppelmann
2023-09-27 9:35 ` [PULL 04/21] target/tricore: Implement FTOU insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 05/21] target/tricore: Clarify special case for FTOUZ insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 06/21] target/tricore: Implement ftohp insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 07/21] target/tricore: Implement hptof insn Bastian Koppelmann
2023-09-27 9:35 ` [PULL 08/21] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 Bastian Koppelmann
2023-09-27 9:35 ` [PULL 09/21] target/tricore: Swap src and dst reg for RCRR_INSERT Bastian Koppelmann
2023-09-27 9:35 ` [PULL 10/21] target/tricore: Replace cpu_*_code with translator_* Bastian Koppelmann
2023-09-27 9:35 ` [PULL 11/21] target/tricore: Fix FTOUZ being ISA v1.3.1 up Bastian Koppelmann
2023-09-27 9:35 ` [PULL 12/21] tests/tcg/tricore: Extended and non-extened regs now match Bastian Koppelmann
2023-09-27 9:35 ` [PULL 13/21] hw/tricore: Log failing test in testdevice Bastian Koppelmann
2023-09-27 9:35 ` [PULL 14/21] tests/tcg: Reset result register after each test Bastian Koppelmann
2023-09-27 9:35 ` [PULL 15/21] tests/tcg/tricore: Add test for all arith insns up to addx Bastian Koppelmann
2023-09-27 9:35 ` [PULL 16/21] tests/tcg/tricore: Add test from 'and' to 'csub' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 17/21] tests/tcg/tricore: Add test from 'dextr' to 'lt' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 18/21] tests/tcg/tricore: Add test from 'max' to 'shas' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 19/21] tests/tcg/tricore: Add test from 'shuffle' to 'xor.t' Bastian Koppelmann
2023-09-27 9:35 ` [PULL 20/21] target/tricore: Remove CSFRs from cpu.h Bastian Koppelmann
2023-09-27 9:35 ` [PULL 21/21] target/tricore: Change effective address (ea) to target_ulong Bastian Koppelmann
2023-09-27 17:40 ` [PULL 00/21] tricore queue Bastian Koppelmann
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