From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: kbastian@mail.uni-paderborn.de
Subject: [PULL v2 00/21] tricore queue
Date: Thu, 28 Sep 2023 10:52:42 +0200 [thread overview]
Message-ID: <20230928085303.511518-1-kbastian@mail.uni-paderborn.de> (raw)
The following changes since commit 36e9aab3c569d4c9ad780473596e18479838d1aa:
migration: Move return path cleanup to main migration thread (2023-09-27 13:58:02 -0400)
are available in the Git repository at:
https://github.com/bkoppelmann/qemu.git tags/pull-tricore-20230928
for you to fetch changes up to 080ca1baa84316a58790b6507de89fabf4c40ec0:
target/tricore: Change effective address (ea) to target_ulong (2023-09-28 10:45:22 +0200)
----------------------------------------------------------------
- Add FTOU, CRCN, FTOHP, and HPTOF insns
- Add test for arithmetic TriCore insns
----------------------------------------------------------------
Changes from v1:
- Removed sas.py file that slipped in patch 15
----------------------------------------------------------------
Bastian Koppelmann (21):
tests/tcg/tricore: Bump cpu to tc37x
target/tricore: Implement CRCN insn
target/tricore: Correctly handle FPU RM from PSW
target/tricore: Implement FTOU insn
target/tricore: Clarify special case for FTOUZ insn
target/tricore: Implement ftohp insn
target/tricore: Implement hptof insn
target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
target/tricore: Swap src and dst reg for RCRR_INSERT
target/tricore: Replace cpu_*_code with translator_*
target/tricore: Fix FTOUZ being ISA v1.3.1 up
tests/tcg/tricore: Extended and non-extened regs now match
hw/tricore: Log failing test in testdevice
tests/tcg: Reset result register after each test
tests/tcg/tricore: Add test for all arith insns up to addx
tests/tcg/tricore: Add test from 'and' to 'csub'
tests/tcg/tricore: Add test from 'dextr' to 'lt'
tests/tcg/tricore: Add test from 'max' to 'shas'
tests/tcg/tricore: Add test from 'shuffle' to 'xor.t'
target/tricore: Remove CSFRs from cpu.h
target/tricore: Change effective address (ea) to target_ulong
hw/tricore/tricore_testdevice.c | 4 +
target/tricore/cpu.h | 143 +--------------
target/tricore/fpu_helper.c | 111 ++++++++++++
target/tricore/helper.c | 19 +-
target/tricore/helper.h | 4 +
target/tricore/op_helper.c | 79 ++++++++-
target/tricore/translate.c | 56 ++++--
target/tricore/tricore-opcodes.h | 3 +
tests/tcg/tricore/Makefile.softmmu-target | 7 +-
tests/tcg/tricore/asm/macros.h | 190 +++++++++++++++++---
tests/tcg/tricore/asm/test_arith.S | 280 ++++++++++++++++++++++++++++++
tests/tcg/tricore/asm/test_crcn.S | 9 +
tests/tcg/tricore/asm/test_ftohp.S | 14 ++
tests/tcg/tricore/asm/test_ftou.S | 12 ++
tests/tcg/tricore/asm/test_hptof.S | 12 ++
tests/tcg/tricore/asm/test_insert.S | 14 ++
16 files changed, 780 insertions(+), 177 deletions(-)
create mode 100644 tests/tcg/tricore/asm/test_arith.S
create mode 100644 tests/tcg/tricore/asm/test_crcn.S
create mode 100644 tests/tcg/tricore/asm/test_ftohp.S
create mode 100644 tests/tcg/tricore/asm/test_ftou.S
create mode 100644 tests/tcg/tricore/asm/test_hptof.S
next reply other threads:[~2023-09-28 8:55 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-28 8:52 Bastian Koppelmann [this message]
2023-09-28 8:52 ` [PULL v2 01/21] tests/tcg/tricore: Bump cpu to tc37x Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 02/21] target/tricore: Implement CRCN insn Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 03/21] target/tricore: Correctly handle FPU RM from PSW Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 04/21] target/tricore: Implement FTOU insn Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 05/21] target/tricore: Clarify special case for FTOUZ insn Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 06/21] target/tricore: Implement ftohp insn Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 07/21] target/tricore: Implement hptof insn Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 08/21] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 09/21] target/tricore: Swap src and dst reg for RCRR_INSERT Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 10/21] target/tricore: Replace cpu_*_code with translator_* Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 11/21] target/tricore: Fix FTOUZ being ISA v1.3.1 up Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 12/21] tests/tcg/tricore: Extended and non-extened regs now match Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 13/21] hw/tricore: Log failing test in testdevice Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 14/21] tests/tcg: Reset result register after each test Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 15/21] tests/tcg/tricore: Add test for all arith insns up to addx Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 16/21] tests/tcg/tricore: Add test from 'and' to 'csub' Bastian Koppelmann
2023-09-28 8:52 ` [PULL v2 17/21] tests/tcg/tricore: Add test from 'dextr' to 'lt' Bastian Koppelmann
2023-09-28 8:53 ` [PULL v2 18/21] tests/tcg/tricore: Add test from 'max' to 'shas' Bastian Koppelmann
2023-09-28 8:53 ` [PULL v2 19/21] tests/tcg/tricore: Add test from 'shuffle' to 'xor.t' Bastian Koppelmann
2023-09-28 8:53 ` [PULL v2 20/21] target/tricore: Remove CSFRs from cpu.h Bastian Koppelmann
2023-09-28 8:53 ` [PULL v2 21/21] target/tricore: Change effective address (ea) to target_ulong Bastian Koppelmann
2023-09-28 14:26 ` [PULL v2 00/21] tricore queue Stefan Hajnoczi
2023-09-29 6:38 ` Bastian Koppelmann
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