* [PULL v3 01/16] tests/tcg/tricore: Bump cpu to tc37x
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 02/16] target/tricore: Implement CRCN insn Bastian Koppelmann
` (16 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Richard Henderson
we don't want to exclude ISA v1.6.2 insns from our tests.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230828112651.522058-2-kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/Makefile.softmmu-target | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index 2ec0bd3622..d556201b07 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -25,7 +25,7 @@ TESTS += test_muls.asm.tst
TESTS += test_boot_to_main.c.tst
TESTS += test_context_save_areas.c.tst
-QEMU_OPTS += -M tricore_testboard -cpu tc27x -nographic -kernel
+QEMU_OPTS += -M tricore_testboard -cpu tc37x -nographic -kernel
%.pS: $(ASM_TESTS_PATH)/%.S
$(CC) -E -o $@ $<
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 02/16] target/tricore: Implement CRCN insn
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 01/16] tests/tcg/tricore: Bump cpu to tc37x Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 03/16] target/tricore: Correctly handle FPU RM from PSW Bastian Koppelmann
` (15 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Richard Henderson
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-3-kbastian@mail.uni-paderborn.de>
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c | 63 +++++++++++++++++++++++
target/tricore/translate.c | 8 +++
target/tricore/tricore-opcodes.h | 1 +
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/asm/test_crcn.S | 9 ++++
6 files changed, 83 insertions(+)
create mode 100644 tests/tcg/tricore/asm/test_crcn.S
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 31d71eac7a..190645413a 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -134,6 +134,7 @@ DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32_be, TCG_CALL_NO_RWG_SE, i32, i32, i32)
DEF_HELPER_FLAGS_2(crc32_le, TCG_CALL_NO_RWG_SE, i32, i32, i32)
+DEF_HELPER_FLAGS_3(crcn, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
DEF_HELPER_FLAGS_2(shuffle, TCG_CALL_NO_RWG_SE, i32, i32, i32)
/* CSA */
DEF_HELPER_2(call, void, env, i32)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 89be1ed648..0cf8eb50bd 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2308,6 +2308,69 @@ uint32_t helper_crc32_le(uint32_t arg0, uint32_t arg1)
return crc32(arg1, buf, 4);
}
+static uint32_t crc_div(uint32_t crc_in, uint32_t data, uint32_t gen,
+ uint32_t n, uint32_t m)
+{
+ uint32_t i;
+
+ data = data << n;
+ for (i = 0; i < m; i++) {
+ if (crc_in & (1u << (n - 1))) {
+ crc_in <<= 1;
+ if (data & (1u << (m - 1))) {
+ crc_in++;
+ }
+ crc_in ^= gen;
+ } else {
+ crc_in <<= 1;
+ if (data & (1u << (m - 1))) {
+ crc_in++;
+ }
+ }
+ data <<= 1;
+ }
+
+ return crc_in;
+}
+
+uint32_t helper_crcn(uint32_t arg0, uint32_t arg1, uint32_t arg2)
+{
+ uint32_t crc_out, crc_in;
+ uint32_t n = extract32(arg0, 12, 4) + 1;
+ uint32_t gen = extract32(arg0, 16, n);
+ uint32_t inv = extract32(arg0, 9, 1);
+ uint32_t le = extract32(arg0, 8, 1);
+ uint32_t m = extract32(arg0, 0, 3) + 1;
+ uint32_t data = extract32(arg1, 0, m);
+ uint32_t seed = extract32(arg2, 0, n);
+
+ if (le == 1) {
+ if (m == 0) {
+ data = 0;
+ } else {
+ data = revbit32(data) >> (32 - m);
+ }
+ }
+
+ if (inv == 1) {
+ seed = ~seed;
+ }
+
+ if (m > n) {
+ crc_in = (data >> (m - n)) ^ seed;
+ } else {
+ crc_in = (data << (n - m)) ^ seed;
+ }
+
+ crc_out = crc_div(crc_in, data, gen, n, m);
+
+ if (inv) {
+ crc_out = ~crc_out;
+ }
+
+ return extract32(crc_out, 0, n);
+}
+
uint32_t helper_shuffle(uint32_t arg0, uint32_t arg1)
{
uint32_t resb;
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 6ae5ccbf72..4e7e18f985 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6669,6 +6669,14 @@ static void decode_rrr_divide(DisasContext *ctx)
gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
+ case OPC2_32_RRR_CRCN:
+ if (has_feature(ctx, TRICORE_FEATURE_162)) {
+ gen_helper_crcn(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2],
+ cpu_gpr_d[r3]);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
case OPC2_32_RRR_ADD_F:
gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
break;
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index bc62b73173..f070571665 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1247,6 +1247,7 @@ enum {
OPC2_32_RRR_SUB_F = 0x03,
OPC2_32_RRR_MADD_F = 0x06,
OPC2_32_RRR_MSUB_F = 0x07,
+ OPC2_32_RRR_CRCN = 0x01, /* 1.6.2 up */
};
/*
* RRR1 Format
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index d556201b07..b8d9b33933 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -9,6 +9,7 @@ CFLAGS = -mtc162 -c -I$(TESTS_PATH)
TESTS += test_abs.asm.tst
TESTS += test_bmerge.asm.tst
TESTS += test_clz.asm.tst
+TESTS += test_crcn.asm.tst
TESTS += test_dextr.asm.tst
TESTS += test_dvstep.asm.tst
TESTS += test_fadd.asm.tst
diff --git a/tests/tcg/tricore/asm/test_crcn.S b/tests/tcg/tricore/asm/test_crcn.S
new file mode 100644
index 0000000000..51a22722a3
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_crcn.S
@@ -0,0 +1,9 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+# insn num result rs1 rs2 rs3
+# | | | | | |
+ TEST_D_DDD(crcn, 1, 0x00002bed, 0x0, 0xa10ddeed, 0x0)
+
+ TEST_PASSFAIL
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 03/16] target/tricore: Correctly handle FPU RM from PSW
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 01/16] tests/tcg/tricore: Bump cpu to tc37x Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 02/16] target/tricore: Implement CRCN insn Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 04/16] target/tricore: Implement FTOU insn Bastian Koppelmann
` (14 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Richard Henderson
when we reconstructed PSW using psw_read(), we were trying to clear the
cached USB bits out of env->PSW. The mask was wrong and we would clear
PSW.RM as well.
when we write the PSW using psw_write() we update the rounding modes in
env->fp_status for softfloat. The order of bits used by TriCore is not
the one used by softfloat.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-4-kbastian@mail.uni-paderborn.de>
---
target/tricore/helper.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 6d076ac36f..e615c3d6d4 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -120,7 +120,21 @@ void tricore_cpu_list(void)
void fpu_set_state(CPUTriCoreState *env)
{
- set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status);
+ switch (extract32(env->PSW, 24, 2)) {
+ case 0:
+ set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
+ break;
+ case 1:
+ set_float_rounding_mode(float_round_up, &env->fp_status);
+ break;
+ case 2:
+ set_float_rounding_mode(float_round_down, &env->fp_status);
+ break;
+ case 3:
+ set_float_rounding_mode(float_round_to_zero, &env->fp_status);
+ break;
+ }
+
set_flush_inputs_to_zero(1, &env->fp_status);
set_flush_to_zero(1, &env->fp_status);
set_default_nan_mode(1, &env->fp_status);
@@ -129,7 +143,7 @@ void fpu_set_state(CPUTriCoreState *env)
uint32_t psw_read(CPUTriCoreState *env)
{
/* clear all USB bits */
- env->PSW &= 0x6ffffff;
+ env->PSW &= 0x7ffffff;
/* now set them from the cache */
env->PSW |= ((env->PSW_USB_C != 0) << 31);
env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1);
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 04/16] target/tricore: Implement FTOU insn
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (2 preceding siblings ...)
2023-09-29 6:39 ` [PULL v3 03/16] target/tricore: Correctly handle FPU RM from PSW Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 05/16] target/tricore: Clarify special case for FTOUZ insn Bastian Koppelmann
` (13 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Richard Henderson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-5-kbastian@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 32 +++++++++++++++++++++++
target/tricore/helper.h | 1 +
target/tricore/translate.c | 3 +++
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/asm/test_ftou.S | 12 +++++++++
5 files changed, 49 insertions(+)
create mode 100644 tests/tcg/tricore/asm/test_ftou.S
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index cb7ee7dd35..3aefeb776e 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -429,6 +429,38 @@ uint32_t helper_ftoiz(CPUTriCoreState *env, uint32_t arg)
return result;
}
+uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg)
+{
+ float32 f_arg = make_float32(arg);
+ uint32_t result;
+ int32_t flags = 0;
+
+ result = float32_to_uint32(f_arg, &env->fp_status);
+
+ flags = f_get_excp_flags(env);
+ if (flags & float_flag_invalid) {
+ flags &= ~float_flag_inexact;
+ if (float32_is_any_nan(f_arg)) {
+ result = 0;
+ }
+ /*
+ * we need to check arg < 0.0 before rounding as TriCore needs to raise
+ * float_flag_invalid as well. For instance, when we have a negative
+ * exponent and sign, softfloat would only raise float_flat_inexact.
+ */
+ } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
+ flags = float_flag_invalid;
+ result = 0;
+ }
+
+ if (flags) {
+ f_update_psw_flags(env, flags);
+ } else {
+ env->FPU_FS = 0;
+ }
+ return result;
+}
+
uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
{
float32 f_arg = make_float32(arg);
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 190645413a..827fbaa692 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -114,6 +114,7 @@ DEF_HELPER_2(ftoi, i32, env, i32)
DEF_HELPER_2(itof, i32, env, i32)
DEF_HELPER_2(utof, i32, env, i32)
DEF_HELPER_2(ftoiz, i32, env, i32)
+DEF_HELPER_2(ftou, i32, env, i32)
DEF_HELPER_2(ftouz, i32, env, i32)
DEF_HELPER_2(updfl, void, env, i32)
/* dvinit */
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 4e7e18f985..382ecf4775 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6269,6 +6269,9 @@ static void decode_rr_divide(DisasContext *ctx)
case OPC2_32_RR_ITOF:
gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
break;
+ case OPC2_32_RR_FTOU:
+ gen_helper_ftou(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ break;
case OPC2_32_RR_FTOUZ:
gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
break;
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index b8d9b33933..91ae129a83 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -15,6 +15,7 @@ TESTS += test_dvstep.asm.tst
TESTS += test_fadd.asm.tst
TESTS += test_fmul.asm.tst
TESTS += test_ftoi.asm.tst
+TESTS += test_ftou.asm.tst
TESTS += test_imask.asm.tst
TESTS += test_insert.asm.tst
TESTS += test_ld_bu.asm.tst
diff --git a/tests/tcg/tricore/asm/test_ftou.S b/tests/tcg/tricore/asm/test_ftou.S
new file mode 100644
index 0000000000..10f106ad62
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_ftou.S
@@ -0,0 +1,12 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+ TEST_D_D(ftou, 1, 0x00000000, 0x1733f6c2)
+ TEST_D_D(ftou, 2, 0x00000000, 0x2c9d9cdc)
+ TEST_D_D(ftou, 3, 0xffffffff, 0x56eb7395)
+ TEST_D_D(ftou, 4, 0x79900800, 0x4ef32010)
+ TEST_D_D(ftou, 5, 0x0353f510, 0x4c54fd44)
+
+ TEST_PASSFAIL
+
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 05/16] target/tricore: Clarify special case for FTOUZ insn
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (3 preceding siblings ...)
2023-09-29 6:39 ` [PULL v3 04/16] target/tricore: Implement FTOU insn Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 06/16] target/tricore: Implement ftohp insn Bastian Koppelmann
` (12 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Richard Henderson
this is not something other ISAs do, so clarify it with a comment.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-6-kbastian@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index 3aefeb776e..d0c474c5f3 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -475,6 +475,11 @@ uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
if (float32_is_any_nan(f_arg)) {
result = 0;
}
+ /*
+ * we need to check arg < 0.0 before rounding as TriCore needs to raise
+ * float_flag_invalid as well. For instance, when we have a negative
+ * exponent and sign, softfloat would only raise float_flat_inexact.
+ */
} else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
flags = float_flag_invalid;
result = 0;
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 06/16] target/tricore: Implement ftohp insn
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (4 preceding siblings ...)
2023-09-29 6:39 ` [PULL v3 05/16] target/tricore: Clarify special case for FTOUZ insn Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 07/16] target/tricore: Implement hptof insn Bastian Koppelmann
` (11 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Richard Henderson
reported in https://gitlab.com/qemu-project/qemu/-/issues/1667
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-7-kbastian@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 38 +++++++++++++++++++++++
target/tricore/helper.c | 1 +
target/tricore/helper.h | 1 +
target/tricore/translate.c | 7 +++++
target/tricore/tricore-opcodes.h | 1 +
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/asm/test_ftohp.S | 14 +++++++++
7 files changed, 63 insertions(+)
create mode 100644 tests/tcg/tricore/asm/test_ftohp.S
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index d0c474c5f3..848c4a40a0 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -373,6 +373,44 @@ uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
return (uint32_t)result;
}
+uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
+{
+ float32 f_arg = make_float32(arg);
+ uint32_t result = 0;
+ int32_t flags = 0;
+
+ /*
+ * if we have any NAN we need to move the top 2 and lower 8 input mantissa
+ * bits to the top 2 and lower 8 output mantissa bits respectively.
+ * Softfloat on the other hand uses the top 10 mantissa bits.
+ */
+ if (float32_is_any_nan(f_arg)) {
+ if (float32_is_signaling_nan(f_arg, &env->fp_status)) {
+ flags |= float_flag_invalid;
+ }
+ result = float16_set_sign(result, arg >> 31);
+ result = deposit32(result, 10, 5, 0x1f);
+ result = deposit32(result, 8, 2, extract32(arg, 21, 2));
+ result = deposit32(result, 0, 8, extract32(arg, 0, 8));
+ if (extract32(result, 0, 10) == 0) {
+ result |= (1 << 8);
+ }
+ } else {
+ set_flush_to_zero(0, &env->fp_status);
+ result = float32_to_float16(f_arg, true, &env->fp_status);
+ set_flush_to_zero(1, &env->fp_status);
+ flags = f_get_excp_flags(env);
+ }
+
+ if (flags) {
+ f_update_psw_flags(env, flags);
+ } else {
+ env->FPU_FS = 0;
+ }
+
+ return result;
+}
+
uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
{
float32 f_result;
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index e615c3d6d4..7e5da3cb23 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -137,6 +137,7 @@ void fpu_set_state(CPUTriCoreState *env)
set_flush_inputs_to_zero(1, &env->fp_status);
set_flush_to_zero(1, &env->fp_status);
+ set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
set_default_nan_mode(1, &env->fp_status);
}
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 827fbaa692..dcc5a492b3 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -111,6 +111,7 @@ DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)
DEF_HELPER_3(fcmp, i32, env, i32, i32)
DEF_HELPER_2(qseed, i32, env, i32)
DEF_HELPER_2(ftoi, i32, env, i32)
+DEF_HELPER_2(ftohp, i32, env, i32)
DEF_HELPER_2(itof, i32, env, i32)
DEF_HELPER_2(utof, i32, env, i32)
DEF_HELPER_2(ftoiz, i32, env, i32)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 382ecf4775..d76b6475f1 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6260,6 +6260,13 @@ static void decode_rr_divide(DisasContext *ctx)
case OPC2_32_RR_DIV_F:
gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
+ case OPC2_32_RR_FTOHP:
+ if (has_feature(ctx, TRICORE_FEATURE_162)) {
+ gen_helper_ftohp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
case OPC2_32_RR_CMP_F:
gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index f070571665..29e655a667 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1152,6 +1152,7 @@ enum {
OPC2_32_RR_ITOF = 0x14,
OPC2_32_RR_CMP_F = 0x00,
OPC2_32_RR_FTOIZ = 0x13,
+ OPC2_32_RR_FTOHP = 0x25, /* 1.6.2 only */
OPC2_32_RR_FTOQ31 = 0x11,
OPC2_32_RR_FTOQ31Z = 0x18,
OPC2_32_RR_FTOU = 0x12,
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index 91ae129a83..fc545d45ae 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -14,6 +14,7 @@ TESTS += test_dextr.asm.tst
TESTS += test_dvstep.asm.tst
TESTS += test_fadd.asm.tst
TESTS += test_fmul.asm.tst
+TESTS += test_ftohp.asm.tst
TESTS += test_ftoi.asm.tst
TESTS += test_ftou.asm.tst
TESTS += test_imask.asm.tst
diff --git a/tests/tcg/tricore/asm/test_ftohp.S b/tests/tcg/tricore/asm/test_ftohp.S
new file mode 100644
index 0000000000..9e23141c1e
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_ftohp.S
@@ -0,0 +1,14 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+ TEST_D_D(ftohp, 1, 0xffff, 0xffffffff)
+ TEST_D_D(ftohp, 2, 0xfc00, 0xff800000)
+ TEST_D_D(ftohp, 3, 0x7c00, 0x7f800000)
+ TEST_D_D(ftohp, 4, 0x0, 0x0)
+ TEST_D_D(ftohp, 5, 0x5, 0x34a43580)
+
+ #TEST_D_D_PSW(ftohp, 6, 0x400, 0x8c000b80, 0x387fee74)
+
+ TEST_PASSFAIL
+
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 07/16] target/tricore: Implement hptof insn
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (5 preceding siblings ...)
2023-09-29 6:39 ` [PULL v3 06/16] target/tricore: Implement ftohp insn Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 08/16] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 Bastian Koppelmann
` (10 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Richard Henderson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-8-kbastian@mail.uni-paderborn.de>
---
target/tricore/fpu_helper.c | 36 +++++++++++++++++++++++
target/tricore/helper.h | 1 +
target/tricore/translate.c | 7 +++++
target/tricore/tricore-opcodes.h | 1 +
tests/tcg/tricore/Makefile.softmmu-target | 1 +
tests/tcg/tricore/asm/test_hptof.S | 12 ++++++++
6 files changed, 58 insertions(+)
create mode 100644 tests/tcg/tricore/asm/test_hptof.S
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index 848c4a40a0..5d38aea143 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -373,6 +373,42 @@ uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
return (uint32_t)result;
}
+uint32_t helper_hptof(CPUTriCoreState *env, uint32_t arg)
+{
+ float16 f_arg = make_float16(arg);
+ uint32_t result = 0;
+ int32_t flags = 0;
+
+ /*
+ * if we have any NAN we need to move the top 2 and lower 8 input mantissa
+ * bits to the top 2 and lower 8 output mantissa bits respectively.
+ * Softfloat on the other hand uses the top 10 mantissa bits.
+ */
+ if (float16_is_any_nan(f_arg)) {
+ if (float16_is_signaling_nan(f_arg, &env->fp_status)) {
+ flags |= float_flag_invalid;
+ }
+ result = 0;
+ result = float32_set_sign(result, f_arg >> 15);
+ result = deposit32(result, 23, 8, 0xff);
+ result = deposit32(result, 21, 2, extract32(f_arg, 8, 2));
+ result = deposit32(result, 0, 8, extract32(f_arg, 0, 8));
+ } else {
+ set_flush_inputs_to_zero(0, &env->fp_status);
+ result = float16_to_float32(f_arg, true, &env->fp_status);
+ set_flush_inputs_to_zero(1, &env->fp_status);
+ flags = f_get_excp_flags(env);
+ }
+
+ if (flags) {
+ f_update_psw_flags(env, flags);
+ } else {
+ env->FPU_FS = 0;
+ }
+
+ return result;
+}
+
uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
{
float32 f_arg = make_float32(arg);
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index dcc5a492b3..1d97d078b0 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -112,6 +112,7 @@ DEF_HELPER_3(fcmp, i32, env, i32, i32)
DEF_HELPER_2(qseed, i32, env, i32)
DEF_HELPER_2(ftoi, i32, env, i32)
DEF_HELPER_2(ftohp, i32, env, i32)
+DEF_HELPER_2(hptof, i32, env, i32)
DEF_HELPER_2(itof, i32, env, i32)
DEF_HELPER_2(utof, i32, env, i32)
DEF_HELPER_2(ftoiz, i32, env, i32)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index d76b6475f1..c9823ee32a 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6267,6 +6267,13 @@ static void decode_rr_divide(DisasContext *ctx)
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
+ case OPC2_32_RR_HPTOF:
+ if (has_feature(ctx, TRICORE_FEATURE_162)) {
+ gen_helper_hptof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
case OPC2_32_RR_CMP_F:
gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index 29e655a667..60d2402b6e 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1153,6 +1153,7 @@ enum {
OPC2_32_RR_CMP_F = 0x00,
OPC2_32_RR_FTOIZ = 0x13,
OPC2_32_RR_FTOHP = 0x25, /* 1.6.2 only */
+ OPC2_32_RR_HPTOF = 0x24, /* 1.6.2 only */
OPC2_32_RR_FTOQ31 = 0x11,
OPC2_32_RR_FTOQ31Z = 0x18,
OPC2_32_RR_FTOU = 0x12,
diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-target
index fc545d45ae..258aeb40ae 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -17,6 +17,7 @@ TESTS += test_fmul.asm.tst
TESTS += test_ftohp.asm.tst
TESTS += test_ftoi.asm.tst
TESTS += test_ftou.asm.tst
+TESTS += test_hptof.asm.tst
TESTS += test_imask.asm.tst
TESTS += test_insert.asm.tst
TESTS += test_ld_bu.asm.tst
diff --git a/tests/tcg/tricore/asm/test_hptof.S b/tests/tcg/tricore/asm/test_hptof.S
new file mode 100644
index 0000000000..8adc5e5273
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_hptof.S
@@ -0,0 +1,12 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+ TEST_D_D(hptof, 1, 0xba190000, 0xcc0e90c8)
+ TEST_D_D(hptof, 2, 0x3eaea000, 0x8be23575)
+ TEST_D_D(hptof, 3, 0xc33b8000, 0xcc48d9dc)
+ TEST_D_D(hptof, 4, 0x43e2a000, 0xaef95f15)
+ TEST_D_D(hptof, 5, 0x3d55e000, 0x04932aaf)
+
+ TEST_PASSFAIL
+
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 08/16] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (6 preceding siblings ...)
2023-09-29 6:39 ` [PULL v3 07/16] target/tricore: Implement hptof insn Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 09/16] target/tricore: Swap src and dst reg for RCRR_INSERT Bastian Koppelmann
` (9 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Philippe Mathieu-Daudé, Richard Henderson
we would crash if width was 0 for these insns, as tcg_gen_deposit() is
undefined for that case. For TriCore, width = 0 is a mov from the src reg
to the dst reg, so we special case this here.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-9-kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 10 ++++++++--
tests/tcg/tricore/asm/macros.h | 15 +++++++++++++++
tests/tcg/tricore/asm/test_insert.S | 9 +++++++++
3 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index c9823ee32a..3f950ae33b 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -5310,8 +5310,11 @@ static void decode_rcpw_insert(DisasContext *ctx)
}
break;
case OPC2_32_RCPW_INSERT:
+ /* tcg_gen_deposit_tl() does not handle the case of width = 0 */
+ if (width == 0) {
+ tcg_gen_mov_tl(cpu_gpr_d[r2], cpu_gpr_d[r1]);
/* if pos + width > 32 undefined result */
- if (pos + width <= 32) {
+ } else if (pos + width <= 32) {
temp = tcg_constant_i32(const4);
tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
}
@@ -6571,7 +6574,10 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
break;
case OPC2_32_RRPW_INSERT:
- if (pos + width <= 32) {
+ /* tcg_gen_deposit_tl() does not handle the case of width = 0 */
+ if (width == 0) {
+ tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ } else if (pos + width <= 32) {
tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos, width);
}
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index b5087b5c97..51f6191ef2 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -161,6 +161,21 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \
)
+#define TEST_D_DDII(insn, num, result, rs1, rs2, imm1, imm2) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2; \
+ )
+
+#define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, imm1, imm2, imm3; \
+ )
+
#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
TEST_CASE_E(num, res_lo, res_hi, \
LI(EREG_RS1_LO, rs1_lo); \
diff --git a/tests/tcg/tricore/asm/test_insert.S b/tests/tcg/tricore/asm/test_insert.S
index d5fd2237e1..3978810121 100644
--- a/tests/tcg/tricore/asm/test_insert.S
+++ b/tests/tcg/tricore/asm/test_insert.S
@@ -6,4 +6,13 @@ _start:
# | | | | | | |
TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8)
+# insn num result rs1 imm1 imm2 imm3
+# | | | | | | |
+ TEST_D_DIII(insert, 2, 0xd38fe370, 0xd38fe370, 0x4, 0x4 , 0x0)
+ TEST_D_DIII(insert, 3, 0xd38fe374, 0xd38fe370, 0x4, 0x0 , 0x4)
+
+# insn num result rs1 rs2 pos width
+# | | | | | | |
+ TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
+
TEST_PASSFAIL
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 09/16] target/tricore: Swap src and dst reg for RCRR_INSERT
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (7 preceding siblings ...)
2023-09-29 6:39 ` [PULL v3 08/16] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 10/16] target/tricore: Replace cpu_*_code with translator_* Bastian Koppelmann
` (8 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Richard Henderson
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-10-kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 8 ++++----
tests/tcg/tricore/asm/macros.h | 9 +++++++++
tests/tcg/tricore/asm/test_insert.S | 5 +++++
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 3f950ae33b..7aba7b067c 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8223,12 +8223,12 @@ static void decode_32Bit_opc(DisasContext *ctx)
temp2 = tcg_temp_new(); /* width*/
temp3 = tcg_temp_new(); /* pos */
- CHECK_REG_PAIR(r3);
+ CHECK_REG_PAIR(r2);
- tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
- tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
+ tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f);
+ tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f);
- gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
+ gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3);
break;
/* RCRW Format */
case OPCM_32_RCRW_MASK_INSERT:
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 51f6191ef2..17e696bef5 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -169,6 +169,15 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2; \
)
+#define TEST_D_DIE(insn, num, result, rs1, imm1, rs2_lo, rs2_hi)\
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(EREG_RS2_LO, rs2_lo); \
+ LI(EREG_RS2_HI, rs2_hi); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, imm1, EREG_RS2; \
+ )
+
#define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
TEST_CASE(num, DREG_CALC_RESULT, result, \
LI(DREG_RS1, rs1); \
diff --git a/tests/tcg/tricore/asm/test_insert.S b/tests/tcg/tricore/asm/test_insert.S
index 3978810121..223d7ce796 100644
--- a/tests/tcg/tricore/asm/test_insert.S
+++ b/tests/tcg/tricore/asm/test_insert.S
@@ -15,4 +15,9 @@ _start:
# | | | | | | |
TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
+# insn num result rs1 imm1 rs2_h rs2_l
+# | | | | | | |
+ TEST_D_DIE(insert, 5, 0xe30c308d, 0xe30c308d ,0x3 , 0x00000000 ,0x00000000)
+ TEST_D_DIE(insert, 6, 0x669b0120, 0x669b2820 ,0x2 , 0x5530a1c7 ,0x3a2b0f67)
+
TEST_PASSFAIL
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 10/16] target/tricore: Replace cpu_*_code with translator_*
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (8 preceding siblings ...)
2023-09-29 6:39 ` [PULL v3 09/16] target/tricore: Swap src and dst reg for RCRR_INSERT Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 11/16] target/tricore: Fix FTOUZ being ISA v1.3.1 up Bastian Koppelmann
` (7 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Richard Henderson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-11-kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 7aba7b067c..2107d1fdd4 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8398,7 +8398,7 @@ static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx)
* 4 bytes from the page boundary, so we cross the page if the first
* 16 bits indicate that this is a 32 bit insn.
*/
- uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next);
+ uint16_t insn = translator_lduw(env, &ctx->base, ctx->base.pc_next);
return !tricore_insn_is_16bit(insn);
}
@@ -8411,14 +8411,15 @@ static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
uint16_t insn_lo;
bool is_16bit;
- insn_lo = cpu_lduw_code(env, ctx->base.pc_next);
+ insn_lo = translator_lduw(env, &ctx->base, ctx->base.pc_next);
is_16bit = tricore_insn_is_16bit(insn_lo);
if (is_16bit) {
ctx->opcode = insn_lo;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
decode_16Bit_opc(ctx);
} else {
- uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2);
+ uint32_t insn_hi = translator_lduw(env, &ctx->base,
+ ctx->base.pc_next + 2);
ctx->opcode = insn_hi << 16 | insn_lo;
ctx->pc_succ_insn = ctx->base.pc_next + 4;
decode_32Bit_opc(ctx);
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 11/16] target/tricore: Fix FTOUZ being ISA v1.3.1 up
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (9 preceding siblings ...)
2023-09-29 6:39 ` [PULL v3 10/16] target/tricore: Replace cpu_*_code with translator_* Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 12/16] tests/tcg/tricore: Extended and non-extened regs now match Bastian Koppelmann
` (6 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Richard Henderson
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-12-kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 2107d1fdd4..7b53307eff 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6290,7 +6290,11 @@ static void decode_rr_divide(DisasContext *ctx)
gen_helper_ftou(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
break;
case OPC2_32_RR_FTOUZ:
- gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ if (has_feature(ctx, TRICORE_FEATURE_131)) {
+ gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
break;
case OPC2_32_RR_UPDFL:
gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 12/16] tests/tcg/tricore: Extended and non-extened regs now match
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (10 preceding siblings ...)
2023-09-29 6:39 ` [PULL v3 11/16] target/tricore: Fix FTOUZ being ISA v1.3.1 up Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 13/16] hw/tricore: Log failing test in testdevice Bastian Koppelmann
` (5 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
RSx for d regs and e regs now use the same numbering. This makes sure
that mixing d and e registers in an insn test will not overwrite data
between registers.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-2-kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 38 +++++++++++++++++-----------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 17e696bef5..0f349dbf1e 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -12,31 +12,31 @@
#define TESTDEV_ADDR 0xf0000000
/* Register definitions */
#define DREG_RS1 %d0
-#define DREG_RS2 %d1
-#define DREG_RS3 %d2
-#define DREG_CALC_RESULT %d3
-#define DREG_CALC_PSW %d4
-#define DREG_CORRECT_PSW %d5
-#define DREG_TEMP_LI %d10
-#define DREG_TEMP %d11
-#define DREG_TEST_NUM %d14
-#define DREG_CORRECT_RESULT %d15
-#define DREG_CORRECT_RESULT_2 %d13
+#define DREG_RS2 %d2
+#define DREG_RS3 %d4
+#define DREG_CALC_RESULT %d5
+#define DREG_CALC_PSW %d6
+#define DREG_CORRECT_PSW %d7
+#define DREG_TEMP_LI %d13
+#define DREG_TEMP %d14
+#define DREG_TEST_NUM %d8
+#define DREG_CORRECT_RESULT %d9
+#define DREG_CORRECT_RESULT_2 %d10
#define AREG_ADDR %a0
#define AREG_CORRECT_RESULT %a3
#define DREG_DEV_ADDR %a15
-#define EREG_RS1 %e6
-#define EREG_RS1_LO %d6
-#define EREG_RS1_HI %d7
-#define EREG_RS2 %e8
-#define EREG_RS2_LO %d8
-#define EREG_RS2_HI %d9
-#define EREG_CALC_RESULT %e8
-#define EREG_CALC_RESULT_HI %d9
-#define EREG_CALC_RESULT_LO %d8
+#define EREG_RS1 %e0
+#define EREG_RS1_LO %d0
+#define EREG_RS1_HI %d1
+#define EREG_RS2 %e2
+#define EREG_RS2_LO %d2
+#define EREG_RS2_HI %d3
+#define EREG_CALC_RESULT %e6
+#define EREG_CALC_RESULT_LO %d6
+#define EREG_CALC_RESULT_HI %d7
#define EREG_CORRECT_RESULT_LO %d0
#define EREG_CORRECT_RESULT_HI %d1
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 13/16] hw/tricore: Log failing test in testdevice
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (11 preceding siblings ...)
2023-09-29 6:39 ` [PULL v3 12/16] tests/tcg/tricore: Extended and non-extened regs now match Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 14/16] tests/tcg: Reset result register after each test Bastian Koppelmann
` (4 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-3-kbastian@mail.uni-paderborn.de>
---
hw/tricore/tricore_testdevice.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/tricore/tricore_testdevice.c b/hw/tricore/tricore_testdevice.c
index a1563aa568..9028d970b0 100644
--- a/hw/tricore/tricore_testdevice.c
+++ b/hw/tricore/tricore_testdevice.c
@@ -16,6 +16,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/log.h"
#include "hw/sysbus.h"
#include "hw/qdev-properties.h"
#include "hw/tricore/tricore_testdevice.h"
@@ -23,6 +24,9 @@
static void tricore_testdevice_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
+ if (value != 0) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Test %" PRIu64 " failed!\n", value);
+ }
exit(value);
}
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 14/16] tests/tcg: Reset result register after each test
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (12 preceding siblings ...)
2023-09-29 6:39 ` [PULL v3 13/16] hw/tricore: Log failing test in testdevice Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 15/16] target/tricore: Remove CSFRs from cpu.h Bastian Koppelmann
` (3 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
some insns use the result register implicitly as an input. Thus, we
could end up with data from the previous insn spilling over.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-4-kbastian@mail.uni-paderborn.de>
---
tests/tcg/tricore/asm/macros.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 0f349dbf1e..e831f73721 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -46,7 +46,8 @@ test_ ## num: \
code; \
LI(DREG_CORRECT_RESULT, correct) \
mov DREG_TEST_NUM, num; \
- jne testreg, DREG_CORRECT_RESULT, fail \
+ jne testreg, DREG_CORRECT_RESULT, fail; \
+ mov testreg, 0
#define TEST_CASE_E(num, correct_lo, correct_hi, code...) \
test_ ## num: \
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 15/16] target/tricore: Remove CSFRs from cpu.h
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (13 preceding siblings ...)
2023-09-29 6:39 ` [PULL v3 14/16] tests/tcg: Reset result register after each test Bastian Koppelmann
@ 2023-09-29 6:39 ` Bastian Koppelmann
2023-09-29 6:40 ` [PULL v3 16/16] target/tricore: Change effective address (ea) to target_ulong Bastian Koppelmann
` (2 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:39 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
these are already defined in 'csfr.h.inc'. We don't need to duplicate
these registers.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-10-kbastian@mail.uni-paderborn.de>
---
target/tricore/cpu.h | 143 +++----------------------------------------
1 file changed, 9 insertions(+), 134 deletions(-)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 3708405be8..1cace96b01 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -30,150 +30,25 @@ typedef struct CPUArchState {
/* GPR Register */
uint32_t gpr_a[16];
uint32_t gpr_d[16];
- /* CSFR Register */
- uint32_t PCXI;
/* Frequently accessed PSW_USB bits are stored separately for efficiency.
This contains all the other bits. Use psw_{read,write} to access
the whole PSW. */
uint32_t PSW;
-
- /* PSW flag cache for faster execution
- */
+ /* PSW flag cache for faster execution */
uint32_t PSW_USB_C;
uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */
uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */
uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
- uint32_t PC;
- uint32_t SYSCON;
- uint32_t CPU_ID;
- uint32_t CORE_ID;
- uint32_t BIV;
- uint32_t BTV;
- uint32_t ISP;
- uint32_t ICR;
- uint32_t FCX;
- uint32_t LCX;
- uint32_t COMPAT;
-
- /* Mem Protection Register */
- uint32_t DPR0_0L;
- uint32_t DPR0_0U;
- uint32_t DPR0_1L;
- uint32_t DPR0_1U;
- uint32_t DPR0_2L;
- uint32_t DPR0_2U;
- uint32_t DPR0_3L;
- uint32_t DPR0_3U;
-
- uint32_t DPR1_0L;
- uint32_t DPR1_0U;
- uint32_t DPR1_1L;
- uint32_t DPR1_1U;
- uint32_t DPR1_2L;
- uint32_t DPR1_2U;
- uint32_t DPR1_3L;
- uint32_t DPR1_3U;
-
- uint32_t DPR2_0L;
- uint32_t DPR2_0U;
- uint32_t DPR2_1L;
- uint32_t DPR2_1U;
- uint32_t DPR2_2L;
- uint32_t DPR2_2U;
- uint32_t DPR2_3L;
- uint32_t DPR2_3U;
-
- uint32_t DPR3_0L;
- uint32_t DPR3_0U;
- uint32_t DPR3_1L;
- uint32_t DPR3_1U;
- uint32_t DPR3_2L;
- uint32_t DPR3_2U;
- uint32_t DPR3_3L;
- uint32_t DPR3_3U;
-
- uint32_t CPR0_0L;
- uint32_t CPR0_0U;
- uint32_t CPR0_1L;
- uint32_t CPR0_1U;
- uint32_t CPR0_2L;
- uint32_t CPR0_2U;
- uint32_t CPR0_3L;
- uint32_t CPR0_3U;
-
- uint32_t CPR1_0L;
- uint32_t CPR1_0U;
- uint32_t CPR1_1L;
- uint32_t CPR1_1U;
- uint32_t CPR1_2L;
- uint32_t CPR1_2U;
- uint32_t CPR1_3L;
- uint32_t CPR1_3U;
-
- uint32_t CPR2_0L;
- uint32_t CPR2_0U;
- uint32_t CPR2_1L;
- uint32_t CPR2_1U;
- uint32_t CPR2_2L;
- uint32_t CPR2_2U;
- uint32_t CPR2_3L;
- uint32_t CPR2_3U;
-
- uint32_t CPR3_0L;
- uint32_t CPR3_0U;
- uint32_t CPR3_1L;
- uint32_t CPR3_1U;
- uint32_t CPR3_2L;
- uint32_t CPR3_2U;
- uint32_t CPR3_3L;
- uint32_t CPR3_3U;
-
- uint32_t DPM0;
- uint32_t DPM1;
- uint32_t DPM2;
- uint32_t DPM3;
-
- uint32_t CPM0;
- uint32_t CPM1;
- uint32_t CPM2;
- uint32_t CPM3;
-
- /* Memory Management Registers */
- uint32_t MMU_CON;
- uint32_t MMU_ASI;
- uint32_t MMU_TVA;
- uint32_t MMU_TPA;
- uint32_t MMU_TPX;
- uint32_t MMU_TFA;
- /* {1.3.1 only */
- uint32_t BMACON;
- uint32_t SMACON;
- uint32_t DIEAR;
- uint32_t DIETR;
- uint32_t CCDIER;
- uint32_t MIECON;
- uint32_t PIEAR;
- uint32_t PIETR;
- uint32_t CCPIER;
- /*} */
- /* Debug Registers */
- uint32_t DBGSR;
- uint32_t EXEVT;
- uint32_t CREVT;
- uint32_t SWEVT;
- uint32_t TR0EVT;
- uint32_t TR1EVT;
- uint32_t DMS;
- uint32_t DCX;
- uint32_t DBGTCR;
- uint32_t CCTRL;
- uint32_t CCNT;
- uint32_t ICNT;
- uint32_t M1CNT;
- uint32_t M2CNT;
- uint32_t M3CNT;
+#define R(ADDR, NAME, FEATURE) uint32_t NAME;
+#define A(ADDR, NAME, FEATURE) uint32_t NAME;
+#define E(ADDR, NAME, FEATURE) uint32_t NAME;
+#include "csfr.h.inc"
+#undef R
+#undef A
+#undef E
+
/* Floating Point Registers */
float_status fp_status;
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL v3 16/16] target/tricore: Change effective address (ea) to target_ulong
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (14 preceding siblings ...)
2023-09-29 6:39 ` [PULL v3 15/16] target/tricore: Remove CSFRs from cpu.h Bastian Koppelmann
@ 2023-09-29 6:40 ` Bastian Koppelmann
2023-10-02 21:56 ` [PULL v3 00/16] tricore queue Stefan Hajnoczi
2023-10-02 23:06 ` Michael Tokarev
17 siblings, 0 replies; 19+ messages in thread
From: Bastian Koppelmann @ 2023-09-29 6:40 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian
as this is an effective address and those cannot be signed,
it should not be a signed integer.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230913105326.40832-11-kbastian@mail.uni-paderborn.de>
---
target/tricore/op_helper.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 0cf8eb50bd..ba9c4444b3 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2458,7 +2458,7 @@ static bool cdc_zero(target_ulong *psw)
return count == 0;
}
-static void save_context_upper(CPUTriCoreState *env, int ea)
+static void save_context_upper(CPUTriCoreState *env, target_ulong ea)
{
cpu_stl_data(env, ea, env->PCXI);
cpu_stl_data(env, ea+4, psw_read(env));
@@ -2478,7 +2478,7 @@ static void save_context_upper(CPUTriCoreState *env, int ea)
cpu_stl_data(env, ea+60, env->gpr_d[15]);
}
-static void save_context_lower(CPUTriCoreState *env, int ea)
+static void save_context_lower(CPUTriCoreState *env, target_ulong ea)
{
cpu_stl_data(env, ea, env->PCXI);
cpu_stl_data(env, ea+4, env->gpr_a[11]);
@@ -2498,7 +2498,7 @@ static void save_context_lower(CPUTriCoreState *env, int ea)
cpu_stl_data(env, ea+60, env->gpr_d[7]);
}
-static void restore_context_upper(CPUTriCoreState *env, int ea,
+static void restore_context_upper(CPUTriCoreState *env, target_ulong ea,
target_ulong *new_PCXI, target_ulong *new_PSW)
{
*new_PCXI = cpu_ldl_data(env, ea);
@@ -2519,7 +2519,7 @@ static void restore_context_upper(CPUTriCoreState *env, int ea,
env->gpr_d[15] = cpu_ldl_data(env, ea+60);
}
-static void restore_context_lower(CPUTriCoreState *env, int ea,
+static void restore_context_lower(CPUTriCoreState *env, target_ulong ea,
target_ulong *ra, target_ulong *pcxi)
{
*pcxi = cpu_ldl_data(env, ea);
@@ -2763,26 +2763,26 @@ void helper_rfm(CPUTriCoreState *env)
}
}
-void helper_ldlcx(CPUTriCoreState *env, uint32_t ea)
+void helper_ldlcx(CPUTriCoreState *env, target_ulong ea)
{
uint32_t dummy;
/* insn doesn't load PCXI and RA */
restore_context_lower(env, ea, &dummy, &dummy);
}
-void helper_lducx(CPUTriCoreState *env, uint32_t ea)
+void helper_lducx(CPUTriCoreState *env, target_ulong ea)
{
uint32_t dummy;
/* insn doesn't load PCXI and PSW */
restore_context_upper(env, ea, &dummy, &dummy);
}
-void helper_stlcx(CPUTriCoreState *env, uint32_t ea)
+void helper_stlcx(CPUTriCoreState *env, target_ulong ea)
{
save_context_lower(env, ea);
}
-void helper_stucx(CPUTriCoreState *env, uint32_t ea)
+void helper_stucx(CPUTriCoreState *env, target_ulong ea)
{
save_context_upper(env, ea);
}
--
2.42.0
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PULL v3 00/16] tricore queue
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (15 preceding siblings ...)
2023-09-29 6:40 ` [PULL v3 16/16] target/tricore: Change effective address (ea) to target_ulong Bastian Koppelmann
@ 2023-10-02 21:56 ` Stefan Hajnoczi
2023-10-02 23:06 ` Michael Tokarev
17 siblings, 0 replies; 19+ messages in thread
From: Stefan Hajnoczi @ 2023-10-02 21:56 UTC (permalink / raw)
To: Bastian Koppelmann; +Cc: qemu-devel, kbastian
[-- Attachment #1: Type: text/plain, Size: 115 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PULL v3 00/16] tricore queue
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
` (16 preceding siblings ...)
2023-10-02 21:56 ` [PULL v3 00/16] tricore queue Stefan Hajnoczi
@ 2023-10-02 23:06 ` Michael Tokarev
17 siblings, 0 replies; 19+ messages in thread
From: Michael Tokarev @ 2023-10-02 23:06 UTC (permalink / raw)
To: Bastian Koppelmann, qemu-devel
29.09.2023 09:39, Bastian Koppelmann:
> ----------------------------------------------------------------
> - Add FTOU, CRCN, FTOHP, and HPTOF insns
>
> ----------------------------------------------------------------
> Changes from v2:
> - Replaced %ld with PRIu64 for patch 13
> - Dropped patches 15 - 19, as they require an updated patch series
> ----------------------------------------------------------------
>
> Bastian Koppelmann (16):
> tests/tcg/tricore: Bump cpu to tc37x
> target/tricore: Implement CRCN insn
> target/tricore: Correctly handle FPU RM from PSW
> target/tricore: Implement FTOU insn
> target/tricore: Clarify special case for FTOUZ insn
> target/tricore: Implement ftohp insn
> target/tricore: Implement hptof insn
> target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
> target/tricore: Swap src and dst reg for RCRR_INSERT
> target/tricore: Replace cpu_*_code with translator_*
> target/tricore: Fix FTOUZ being ISA v1.3.1 up
> tests/tcg/tricore: Extended and non-extened regs now match
> hw/tricore: Log failing test in testdevice
> tests/tcg: Reset result register after each test
> target/tricore: Remove CSFRs from cpu.h
> target/tricore: Change effective address (ea) to target_ulong
Is there anything here to apply to -stable, or there's no reason to bother?
"Fix RCPW/RRPW_INSERT insns for width = 0" might be a candidate, maybe others..
Thanks,
/mjt
^ permalink raw reply [flat|nested] 19+ messages in thread