From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: kbastian@mail.uni-paderborn.de,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [PULL v3 08/16] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
Date: Fri, 29 Sep 2023 08:39:52 +0200 [thread overview]
Message-ID: <20230929064000.536923-9-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20230929064000.536923-1-kbastian@mail.uni-paderborn.de>
we would crash if width was 0 for these insns, as tcg_gen_deposit() is
undefined for that case. For TriCore, width = 0 is a mov from the src reg
to the dst reg, so we special case this here.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-9-kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 10 ++++++++--
tests/tcg/tricore/asm/macros.h | 15 +++++++++++++++
tests/tcg/tricore/asm/test_insert.S | 9 +++++++++
3 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index c9823ee32a..3f950ae33b 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -5310,8 +5310,11 @@ static void decode_rcpw_insert(DisasContext *ctx)
}
break;
case OPC2_32_RCPW_INSERT:
+ /* tcg_gen_deposit_tl() does not handle the case of width = 0 */
+ if (width == 0) {
+ tcg_gen_mov_tl(cpu_gpr_d[r2], cpu_gpr_d[r1]);
/* if pos + width > 32 undefined result */
- if (pos + width <= 32) {
+ } else if (pos + width <= 32) {
temp = tcg_constant_i32(const4);
tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
}
@@ -6571,7 +6574,10 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
break;
case OPC2_32_RRPW_INSERT:
- if (pos + width <= 32) {
+ /* tcg_gen_deposit_tl() does not handle the case of width = 0 */
+ if (width == 0) {
+ tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+ } else if (pos + width <= 32) {
tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos, width);
}
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index b5087b5c97..51f6191ef2 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -161,6 +161,21 @@ test_ ## num: \
insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \
)
+#define TEST_D_DDII(insn, num, result, rs1, rs2, imm1, imm2) \
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ LI(DREG_RS2, rs2); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2; \
+ )
+
+#define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
+ TEST_CASE(num, DREG_CALC_RESULT, result, \
+ LI(DREG_RS1, rs1); \
+ rstv; \
+ insn DREG_CALC_RESULT, DREG_RS1, imm1, imm2, imm3; \
+ )
+
#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
TEST_CASE_E(num, res_lo, res_hi, \
LI(EREG_RS1_LO, rs1_lo); \
diff --git a/tests/tcg/tricore/asm/test_insert.S b/tests/tcg/tricore/asm/test_insert.S
index d5fd2237e1..3978810121 100644
--- a/tests/tcg/tricore/asm/test_insert.S
+++ b/tests/tcg/tricore/asm/test_insert.S
@@ -6,4 +6,13 @@ _start:
# | | | | | | |
TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8)
+# insn num result rs1 imm1 imm2 imm3
+# | | | | | | |
+ TEST_D_DIII(insert, 2, 0xd38fe370, 0xd38fe370, 0x4, 0x4 , 0x0)
+ TEST_D_DIII(insert, 3, 0xd38fe374, 0xd38fe370, 0x4, 0x0 , 0x4)
+
+# insn num result rs1 rs2 pos width
+# | | | | | | |
+ TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
+
TEST_PASSFAIL
--
2.42.0
next prev parent reply other threads:[~2023-09-29 6:41 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-29 6:39 [PULL v3 00/16] tricore queue Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 01/16] tests/tcg/tricore: Bump cpu to tc37x Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 02/16] target/tricore: Implement CRCN insn Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 03/16] target/tricore: Correctly handle FPU RM from PSW Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 04/16] target/tricore: Implement FTOU insn Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 05/16] target/tricore: Clarify special case for FTOUZ insn Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 06/16] target/tricore: Implement ftohp insn Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 07/16] target/tricore: Implement hptof insn Bastian Koppelmann
2023-09-29 6:39 ` Bastian Koppelmann [this message]
2023-09-29 6:39 ` [PULL v3 09/16] target/tricore: Swap src and dst reg for RCRR_INSERT Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 10/16] target/tricore: Replace cpu_*_code with translator_* Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 11/16] target/tricore: Fix FTOUZ being ISA v1.3.1 up Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 12/16] tests/tcg/tricore: Extended and non-extened regs now match Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 13/16] hw/tricore: Log failing test in testdevice Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 14/16] tests/tcg: Reset result register after each test Bastian Koppelmann
2023-09-29 6:39 ` [PULL v3 15/16] target/tricore: Remove CSFRs from cpu.h Bastian Koppelmann
2023-09-29 6:40 ` [PULL v3 16/16] target/tricore: Change effective address (ea) to target_ulong Bastian Koppelmann
2023-10-02 21:56 ` [PULL v3 00/16] tricore queue Stefan Hajnoczi
2023-10-02 23:06 ` Michael Tokarev
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