From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 06/10] tcg/loongarch64: Use tcg_use_softmmu
Date: Tue, 3 Oct 2023 10:43:52 -0700 [thread overview]
Message-ID: <20231003174356.1602279-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231003174356.1602279-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 126 +++++++++++++++----------------
1 file changed, 61 insertions(+), 65 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 8f7091002b..dd3cab545b 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -165,10 +165,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
return TCG_REG_A0 + slot;
}
-#ifndef CONFIG_SOFTMMU
-#define USE_GUEST_BASE (guest_base != 0)
#define TCG_GUEST_BASE_REG TCG_REG_S1
-#endif
#define TCG_CT_CONST_ZERO 0x100
#define TCG_CT_CONST_S12 0x200
@@ -908,76 +905,77 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
a_bits = h->aa.align;
-#ifdef CONFIG_SOFTMMU
- unsigned s_bits = opc & MO_SIZE;
- int mem_index = get_mmuidx(oi);
- int fast_ofs = tlb_mask_table_ofs(s, mem_index);
- int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
- int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
+ if (tcg_use_softmmu) {
+ unsigned s_bits = opc & MO_SIZE;
+ int mem_index = get_mmuidx(oi);
+ int fast_ofs = tlb_mask_table_ofs(s, mem_index);
+ int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
+ int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
- ldst = new_ldst_label(s);
- ldst->is_ld = is_ld;
- ldst->oi = oi;
- ldst->addrlo_reg = addr_reg;
-
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs);
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
-
- tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg,
- s->page_bits - CPU_TLB_ENTRY_BITS);
- tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
- tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
-
- /* Load the tlb comparator and the addend. */
- QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
- tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2,
- is_ld ? offsetof(CPUTLBEntry, addr_read)
- : offsetof(CPUTLBEntry, addr_write));
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
- offsetof(CPUTLBEntry, addend));
-
- /*
- * For aligned accesses, we check the first byte and include the alignment
- * bits within the address. For unaligned access, we check that we don't
- * cross pages using the address of the last byte of the access.
- */
- if (a_bits < s_bits) {
- unsigned a_mask = (1u << a_bits) - 1;
- unsigned s_mask = (1u << s_bits) - 1;
- tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask);
- } else {
- tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg);
- }
- tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO,
- a_bits, s->page_bits - 1);
-
- /* Compare masked address with the TLB entry. */
- ldst->label_ptr[0] = s->code_ptr;
- tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0);
-
- h->index = TCG_REG_TMP2;
-#else
- if (a_bits) {
ldst = new_ldst_label(s);
-
ldst->is_ld = is_ld;
ldst->oi = oi;
ldst->addrlo_reg = addr_reg;
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs);
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
+
+ tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg,
+ s->page_bits - CPU_TLB_ENTRY_BITS);
+ tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
+ tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
+
+ /* Load the tlb comparator and the addend. */
+ QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
+ tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2,
+ is_ld ? offsetof(CPUTLBEntry, addr_read)
+ : offsetof(CPUTLBEntry, addr_write));
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
+ offsetof(CPUTLBEntry, addend));
+
/*
- * Without micro-architecture details, we don't know which of
- * bstrpick or andi is faster, so use bstrpick as it's not
- * constrained by imm field width. Not to say alignments >= 2^12
- * are going to happen any time soon.
+ * For aligned accesses, we check the first byte and include the
+ * alignment bits within the address. For unaligned access, we
+ * check that we don't cross pages using the address of the last
+ * byte of the access.
*/
- tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1);
+ if (a_bits < s_bits) {
+ unsigned a_mask = (1u << a_bits) - 1;
+ unsigned s_mask = (1u << s_bits) - 1;
+ tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask);
+ } else {
+ tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg);
+ }
+ tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO,
+ a_bits, s->page_bits - 1);
+ /* Compare masked address with the TLB entry. */
ldst->label_ptr[0] = s->code_ptr;
- tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0);
- }
+ tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0);
- h->index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
-#endif
+ h->index = TCG_REG_TMP2;
+ } else {
+ if (a_bits) {
+ ldst = new_ldst_label(s);
+
+ ldst->is_ld = is_ld;
+ ldst->oi = oi;
+ ldst->addrlo_reg = addr_reg;
+
+ /*
+ * Without micro-architecture details, we don't know which of
+ * bstrpick or andi is faster, so use bstrpick as it's not
+ * constrained by imm field width. Not to say alignments >= 2^12
+ * are going to happen any time soon.
+ */
+ tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1);
+
+ ldst->label_ptr[0] = s->code_ptr;
+ tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0);
+ }
+
+ h->index = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
+ }
if (addr_type == TCG_TYPE_I32) {
h->base = TCG_REG_TMP0;
@@ -2272,12 +2270,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
}
-#if !defined(CONFIG_SOFTMMU)
- if (USE_GUEST_BASE) {
+ if (!tcg_use_softmmu && guest_base) {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
}
-#endif
/* Call generated code */
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
--
2.34.1
next prev parent reply other threads:[~2023-10-03 17:44 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-03 17:43 [PATCH 00/10] tcg: Allow softmmu for user-only Richard Henderson
2023-10-03 17:43 ` [PATCH 01/10] tcg: Introduce tcg_use_softmmu Richard Henderson
2023-10-04 6:27 ` Philippe Mathieu-Daudé
2023-10-03 17:43 ` [PATCH 02/10] tcg: Provide guest_base fallback for system mode Richard Henderson
2023-10-04 6:43 ` Philippe Mathieu-Daudé
2023-10-03 17:43 ` [PATCH 03/10] tcg/arm: Use tcg_use_softmmu Richard Henderson
2023-10-05 16:53 ` Philippe Mathieu-Daudé
2023-10-13 3:41 ` Richard Henderson
2023-10-03 17:43 ` [PATCH 04/10] tcg/aarch64: " Richard Henderson
2023-10-04 6:35 ` Philippe Mathieu-Daudé
2023-10-03 17:43 ` [PATCH 05/10] tcg/i386: " Richard Henderson
2023-10-05 16:51 ` Philippe Mathieu-Daudé
2023-10-03 17:43 ` Richard Henderson [this message]
2023-10-04 6:37 ` [PATCH 06/10] tcg/loongarch64: " Philippe Mathieu-Daudé
2023-10-03 17:43 ` [PATCH 07/10] tcg/mips: " Richard Henderson
2023-10-04 6:35 ` Philippe Mathieu-Daudé
2023-10-03 17:43 ` [PATCH 08/10] tcg/ppc: " Richard Henderson
2023-10-04 6:40 ` Philippe Mathieu-Daudé
2023-10-03 17:43 ` [PATCH 09/10] tcg/riscv: " Richard Henderson
2023-10-04 6:42 ` Philippe Mathieu-Daudé
2023-10-05 16:57 ` Philippe Mathieu-Daudé
2023-10-03 17:43 ` [PATCH 10/10] tcg/s390x: " Richard Henderson
2023-10-04 6:42 ` Philippe Mathieu-Daudé
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