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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id g14-20020a056000118e00b003231ca246b6sm3386048wrx.95.2023.10.04.01.13.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 01:13:02 -0700 (PDT) Date: Wed, 4 Oct 2023 10:13:01 +0200 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, "Paul A . Clarke" Subject: Re: [PATCH] target/riscv/tcg: remove RVG warning Message-ID: <20231004-5e0c2c9d1723355b793d1cca@orel> References: <20231003122539.775932-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231003122539.775932-1-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Oct 03, 2023 at 09:25:39AM -0300, Daniel Henrique Barboza wrote: > Vendor CPUs that set RVG are displaying user warnings about other > extensions that RVG must enable, one warning per CPU. E.g.: > > $ ./build/qemu-system-riscv64 -smp 8 -M virt -cpu veyron-v1 -nographic > qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei > qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei > qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei > qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei > qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei > qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei > qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei > qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei > > This happens because we decided a while ago that, for simplicity, vendor > CPUs could set RVG instead of setting each G extension individually in > their cpu_init(). Our warning isn't taking that into account, and we're > bugging users with a warning that we're causing ourselves. > > In a closer look we conclude that this warning is not warranted in any > other circumstance since we're just following the ISA [1], which states > in chapter 24: > > "One goal of the RISC-V project is that it be used as a stable software > development target. For this purpose, we define a combination of a base > ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr, > Zifencei) as a 'general-purpose' ISA, and we use the abbreviation G for > the IMAFDZicsr Zifencei combination of instruction-set extensions." > > With this in mind, enabling IMAFD_Zicsr_Zifencei if the user explicitly > enables 'G' is an expected behavior and the warning is unneeded. Any > user caught by surprise should refer to the ISA. > > Remove the warning when handling RVG. > > [1] https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf > > Reported-by: Paul A. Clarke > Suggested-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/tcg/tcg-cpu.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index 08b806dc07..f50ce57602 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -293,7 +293,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > return; > } > > - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); > cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true); > cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true); > > -- > 2.41.0 > Reviewed-by: Andrew Jones