From: Bernhard Beschow <shentey@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Chuck Zmudzinski" <brchuckz@aol.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Hervé Poussineau" <hpoussin@reactos.org>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Bernhard Beschow" <shentey@gmail.com>
Subject: [PATCH v8 29/29] hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine
Date: Sat, 7 Oct 2023 14:38:37 +0200 [thread overview]
Message-ID: <20231007123843.127151-30-shentey@gmail.com> (raw)
In-Reply-To: <20231007123843.127151-1-shentey@gmail.com>
QEMU's PIIX3 implementation actually models the real PIIX4, but with different
PCI IDs. Usually, guests deal just fine with it. Still, in order to provide a
more consistent illusion to guests, allow QEMU's PIIX4 implementation to be used
in the PC machine.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
docs/system/target-i386-desc.rst.inc | 8 ++++
include/hw/i386/pc.h | 2 +
hw/i386/pc.c | 1 +
hw/i386/pc_piix.c | 61 +++++++++++++++++++++++++++-
4 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/docs/system/target-i386-desc.rst.inc b/docs/system/target-i386-desc.rst.inc
index 7d1fffacbe..5ebbcda9db 100644
--- a/docs/system/target-i386-desc.rst.inc
+++ b/docs/system/target-i386-desc.rst.inc
@@ -71,3 +71,11 @@ machine property, i.e.
|qemu_system_x86| some.img \
-audiodev <backend>,id=<name> \
-machine pcspk-audiodev=<name>
+
+Machine-specific options
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+It supports the following machine-specific options:
+
+- ``x-south-bridge=PIIX3|piix4-isa`` (Experimental option to select a particular
+ south bridge. Default: ``PIIX3``)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index bec38cb92c..29a9724524 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -42,6 +42,7 @@ typedef struct PCMachineState {
uint64_t max_ram_below_4g;
OnOffAuto vmport;
SmbiosEntryPointType smbios_entry_point_type;
+ const char *south_bridge;
bool acpi_build_enabled;
bool smbus_enabled;
@@ -92,6 +93,7 @@ struct PCMachineClass {
/* Device configuration: */
bool pci_enabled;
bool kvmclock_enabled;
+ const char *default_south_bridge;
/* Compat options: */
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 4e844d02f2..c84d1bdf08 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1707,6 +1707,7 @@ static void pc_machine_initfn(Object *obj)
#endif /* CONFIG_VMPORT */
pcms->max_ram_below_4g = 0; /* use default */
pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
+ pcms->south_bridge = pcmc->default_south_bridge;
/* acpi build is enabled by default if machine supports it */
pcms->acpi_build_enabled = pcmc->has_acpi_build;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index e38942a3c3..334d9a0299 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -262,7 +262,7 @@ static void pc_init1(MachineState *machine,
DeviceState *dev;
size_t i;
- pci_dev = pci_new_multifunction(-1, TYPE_PIIX3_DEVICE);
+ pci_dev = pci_new_multifunction(-1, pcms->south_bridge);
object_property_set_bool(OBJECT(pci_dev), "has-usb",
machine_usb(machine), &error_abort);
object_property_set_bool(OBJECT(pci_dev), "has-acpi",
@@ -394,6 +394,56 @@ static void pc_init1(MachineState *machine,
}
}
+typedef enum PCSouthBridgeOption {
+ PC_SOUTH_BRIDGE_OPTION_PIIX3,
+ PC_SOUTH_BRIDGE_OPTION_PIIX4,
+ PC_SOUTH_BRIDGE_OPTION_MAX,
+} PCSouthBridgeOption;
+
+static const QEnumLookup PCSouthBridgeOption_lookup = {
+ .array = (const char *const[]) {
+ [PC_SOUTH_BRIDGE_OPTION_PIIX3] = TYPE_PIIX3_DEVICE,
+ [PC_SOUTH_BRIDGE_OPTION_PIIX4] = TYPE_PIIX4_PCI_DEVICE,
+ },
+ .size = PC_SOUTH_BRIDGE_OPTION_MAX
+};
+
+#define NotifyVmexitOption_str(val) \
+ qapi_enum_lookup(&NotifyVmexitOption_lookup, (val))
+
+static int pc_get_south_bridge(Object *obj, Error **errp)
+{
+ PCMachineState *pcms = PC_MACHINE(obj);
+ int i;
+
+ for (i = 0; i < PCSouthBridgeOption_lookup.size; i++) {
+ if (g_strcmp0(PCSouthBridgeOption_lookup.array[i],
+ pcms->south_bridge) == 0) {
+ return i;
+ }
+ }
+
+ error_setg(errp, "Invalid south bridge value set");
+ return 0;
+}
+
+static void pc_set_south_bridge(Object *obj, int value, Error **errp)
+{
+ PCMachineState *pcms = PC_MACHINE(obj);
+
+ if (value < 0) {
+ error_setg(errp, "Value can't be negative");
+ return;
+ }
+
+ if (value >= PCSouthBridgeOption_lookup.size) {
+ error_setg(errp, "Value too big");
+ return;
+ }
+
+ pcms->south_bridge = PCSouthBridgeOption_lookup.array[value];
+}
+
/* Looking for a pc_compat_2_4() function? It doesn't exist.
* pc_compat_*() functions that run on machine-init time and
* change global QEMU state are deprecated. Please don't create
@@ -473,6 +523,8 @@ static void pc_xen_hvm_init(MachineState *machine)
static void pc_i440fx_machine_options(MachineClass *m)
{
PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
+ ObjectClass *oc = OBJECT_CLASS(m);
+ pcmc->default_south_bridge = TYPE_PIIX3_DEVICE;
pcmc->pci_root_uid = 0;
pcmc->default_cpu_version = 1;
@@ -484,6 +536,13 @@ static void pc_i440fx_machine_options(MachineClass *m)
m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
+
+ object_class_property_add_enum(oc, "x-south-bridge", "PCSouthBridgeOption",
+ &PCSouthBridgeOption_lookup,
+ pc_get_south_bridge,
+ pc_set_south_bridge);
+ object_class_property_set_description(oc, "x-south-bridge",
+ "Use a different south bridge than PIIX3");
}
static void pc_i440fx_8_2_machine_options(MachineClass *m)
--
2.42.0
next prev parent reply other threads:[~2023-10-07 12:42 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-07 12:38 [PATCH v8 00/29] Consolidate PIIX south bridges Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 01/29] hw/i386/pc: Merge two if statements into one Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 02/29] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 03/29] hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize() Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 04/29] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 05/29] hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 06/29] hw/i386/pc_piix: Remove redundant "piix3" variable Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 07/29] hw/isa/piix3: Rename "pic" attribute to "isa_irqs_in" Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 08/29] hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize() Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 09/29] hw/isa/piix3: Wire PIC IRQs to ISA bus in host device Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 10/29] hw/i386/pc: Wire RTC ISA IRQs in south bridges Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 11/29] hw/isa/piix3: Create IDE controller in host device Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 12/29] hw/isa/piix3: Create USB " Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 13/29] hw/isa/piix3: Create power management " Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 14/29] hw/isa/piix3: Drop the "3" from PIIX base class name Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 15/29] hw/isa/piix4: Remove unused inbound ISA interrupt lines Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 16/29] hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in" Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 17/29] hw/isa/piix4: Rename reset control operations to match PIIX3 Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 18/29] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 19/29] hw/isa/piix3: Merge hw/isa/piix4.c Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 20/29] hw/isa/piix: Allow for optional PIC creation in PIIX3 Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 21/29] hw/isa/piix: Allow for optional PIT " Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 22/29] hw/isa/piix: Harmonize names of reset control memory regions Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 23/29] hw/isa/piix: Share PIIX3's base class with PIIX4 Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 24/29] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 25/29] hw/isa/piix: Rename functions to be shared for PCI interrupt triggering Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 26/29] hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4 Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 27/29] hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring Bernhard Beschow
2023-10-07 12:38 ` [PATCH v8 28/29] hw/isa/piix: Implement multi-process QEMU support also for PIIX4 Bernhard Beschow
2023-10-07 12:38 ` Bernhard Beschow [this message]
2023-10-08 17:56 ` [PATCH v8 00/29] Consolidate PIIX south bridges Chuck Zmudzinski
2023-10-11 18:57 ` Bernhard Beschow
2023-10-11 20:18 ` Michael S. Tsirkin
2023-10-12 18:13 ` Bernhard Beschow
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