From: Salil Mehta via <qemu-devel@nongnu.org> To: <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org> Cc: <salil.mehta@huawei.com>, <maz@kernel.org>, <jean-philippe@linaro.org>, <jonathan.cameron@huawei.com>, <lpieralisi@kernel.org>, <peter.maydell@linaro.org>, <richard.henderson@linaro.org>, <imammedo@redhat.com>, <andrew.jones@linux.dev>, <david@redhat.com>, <philmd@linaro.org>, <eric.auger@redhat.com>, <oliver.upton@linux.dev>, <pbonzini@redhat.com>, <mst@redhat.com>, <will@kernel.org>, <gshan@redhat.com>, <rafael@kernel.org>, <alex.bennee@linaro.org>, <linux@armlinux.org.uk>, <darren@os.amperecomputing.com>, <ilkka@os.amperecomputing.com>, <vishnu@os.amperecomputing.com>, <karl.heubaum@oracle.com>, <miguel.luis@oracle.com>, <salil.mehta@opnsrc.net>, <zhukeqian1@huawei.com>, <wangxiongfeng2@huawei.com>, <wangyanan55@huawei.com>, <jiakernel2@gmail.com>, <maobibo@loongson.cn>, <lixianglai@loongson.cn>, <linuxarm@huawei.com> Subject: [PATCH V3 05/10] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change Date: Mon, 9 Oct 2023 12:28:07 +0100 [thread overview] Message-ID: <20231009112812.10612-6-salil.mehta@huawei.com> (raw) In-Reply-To: <20231009112812.10612-1-salil.mehta@huawei.com> CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based on PCI and is IO port based and hence existing CPUs AML code assumes _CRS objects would evaluate to a system resource which describes IO Port address. But on ARM arch CPUs control device(\\_SB.PRES) register interface is memory-mapped hence _CRS object should evaluate to system resource which describes memory-mapped base address. Update build CPUs AML function to accept both IO/MEMORY region spaces and accordingly update the _CRS object. Legacy CPU Hotplug uses Generic ACPI GPE Block Bit 2 (GPE.2) event handler to notify OSPM about any CPU hot(un)plug events. GED framework uses new register interface for cpu-(ctrl)dev. Make AML for GPE.2 event handler conditional. Co-developed-by: Keqian Zhu <zhukeqian1@huawei.com> Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com> Signed-off-by: Salil Mehta <salil.mehta@huawei.com> Reviewed-by: Gavin Shan <gshan@redhat.com> --- hw/acpi/cpu.c | 23 ++++++++++++++++------- hw/i386/acpi-build.c | 2 +- include/hw/acpi/cpu.h | 5 +++-- 3 files changed, 20 insertions(+), 10 deletions(-) diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index 45defdc0e2..66a71660ec 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -338,9 +338,10 @@ const VMStateDescription vmstate_cpu_hotplug = { #define CPU_FW_EJECT_EVENT "CEJF" void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, - hwaddr io_base, + hwaddr base_addr, const char *res_root, - const char *event_handler_method) + const char *event_handler_method, + AmlRegionSpace rs) { Aml *ifctx; Aml *field; @@ -367,13 +368,19 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0)); crs = aml_resource_template(); - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1, + if (rs == AML_SYSTEM_IO) { + aml_append(crs, aml_io(AML_DECODE16, base_addr, base_addr, 1, ACPI_CPU_HOTPLUG_REG_LEN)); + } else { + aml_append(crs, aml_memory32_fixed(base_addr, + ACPI_CPU_HOTPLUG_REG_LEN, AML_READ_WRITE)); + } + aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs)); /* declare CPU hotplug MMIO region with related access fields */ aml_append(cpu_ctrl_dev, - aml_operation_region("PRST", AML_SYSTEM_IO, aml_int(io_base), + aml_operation_region("PRST", rs, aml_int(base_addr), ACPI_CPU_HOTPLUG_REG_LEN)); field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, @@ -699,9 +706,11 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, aml_append(sb_scope, cpus_dev); aml_append(table, sb_scope); - method = aml_method(event_handler_method, 0, AML_NOTSERIALIZED); - aml_append(method, aml_call0("\\_SB.CPUS." CPU_SCAN_METHOD)); - aml_append(table, method); + if (event_handler_method) { + method = aml_method(event_handler_method, 0, AML_NOTSERIALIZED); + aml_append(method, aml_call0("\\_SB.CPUS." CPU_SCAN_METHOD)); + aml_append(table, method); + } g_free(cphp_res_path); } diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 4d2d40bab5..611d3d044d 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1550,7 +1550,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, .fw_unplugs_cpu = pm->smi_on_cpu_unplug, }; build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, - "\\_SB.PCI0", "\\_GPE._E02"); + "\\_SB.PCI0", "\\_GPE._E02", AML_SYSTEM_IO); } if (pcms->memhp_io_base && nr_mem) { diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index 999caaf510..b87ebfdf4b 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -56,9 +56,10 @@ typedef struct CPUHotplugFeatures { } CPUHotplugFeatures; void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, - hwaddr io_base, + hwaddr base_addr, const char *res_root, - const char *event_handler_method); + const char *event_handler_method, + AmlRegionSpace rs); void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list); -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Salil Mehta <salil.mehta@huawei.com> To: <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org> Cc: <salil.mehta@huawei.com>, <maz@kernel.org>, <jean-philippe@linaro.org>, <jonathan.cameron@huawei.com>, <lpieralisi@kernel.org>, <peter.maydell@linaro.org>, <richard.henderson@linaro.org>, <imammedo@redhat.com>, <andrew.jones@linux.dev>, <david@redhat.com>, <philmd@linaro.org>, <eric.auger@redhat.com>, <oliver.upton@linux.dev>, <pbonzini@redhat.com>, <mst@redhat.com>, <will@kernel.org>, <gshan@redhat.com>, <rafael@kernel.org>, <alex.bennee@linaro.org>, <linux@armlinux.org.uk>, <darren@os.amperecomputing.com>, <ilkka@os.amperecomputing.com>, <vishnu@os.amperecomputing.com>, <karl.heubaum@oracle.com>, <miguel.luis@oracle.com>, <salil.mehta@opnsrc.net>, <zhukeqian1@huawei.com>, <wangxiongfeng2@huawei.com>, <wangyanan55@huawei.com>, <jiakernel2@gmail.com>, <maobibo@loongson.cn>, <lixianglai@loongson.cn>, <linuxarm@huawei.com> Subject: [PATCH V3 05/10] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change Date: Mon, 9 Oct 2023 12:28:07 +0100 [thread overview] Message-ID: <20231009112812.10612-6-salil.mehta@huawei.com> (raw) Message-ID: <20231009112807.SWgtLS9y60dwGaZYWUX8gMCRCVrDN1rHE1fsSIF0ne0@z> (raw) In-Reply-To: <20231009112812.10612-1-salil.mehta@huawei.com> CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based on PCI and is IO port based and hence existing CPUs AML code assumes _CRS objects would evaluate to a system resource which describes IO Port address. But on ARM arch CPUs control device(\\_SB.PRES) register interface is memory-mapped hence _CRS object should evaluate to system resource which describes memory-mapped base address. Update build CPUs AML function to accept both IO/MEMORY region spaces and accordingly update the _CRS object. Legacy CPU Hotplug uses Generic ACPI GPE Block Bit 2 (GPE.2) event handler to notify OSPM about any CPU hot(un)plug events. GED framework uses new register interface for cpu-(ctrl)dev. Make AML for GPE.2 event handler conditional. Co-developed-by: Keqian Zhu <zhukeqian1@huawei.com> Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com> Signed-off-by: Salil Mehta <salil.mehta@huawei.com> Reviewed-by: Gavin Shan <gshan@redhat.com> --- hw/acpi/cpu.c | 23 ++++++++++++++++------- hw/i386/acpi-build.c | 2 +- include/hw/acpi/cpu.h | 5 +++-- 3 files changed, 20 insertions(+), 10 deletions(-) diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index 45defdc0e2..66a71660ec 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -338,9 +338,10 @@ const VMStateDescription vmstate_cpu_hotplug = { #define CPU_FW_EJECT_EVENT "CEJF" void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, - hwaddr io_base, + hwaddr base_addr, const char *res_root, - const char *event_handler_method) + const char *event_handler_method, + AmlRegionSpace rs) { Aml *ifctx; Aml *field; @@ -367,13 +368,19 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0)); crs = aml_resource_template(); - aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1, + if (rs == AML_SYSTEM_IO) { + aml_append(crs, aml_io(AML_DECODE16, base_addr, base_addr, 1, ACPI_CPU_HOTPLUG_REG_LEN)); + } else { + aml_append(crs, aml_memory32_fixed(base_addr, + ACPI_CPU_HOTPLUG_REG_LEN, AML_READ_WRITE)); + } + aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs)); /* declare CPU hotplug MMIO region with related access fields */ aml_append(cpu_ctrl_dev, - aml_operation_region("PRST", AML_SYSTEM_IO, aml_int(io_base), + aml_operation_region("PRST", rs, aml_int(base_addr), ACPI_CPU_HOTPLUG_REG_LEN)); field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, @@ -699,9 +706,11 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, aml_append(sb_scope, cpus_dev); aml_append(table, sb_scope); - method = aml_method(event_handler_method, 0, AML_NOTSERIALIZED); - aml_append(method, aml_call0("\\_SB.CPUS." CPU_SCAN_METHOD)); - aml_append(table, method); + if (event_handler_method) { + method = aml_method(event_handler_method, 0, AML_NOTSERIALIZED); + aml_append(method, aml_call0("\\_SB.CPUS." CPU_SCAN_METHOD)); + aml_append(table, method); + } g_free(cphp_res_path); } diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 4d2d40bab5..611d3d044d 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1550,7 +1550,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, .fw_unplugs_cpu = pm->smi_on_cpu_unplug, }; build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, - "\\_SB.PCI0", "\\_GPE._E02"); + "\\_SB.PCI0", "\\_GPE._E02", AML_SYSTEM_IO); } if (pcms->memhp_io_base && nr_mem) { diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index 999caaf510..b87ebfdf4b 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -56,9 +56,10 @@ typedef struct CPUHotplugFeatures { } CPUHotplugFeatures; void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, - hwaddr io_base, + hwaddr base_addr, const char *res_root, - const char *event_handler_method); + const char *event_handler_method, + AmlRegionSpace rs); void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list); -- 2.34.1
next prev parent reply other threads:[~2023-10-09 11:31 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-10-09 11:28 [PATCH V3 00/10] Add architecture agnostic code to support vCPU Hotplug Salil Mehta via 2023-10-09 11:28 ` Salil Mehta 2023-10-09 11:28 ` [PATCH V3 01/10] accel/kvm: Extract common KVM vCPU {creation, parking} code Salil Mehta via 2023-10-09 11:28 ` Salil Mehta 2023-10-09 12:20 ` [PATCH V3 01/10] accel/kvm: Extract common KVM vCPU {creation,parking} code David Hildenbrand 2023-10-09 13:42 ` Salil Mehta via 2023-10-09 13:42 ` Salil Mehta 2023-10-09 14:11 ` David Hildenbrand 2023-10-09 15:10 ` Salil Mehta via 2023-10-09 15:10 ` Salil Mehta 2023-10-09 15:21 ` David Hildenbrand 2023-10-09 15:34 ` Salil Mehta via 2023-10-09 15:34 ` Salil Mehta 2023-10-09 11:28 ` [PATCH V3 02/10] hw/acpi: Move CPU ctrl-dev MMIO region len macro to common header file Salil Mehta via 2023-10-09 11:28 ` Salil Mehta 2023-10-09 12:21 ` David Hildenbrand 2023-10-09 13:43 ` Salil Mehta via 2023-10-09 13:43 ` Salil Mehta 2023-10-09 11:28 ` [PATCH V3 03/10] hw/acpi: Add ACPI CPU hotplug init stub Salil Mehta via 2023-10-09 11:28 ` Salil Mehta 2023-10-09 12:22 ` David Hildenbrand 2023-10-09 13:49 ` Salil Mehta via 2023-10-09 13:49 ` Salil Mehta 2023-10-09 13:55 ` David Hildenbrand 2023-10-09 15:45 ` Salil Mehta via 2023-10-09 15:45 ` Salil Mehta 2023-10-09 11:28 ` [PATCH V3 04/10] hw/acpi: Init GED framework with cpu hotplug events Salil Mehta via 2023-10-09 11:28 ` Salil Mehta 2023-10-09 12:26 ` David Hildenbrand 2023-10-09 14:12 ` Salil Mehta via 2023-10-09 14:12 ` Salil Mehta 2023-10-09 14:14 ` David Hildenbrand 2023-10-09 15:42 ` Salil Mehta via 2023-10-09 15:42 ` Salil Mehta 2023-10-09 11:28 ` Salil Mehta via [this message] 2023-10-09 11:28 ` [PATCH V3 05/10] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change Salil Mehta 2023-10-09 11:28 ` [PATCH V3 06/10] hw/acpi: Update GED _EVT method AML with CPU scan Salil Mehta via 2023-10-09 11:28 ` Salil Mehta 2023-10-09 11:28 ` [PATCH V3 07/10] hw/acpi: Update ACPI GED framework to support vCPU Hotplug Salil Mehta via 2023-10-09 11:28 ` Salil Mehta 2023-10-09 11:28 ` [PATCH V3 08/10] physmem: Add helper function to destroy CPU AddressSpace Salil Mehta via 2023-10-09 11:28 ` Salil Mehta 2023-10-09 11:28 ` [PATCH V3 09/10] gdbstub: Add helper function to unregister GDB register space Salil Mehta via 2023-10-09 11:28 ` Salil Mehta 2023-10-09 11:28 ` [PATCH V3 10/10] target/arm/kvm: Write CPU state back to KVM on reset Salil Mehta via 2023-10-09 11:28 ` Salil Mehta
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