[PATCH 00/18] target: Make 'cpu-qom.h' really target agnostic

[PATCH 00/18] target: Make 'cpu-qom.h' really target agnostic

[Philippe Mathieu-Daudé]

A heterogeneous machine must be able to instantiate CPUs
from different architectures. In order to do that, the
common hw/ code has to access to the QOM CPU definitions
from various architecture.

Those QOM definitions are published in "target/foo/cpu-qom.h".
All 'cpu-qom.h' must be target agnostic, so hw/ can include
multiple of them in order to create a heterogeneous machine.

This series strengthen all (except PPC...) target 'cpu-qom.h',
making them target agnostic.

For various targets it is just a matter of moving definitions
where they belong (either 'cpu.h' or 'cpu-qom.h').

For few (mips/riscv/sparc/x86) we have to remove the target
specific definitions (which 'taint' the header as target specific).

For mips/sparc/x86 this implies splitting the base target
definition by making it explicit to the build type (32 or 64-bit).

PPC is missing because CPU types are currently registered
indistinctly, and whether a CPU is 32/64 bit can not be detected
at build time (it is done in each cpu_class_init() handler,
*after* the type is registered).

Based-on: <20231010074952.79165-1-philmd@linaro.org>
  Introduce qtest_get_base_arch() / qtest_get_arch_bits()

Philippe Mathieu-Daudé (18):
  target: Mention 'cpu-qom.h' is target agnostic
  target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'
  target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'
  target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'
  target/hexagon: Declare QOM definitions in 'cpu-qom.h'
  target/loongarch: Declare QOM definitions in 'cpu-qom.h'
  target/nios2: Declare QOM definitions in 'cpu-qom.h'
  target/openrisc: Declare QOM definitions in 'cpu-qom.h'
  target/i386: Inline target specific TARGET_DEFAULT_CPU_TYPE definition
  target/riscv: Inline target specific TYPE_RISCV_CPU_BASE definition
  target/i386: Declare CPU QOM types using DEFINE_TYPES() macro
  target/mips: Declare CPU QOM types using DEFINE_TYPES() macro
  target/ppc: Declare CPU QOM types using DEFINE_TYPES() macro
  target/sparc: Declare CPU QOM types using DEFINE_TYPES() macro
  cpus: Open code OBJECT_DECLARE_TYPE() in OBJECT_DECLARE_CPU_TYPE()
  target/i386: Make X86_CPU common to new I386_CPU / X86_64_CPU types
  target/mips: Make MIPS_CPU common to new MIPS32_CPU / MIPS64_CPU types
  target/sparc: Make SPARC_CPU common to new SPARC32_CPU/SPARC64_CPU
    types

 include/hw/core/cpu.h       |  7 +++-
 target/alpha/cpu-qom.h      |  5 ++-
 target/alpha/cpu.h          |  2 --
 target/arm/cpu-qom.h        |  2 +-
 target/avr/cpu-qom.h        |  5 ++-
 target/avr/cpu.h            |  2 --
 target/cris/cpu-qom.h       |  5 ++-
 target/cris/cpu.h           |  2 --
 target/hexagon/cpu-qom.h    | 35 ++++++++++++++++++++
 target/hexagon/cpu.h        | 23 +------------
 target/hppa/cpu-qom.h       |  2 +-
 target/i386/cpu-qom.h       | 19 +++++++----
 target/i386/cpu.h           | 11 ++-----
 target/loongarch/cpu-qom.h  | 38 +++++++++++++++++++++
 target/loongarch/cpu.h      | 26 +--------------
 target/m68k/cpu-qom.h       |  5 ++-
 target/m68k/cpu.h           |  2 --
 target/microblaze/cpu-qom.h |  2 +-
 target/mips/cpu-qom.h       | 16 +++++----
 target/mips/cpu.h           |  5 +--
 target/nios2/cpu-qom.h      | 32 ++++++++++++++++++
 target/nios2/cpu.h          | 22 +------------
 target/openrisc/cpu-qom.h   | 36 ++++++++++++++++++++
 target/openrisc/cpu.h       | 26 +--------------
 target/ppc/cpu-qom.h        |  3 +-
 target/ppc/cpu.h            |  2 ++
 target/riscv/cpu-qom.h      |  9 +----
 target/riscv/cpu.h          |  2 ++
 target/rx/cpu-qom.h         |  5 ++-
 target/rx/cpu.h             |  2 --
 target/s390x/cpu-qom.h      |  5 ++-
 target/s390x/cpu.h          |  2 --
 target/sh4/cpu-qom.h        |  5 ++-
 target/sh4/cpu.h            |  2 --
 target/sparc/cpu-qom.h      | 14 ++++----
 target/sparc/cpu.h          |  5 +--
 target/tricore/cpu-qom.h    |  5 +++
 target/tricore/cpu.h        |  2 --
 target/xtensa/cpu-qom.h     |  5 ++-
 target/xtensa/cpu.h         |  2 --
 hw/i386/microvm.c           |  6 +++-
 hw/i386/pc.c                |  6 +++-
 hw/riscv/spike.c            |  8 ++++-
 hw/riscv/virt.c             |  8 ++++-
 target/i386/cpu.c           | 66 ++++++++++++++++++++++---------------
 target/mips/cpu.c           | 34 ++++++++++++-------
 target/ppc/cpu_init.c       | 52 +++++++++++++----------------
 target/sparc/cpu.c          | 35 +++++++++++++-------
 tests/qtest/cpu-plug-test.c |  2 +-
 49 files changed, 369 insertions(+), 248 deletions(-)
 create mode 100644 target/hexagon/cpu-qom.h
 create mode 100644 target/loongarch/cpu-qom.h
 create mode 100644 target/nios2/cpu-qom.h
 create mode 100644 target/openrisc/cpu-qom.h

-- 
2.41.0

[PATCH 01/18] target: Mention 'cpu-qom.h' is target agnostic

[Philippe Mathieu-Daudé]

"target/foo/cpu-qom.h" is supposed to be target agnostic
(include-able by any target). Add such mention in the
header.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/cpu-qom.h        | 2 +-
 target/hppa/cpu-qom.h       | 2 +-
 target/microblaze/cpu-qom.h | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index 514c22ced9..064317a245 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU ARM CPU
+ * QEMU ARM CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h
index b96e0318c7..a89a4f3a0a 100644
--- a/target/hppa/cpu-qom.h
+++ b/target/hppa/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU HPPA CPU
+ * QEMU HPPA CPU QOM header (target agnostic)
  *
  * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
  *
diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
index cda9220fa9..0e3ebaddb1 100644
--- a/target/microblaze/cpu-qom.h
+++ b/target/microblaze/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU MicroBlaze CPU
+ * QEMU MicroBlaze CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
-- 
2.41.0

[PATCH 02/18] target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'

[Philippe Mathieu-Daudé]

CPU_RESOLVING_TYPE is a per-target definition, and is
irrelevant for other targets. Move it to "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/ppc/cpu-qom.h | 3 +--
 target/ppc/cpu.h     | 2 ++
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index be33786bd8..41df51269b 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU PowerPC CPU
+ * QEMU PowerPC CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -33,7 +33,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU)
 
 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
-#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
 
 #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host")
 
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 30392ebeee..492fdecaf3 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -27,6 +27,8 @@
 #include "qom/object.h"
 #include "hw/registerfields.h"
 
+#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
+
 #define TCG_GUEST_DEFAULT_MO 0
 
 #define TARGET_PAGE_BITS_64K 16
-- 
2.41.0

[PATCH 03/18] target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'

[Philippe Mathieu-Daudé]

CPU_RESOLVING_TYPE is a per-target definition, and is
irrelevant for other targets. Move it to "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/cpu-qom.h | 1 -
 target/riscv/cpu.h     | 2 ++
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 04af50983e..8cb67b84a4 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -27,7 +27,6 @@
 
 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
-#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
 
 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ef9cf21c0c..374b813f20 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -31,6 +31,8 @@
 #include "qapi/qapi-types-common.h"
 #include "cpu-qom.h"
 
+#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
+
 #define TCG_GUEST_DEFAULT_MO 0
 
 /*
-- 
2.41.0

[PATCH 04/18] target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'

[Philippe Mathieu-Daudé]

Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME()
macro to resolve target CPU types. Move the declaration
(along with the required FOO_CPU_TYPE_SUFFIX) to "cpu-qom.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/alpha/cpu-qom.h   | 5 ++++-
 target/alpha/cpu.h       | 2 --
 target/avr/cpu-qom.h     | 5 ++++-
 target/avr/cpu.h         | 2 --
 target/cris/cpu-qom.h    | 5 ++++-
 target/cris/cpu.h        | 2 --
 target/i386/cpu-qom.h    | 3 +++
 target/i386/cpu.h        | 2 --
 target/m68k/cpu-qom.h    | 5 ++++-
 target/m68k/cpu.h        | 2 --
 target/mips/cpu-qom.h    | 3 +++
 target/mips/cpu.h        | 2 --
 target/rx/cpu-qom.h      | 5 ++++-
 target/rx/cpu.h          | 2 --
 target/s390x/cpu-qom.h   | 5 ++++-
 target/s390x/cpu.h       | 2 --
 target/sh4/cpu-qom.h     | 5 ++++-
 target/sh4/cpu.h         | 2 --
 target/sparc/cpu-qom.h   | 5 ++++-
 target/sparc/cpu.h       | 2 --
 target/tricore/cpu-qom.h | 5 +++++
 target/tricore/cpu.h     | 2 --
 target/xtensa/cpu-qom.h  | 5 ++++-
 target/xtensa/cpu.h      | 2 --
 24 files changed, 47 insertions(+), 33 deletions(-)

diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
index 1f200724b6..d596d1b69f 100644
--- a/target/alpha/cpu-qom.h
+++ b/target/alpha/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU Alpha CPU
+ * QEMU Alpha CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -27,6 +27,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
 
+#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
+#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
+
 /**
  * AlphaCPUClass:
  * @parent_realize: The parent class' realize handler.
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index e2a467ec17..ba0d9e3468 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -428,8 +428,6 @@ enum {
 
 void alpha_translate_init(void);
 
-#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
-#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
 
 void alpha_cpu_list(void);
diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
index 01ea5f160b..a810d6dc09 100644
--- a/target/avr/cpu-qom.h
+++ b/target/avr/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU AVR CPU
+ * QEMU AVR CPU QOM header (target agnostic)
  *
  * Copyright (c) 2016-2020 Michael Rolnik
  *
@@ -28,6 +28,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
 
+#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
+#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
+
 /**
  *  AVRCPUClass:
  *  @parent_realize: The parent class' realize handler.
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 4ce22d8e4f..d3f0cc65d4 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -28,8 +28,6 @@
 #error "AVR 8-bit does not support user mode"
 #endif
 
-#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
-#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
 #define CPU_RESOLVING_TYPE TYPE_AVR_CPU
 
 #define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h
index 431a1d536a..02a5b589b8 100644
--- a/target/cris/cpu-qom.h
+++ b/target/cris/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU CRIS CPU
+ * QEMU CRIS CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -27,6 +27,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
 
+#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
+#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
+
 /**
  * CRISCPUClass:
  * @parent_realize: The parent class' realize handler.
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 676b8e93ca..1af7ae5ef9 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -242,8 +242,6 @@ enum {
 /* CRIS uses 8k pages.  */
 #define MMAP_SHIFT TARGET_PAGE_BITS
 
-#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
-#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
 #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
 
 /* MMU modes definitions */
diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index 2350f4ae60..78207c0a7c 100644
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -32,6 +32,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
 
+#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
+#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
+
 typedef struct X86CPUModel X86CPUModel;
 
 /**
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e1875466b9..862e4f1ff5 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2241,8 +2241,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
 /* hw/pc.c */
 uint64_t cpu_get_tsc(CPUX86State *env);
 
-#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
-#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
 
 #ifdef TARGET_X86_64
diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
index 0ec7750a92..7192ecd71f 100644
--- a/target/m68k/cpu-qom.h
+++ b/target/m68k/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU Motorola 68k CPU
+ * QEMU Motorola 68k CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -27,6 +27,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
 
+#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
+#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
+
 /*
  * M68kCPUClass:
  * @parent_realize: The parent class' realize handler.
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 20afb0c94d..ae144ebc2f 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -563,8 +563,6 @@ enum {
     ACCESS_DATA  = 0x20, /* Data load/store access        */
 };
 
-#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
-#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU
 
 #define cpu_list m68k_cpu_list
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 0dffab453b..9c98ca1956 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -31,6 +31,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
 
+#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
+#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
+
 /**
  * MIPSCPUClass:
  * @parent_realize: The parent class' realize handler.
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 5fddceff3a..6b026e6bcf 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1303,8 +1303,6 @@ enum {
  */
 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
 
-#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
-#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
 
 bool cpu_type_supports_cps_smp(const char *cpu_type);
diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
index 1c8466a187..99fe771534 100644
--- a/target/rx/cpu-qom.h
+++ b/target/rx/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * RX CPU
+ * QEMU RX CPU QOM header (target agnostic)
  *
  * Copyright (c) 2019 Yoshinori Sato
  *
@@ -28,6 +28,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
 
+#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
+#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
+
 /*
  * RXCPUClass:
  * @parent_realize: The parent class' realize handler.
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index f66754eb8a..f89d88a37f 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -114,8 +114,6 @@ struct ArchCPU {
     CPURXState env;
 };
 
-#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
-#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_RX_CPU
 
 const char *rx_crname(uint8_t cr);
diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
index 00cae2b131..463fe16386 100644
--- a/target/s390x/cpu-qom.h
+++ b/target/s390x/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU S/390 CPU
+ * QEMU S/390 CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -27,6 +27,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU)
 
+#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
+#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
+
 typedef struct S390CPUModel S390CPUModel;
 typedef struct S390CPUDef S390CPUDef;
 
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 7bea7075e1..3e161862e5 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -810,8 +810,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
 
 
 /* helper.c */
-#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
-#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
 #define CPU_RESOLVING_TYPE TYPE_S390_CPU
 
 /* interrupt.c */
diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
index 89785a90f0..ed2de98949 100644
--- a/target/sh4/cpu-qom.h
+++ b/target/sh4/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU SuperH CPU
+ * QEMU SuperH CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -31,6 +31,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
 
+#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
+#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
+
 /**
  * SuperHCPUClass:
  * @parent_realize: The parent class' realize handler.
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index f75a235973..f44b3e5b25 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -252,8 +252,6 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
 
 void cpu_load_tlb(CPUSH4State * env);
 
-#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
-#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU
 
 #define cpu_list sh4_cpu_list
diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
index 78bf00b9a2..86b24a254a 100644
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU SPARC CPU
+ * QEMU SPARC CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -31,6 +31,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
 
+#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
+#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
+
 typedef struct sparc_def_t sparc_def_t;
 /**
  * SPARCCPUClass:
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index b3a98f1d74..924e83b9ce 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -650,8 +650,6 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
 #endif
 #endif
 
-#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
-#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU
 
 #define cpu_list sparc_cpu_list
diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h
index 612731daa0..5368689bd9 100644
--- a/target/tricore/cpu-qom.h
+++ b/target/tricore/cpu-qom.h
@@ -1,4 +1,6 @@
 /*
+ * QEMU TriCore CPU QOM header (target agnostic)
+ *
  *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
  *
  * This library is free software; you can redistribute it and/or
@@ -26,6 +28,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)
 
+#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
+#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
+
 struct TriCoreCPUClass {
     /*< private >*/
     CPUClass parent_class;
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index a357b573f2..fc09590a4f 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -270,8 +270,6 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc,
     *flags = new_flags;
 }
 
-#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
-#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU
 
 /* helpers.c */
diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h
index 419c7d8e4a..710ffa0403 100644
--- a/target/xtensa/cpu-qom.h
+++ b/target/xtensa/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU Xtensa CPU
+ * QEMU Xtensa CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  * All rights reserved.
@@ -36,6 +36,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU)
 
+#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
+#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
+
 typedef struct XtensaConfig XtensaConfig;
 
 /**
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index c6bbef1e5d..20ea6826e4 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -588,8 +588,6 @@ G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 
 #define cpu_list xtensa_cpu_list
 
-#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
-#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
 
 #if TARGET_BIG_ENDIAN
-- 
2.41.0

[PATCH 05/18] target/hexagon: Declare QOM definitions in 'cpu-qom.h'

[Philippe Mathieu-Daudé]

"target/foo/cpu.h" contains the target specific declarations.

A heterogeneous setup need to access target agnostic declarations
(at least the QOM ones, to instantiate the objects).

Our convention is to add such target agnostic QOM declarations in
the "target/foo/cpu-qom.h" header.

Extract QOM definitions from "cpu.h" to "cpu-qom.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/hexagon/cpu-qom.h | 35 +++++++++++++++++++++++++++++++++++
 target/hexagon/cpu.h     | 23 +----------------------
 2 files changed, 36 insertions(+), 22 deletions(-)
 create mode 100644 target/hexagon/cpu-qom.h

diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h
new file mode 100644
index 0000000000..cd45850c64
--- /dev/null
+++ b/target/hexagon/cpu-qom.h
@@ -0,0 +1,35 @@
+/*
+ * QEMU Hexagon CPU QOM header (target agnostic)
+ *
+ * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef QEMU_HEXAGON_CPU_QOM_H
+#define QEMU_HEXAGON_CPU_QOM_H
+
+#include "hw/core/cpu.h"
+#include "qom/object.h"
+
+#define TYPE_HEXAGON_CPU "hexagon-cpu"
+
+#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
+#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
+
+#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
+#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
+#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
+#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
+#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
+
+OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
+
+typedef struct HexagonCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+} HexagonCPUClass;
+
+#endif
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 10cd1efd57..7c3b993035 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -20,11 +20,10 @@
 
 #include "fpu/softfloat-types.h"
 
+#include "cpu-qom.h"
 #include "exec/cpu-defs.h"
 #include "hex_regs.h"
 #include "mmvec/mmvec.h"
-#include "qom/object.h"
-#include "hw/core/cpu.h"
 #include "hw/registerfields.h"
 
 #define NUM_PREGS 4
@@ -36,18 +35,8 @@
 #define PRED_WRITES_MAX 5                   /* 4 insns + endloop */
 #define VSTORES_MAX 2
 
-#define TYPE_HEXAGON_CPU "hexagon-cpu"
-
-#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
-#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU
 
-#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
-#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
-#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
-#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
-#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
-
 void hexagon_cpu_list(void);
 #define cpu_list hexagon_cpu_list
 
@@ -127,16 +116,6 @@ typedef struct CPUArchState {
     VTCMStoreLog vtcm_log;
 } CPUHexagonState;
 
-OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
-
-typedef struct HexagonCPUClass {
-    /*< private >*/
-    CPUClass parent_class;
-    /*< public >*/
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-} HexagonCPUClass;
-
 struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
-- 
2.41.0

[PATCH 06/18] target/loongarch: Declare QOM definitions in 'cpu-qom.h'

[Philippe Mathieu-Daudé]

"target/foo/cpu.h" contains the target specific declarations.

A heterogeneous setup need to access target agnostic declarations
(at least the QOM ones, to instantiate the objects).

Our convention is to add such target agnostic QOM declarations in
the "target/foo/cpu-qom.h" header.

Extract QOM definitions from "cpu.h" to "cpu-qom.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/loongarch/cpu-qom.h | 38 ++++++++++++++++++++++++++++++++++++++
 target/loongarch/cpu.h     | 26 +-------------------------
 2 files changed, 39 insertions(+), 25 deletions(-)
 create mode 100644 target/loongarch/cpu-qom.h

diff --git a/target/loongarch/cpu-qom.h b/target/loongarch/cpu-qom.h
new file mode 100644
index 0000000000..d577af9f6e
--- /dev/null
+++ b/target/loongarch/cpu-qom.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch CPU QOM header (target agnostic)
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_CPU_QOM_H
+#define LOONGARCH_CPU_QOM_H
+
+#include "hw/core/cpu.h"
+#include "qom/object.h"
+
+#define TYPE_LOONGARCH_CPU "loongarch-cpu"
+#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
+#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
+
+OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
+                        LOONGARCH_CPU)
+
+#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
+#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
+
+/**
+ * LoongArchCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A LoongArch CPU model.
+ */
+struct LoongArchCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
+
+#endif
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 40e70a8119..22cebc6280 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -17,6 +17,7 @@
 #include "exec/memory.h"
 #endif
 #include "cpu-csr.h"
+#include "cpu-qom.h"
 
 #define IOCSRF_TEMP             0
 #define IOCSRF_NODECNT          1
@@ -383,29 +384,6 @@ struct ArchCPU {
     const char *dtb_compatible;
 };
 
-#define TYPE_LOONGARCH_CPU "loongarch-cpu"
-#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
-#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
-
-OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
-                        LOONGARCH_CPU)
-
-/**
- * LoongArchCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A LoongArch CPU model.
- */
-struct LoongArchCPUClass {
-    /*< private >*/
-    CPUClass parent_class;
-    /*< public >*/
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-};
-
 /*
  * LoongArch CPUs has 4 privilege levels.
  * 0 for kernel mode, 3 for user mode.
@@ -482,8 +460,6 @@ void loongarch_cpu_list(void);
 
 #include "exec/cpu-all.h"
 
-#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
-#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
 
 #endif /* LOONGARCH_CPU_H */
-- 
2.41.0

[PATCH 07/18] target/nios2: Declare QOM definitions in 'cpu-qom.h'

[Philippe Mathieu-Daudé]

"target/foo/cpu.h" contains the target specific declarations.

A heterogeneous setup need to access target agnostic declarations
(at least the QOM ones, to instantiate the objects).

Our convention is to add such target agnostic QOM declarations in
the "target/foo/cpu-qom.h" header.

Extract QOM definitions from "cpu.h" to "cpu-qom.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/nios2/cpu-qom.h | 32 ++++++++++++++++++++++++++++++++
 target/nios2/cpu.h     | 22 +---------------------
 2 files changed, 33 insertions(+), 21 deletions(-)
 create mode 100644 target/nios2/cpu-qom.h

diff --git a/target/nios2/cpu-qom.h b/target/nios2/cpu-qom.h
new file mode 100644
index 0000000000..0bcf2c724f
--- /dev/null
+++ b/target/nios2/cpu-qom.h
@@ -0,0 +1,32 @@
+/*
+ * QEMU Nios II CPU QOM header (target agnostic)
+ *
+ * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef QEMU_NIOS2_CPU_QOM_H
+#define QEMU_NIOS2_CPU_QOM_H
+
+#include "hw/core/cpu.h"
+#include "qom/object.h"
+
+#define TYPE_NIOS2_CPU "nios2-cpu"
+
+OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
+
+/**
+ * Nios2CPUClass:
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A Nios2 CPU model.
+ */
+struct Nios2CPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
+
+#endif
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 70b6377a4f..e19e12b2a6 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -21,35 +21,15 @@
 #ifndef NIOS2_CPU_H
 #define NIOS2_CPU_H
 
+#include "cpu-qom.h"
 #include "exec/cpu-defs.h"
-#include "hw/core/cpu.h"
 #include "hw/registerfields.h"
-#include "qom/object.h"
 
 typedef struct CPUArchState CPUNios2State;
 #if !defined(CONFIG_USER_ONLY)
 #include "mmu.h"
 #endif
 
-#define TYPE_NIOS2_CPU "nios2-cpu"
-
-OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
-
-/**
- * Nios2CPUClass:
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A Nios2 CPU model.
- */
-struct Nios2CPUClass {
-    /*< private >*/
-    CPUClass parent_class;
-    /*< public >*/
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-};
-
 #define TARGET_HAS_ICE 1
 
 /* Configuration options for Nios II */
-- 
2.41.0

[PATCH 08/18] target/openrisc: Declare QOM definitions in 'cpu-qom.h'

[Philippe Mathieu-Daudé]

"target/foo/cpu.h" contains the target specific declarations.

A heterogeneous setup need to access target agnostic declarations
(at least the QOM ones, to instantiate the objects).

Our convention is to add such target agnostic QOM declarations in
the "target/foo/cpu-qom.h" header.

Extract QOM definitions from "cpu.h" to "cpu-qom.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/openrisc/cpu-qom.h | 36 ++++++++++++++++++++++++++++++++++++
 target/openrisc/cpu.h     | 26 +-------------------------
 2 files changed, 37 insertions(+), 25 deletions(-)
 create mode 100644 target/openrisc/cpu-qom.h

diff --git a/target/openrisc/cpu-qom.h b/target/openrisc/cpu-qom.h
new file mode 100644
index 0000000000..d1930acb74
--- /dev/null
+++ b/target/openrisc/cpu-qom.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU OpenRISC CPU QOM header (target agnostic)
+ *
+ * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef QEMU_OPENRISC_CPU_QOM_H
+#define QEMU_OPENRISC_CPU_QOM_H
+
+#include "hw/core/cpu.h"
+#include "qom/object.h"
+
+#define TYPE_OPENRISC_CPU "or1k-cpu"
+
+OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
+
+#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU
+#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
+
+/**
+ * OpenRISCCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A OpenRISC CPU model.
+ */
+struct OpenRISCCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
+
+#endif
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 334997e9a1..2dccd67378 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -20,33 +20,12 @@
 #ifndef OPENRISC_CPU_H
 #define OPENRISC_CPU_H
 
+#include "cpu-qom.h"
 #include "exec/cpu-defs.h"
 #include "fpu/softfloat-types.h"
-#include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TCG_GUEST_DEFAULT_MO (0)
 
-#define TYPE_OPENRISC_CPU "or1k-cpu"
-
-OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
-
-/**
- * OpenRISCCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A OpenRISC CPU model.
- */
-struct OpenRISCCPUClass {
-    /*< private >*/
-    CPUClass parent_class;
-    /*< public >*/
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-};
-
 #define TARGET_INSN_START_EXTRA_WORDS 1
 
 enum {
@@ -308,7 +287,6 @@ struct ArchCPU {
     CPUOpenRISCState env;
 };
 
-
 void cpu_openrisc_list(void);
 void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -343,8 +321,6 @@ void cpu_openrisc_count_start(OpenRISCCPU *cpu);
 void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
 #endif
 
-#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU
-#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
 
 #include "exec/cpu-all.h"
-- 
2.41.0

[PATCH 09/18] target/i386: Inline target specific TARGET_DEFAULT_CPU_TYPE definition

[Philippe Mathieu-Daudé]

TARGET_DEFAULT_CPU_TYPE depends on the TARGET_X86_64 definition
which is target specific. Such target specific definition taint
"cpu-qom.h".

Since "cpu-qom.h" must be target agnostic, remove this target
specific definition uses by inlining TARGET_DEFAULT_CPU_TYPE in
the two machines using it.

"target/i386/cpu-qom.h" is now fully target agnostic.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/i386/cpu.h | 6 ------
 hw/i386/microvm.c | 6 +++++-
 hw/i386/pc.c      | 6 +++++-
 3 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 862e4f1ff5..7c976971c7 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2243,12 +2243,6 @@ uint64_t cpu_get_tsc(CPUX86State *env);
 
 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
 
-#ifdef TARGET_X86_64
-#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
-#else
-#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
-#endif
-
 #define cpu_list x86_cpu_list
 
 /* MMU modes definitions */
diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
index b9c93039e2..281bf0c364 100644
--- a/hw/i386/microvm.c
+++ b/hw/i386/microvm.c
@@ -650,7 +650,11 @@ static void microvm_class_init(ObjectClass *oc, void *data)
     mc->has_hotpluggable_cpus = false;
     mc->auto_enable_numa_with_memhp = false;
     mc->auto_enable_numa_with_memdev = false;
-    mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
+#ifdef TARGET_X86_64
+    mc->default_cpu_type = X86_CPU_TYPE_NAME("qemu64");
+#else
+    mc->default_cpu_type = X86_CPU_TYPE_NAME("qemu32");
+#endif
     mc->nvdimm_supported = false;
     mc->default_ram_id = "microvm.ram";
 
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index aad7e8ccd1..2f7c0c1bdb 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1818,7 +1818,11 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
     hc->plug = pc_machine_device_plug_cb;
     hc->unplug_request = pc_machine_device_unplug_request_cb;
     hc->unplug = pc_machine_device_unplug_cb;
-    mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
+#ifdef TARGET_X86_64
+    mc->default_cpu_type = X86_CPU_TYPE_NAME("qemu64");
+#else
+    mc->default_cpu_type = X86_CPU_TYPE_NAME("qemu32");
+#endif
     mc->nvdimm_supported = true;
     mc->smp_props.dies_supported = true;
     mc->default_ram_id = "pc.ram";
-- 
2.41.0

[PATCH 10/18] target/riscv: Inline target specific TYPE_RISCV_CPU_BASE definition

[Philippe Mathieu-Daudé]

TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64
definitions which are target specific. Such target specific
definition taints "cpu-qom.h".

Since "cpu-qom.h" must be target agnostic, remove its target
specific definition uses by inlining TYPE_RISCV_CPU_BASE in the
two machines using it.

"target/riscv/cpu-qom.h" is now fully target agnostic.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/cpu-qom.h | 8 +-------
 hw/riscv/spike.c       | 8 +++++++-
 hw/riscv/virt.c        | 8 +++++++-
 3 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 8cb67b84a4..f607687384 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU RISC-V CPU QOM header
+ * QEMU RISC-V CPU QOM header (target agnostic)
  *
  * Copyright (c) 2023 Ventana Micro Systems Inc.
  *
@@ -43,12 +43,6 @@
 #define TYPE_RISCV_CPU_VEYRON_V1        RISCV_CPU_TYPE_NAME("veyron-v1")
 #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
 
-#if defined(TARGET_RISCV32)
-# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
-#elif defined(TARGET_RISCV64)
-# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
-#endif
-
 typedef struct CPUArchState CPURISCVState;
 
 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 81f7e53aed..eae49da6d6 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -349,7 +349,13 @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
     mc->init = spike_board_init;
     mc->max_cpus = SPIKE_CPUS_MAX;
     mc->is_default = true;
-    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
+#if defined(TARGET_RISCV32)
+    mc->default_cpu_type = TYPE_RISCV_CPU_BASE32;
+#elif defined(TARGET_RISCV64)
+    mc->default_cpu_type = TYPE_RISCV_CPU_BASE64;
+#else
+#error unsupported target
+#endif
     mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 5edc1d98d2..620a4e5f07 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1685,7 +1685,13 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->desc = "RISC-V VirtIO board";
     mc->init = virt_machine_init;
     mc->max_cpus = VIRT_CPUS_MAX;
-    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
+#if defined(TARGET_RISCV32)
+    mc->default_cpu_type = TYPE_RISCV_CPU_BASE32;
+#elif defined(TARGET_RISCV64)
+    mc->default_cpu_type = TYPE_RISCV_CPU_BASE64;
+#else
+#error unsupported target
+#endif
     mc->pci_allow_0_address = true;
     mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
-- 
2.41.0

[PATCH 11/18] target/i386: Declare CPU QOM types using DEFINE_TYPES() macro

[Philippe Mathieu-Daudé]

When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.

In few commits we are going to add more types, so replace
the type_register_static() to ease further reviews.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/i386/cpu.c | 50 ++++++++++++++++++++++-------------------------
 1 file changed, 23 insertions(+), 27 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 9fad31b8db..8f1fd5f304 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4989,13 +4989,6 @@ static void max_x86_cpu_initfn(Object *obj)
                             &error_abort);
 }
 
-static const TypeInfo max_x86_cpu_type_info = {
-    .name = X86_CPU_TYPE_NAME("max"),
-    .parent = TYPE_X86_CPU,
-    .instance_init = max_x86_cpu_initfn,
-    .class_init = max_x86_cpu_class_init,
-};
-
 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
 {
     assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
@@ -8017,19 +8010,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
     }
 }
 
-static const TypeInfo x86_cpu_type_info = {
-    .name = TYPE_X86_CPU,
-    .parent = TYPE_CPU,
-    .instance_size = sizeof(X86CPU),
-    .instance_align = __alignof(X86CPU),
-    .instance_init = x86_cpu_initfn,
-    .instance_post_init = x86_cpu_post_initfn,
-
-    .abstract = true,
-    .class_size = sizeof(X86CPUClass),
-    .class_init = x86_cpu_common_class_init,
-};
-
 /* "base" CPU model, used by query-cpu-model-expansion */
 static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
 {
@@ -8041,22 +8021,38 @@ static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
     xcc->ordering = 8;
 }
 
-static const TypeInfo x86_base_cpu_type_info = {
-        .name = X86_CPU_TYPE_NAME("base"),
-        .parent = TYPE_X86_CPU,
-        .class_init = x86_cpu_base_class_init,
+static const TypeInfo x86_cpu_types[] = {
+    {
+        .name           = TYPE_X86_CPU,
+        .parent         = TYPE_CPU,
+        .abstract       = true,
+        .instance_size  = sizeof(X86CPU),
+        .instance_align = __alignof(X86CPU),
+        .instance_init  = x86_cpu_initfn,
+        .instance_post_init = x86_cpu_post_initfn,
+        .class_size     = sizeof(X86CPUClass),
+        .class_init     = x86_cpu_common_class_init,
+    }, {
+        .name           = X86_CPU_TYPE_NAME("base"),
+        .parent         = TYPE_X86_CPU,
+        .class_init     = x86_cpu_base_class_init,
+    }, {
+        .name           = X86_CPU_TYPE_NAME("max"),
+        .parent         = TYPE_X86_CPU,
+        .instance_init  = max_x86_cpu_initfn,
+        .class_init     = max_x86_cpu_class_init,
+    }
 };
 
+DEFINE_TYPES(x86_cpu_types)
+
 static void x86_cpu_register_types(void)
 {
     int i;
 
-    type_register_static(&x86_cpu_type_info);
     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
         x86_register_cpudef_types(&builtin_x86_defs[i]);
     }
-    type_register_static(&max_x86_cpu_type_info);
-    type_register_static(&x86_base_cpu_type_info);
 }
 
 type_init(x86_cpu_register_types)
-- 
2.41.0

[PATCH 12/18] target/mips: Declare CPU QOM types using DEFINE_TYPES() macro

[Philippe Mathieu-Daudé]

When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.

In few commits we are going to add more types, so replace
the type_register_static() to ease further reviews.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/cpu.c | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index a0023edd43..83ee54f766 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -595,17 +595,21 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
 #endif /* CONFIG_TCG */
 }
 
-static const TypeInfo mips_cpu_type_info = {
-    .name = TYPE_MIPS_CPU,
-    .parent = TYPE_CPU,
-    .instance_size = sizeof(MIPSCPU),
-    .instance_align = __alignof(MIPSCPU),
-    .instance_init = mips_cpu_initfn,
-    .abstract = true,
-    .class_size = sizeof(MIPSCPUClass),
-    .class_init = mips_cpu_class_init,
+static const TypeInfo mips_cpu_types[] = {
+    {
+        .name           = TYPE_MIPS_CPU,
+        .parent         = TYPE_CPU,
+        .instance_size  = sizeof(MIPSCPU),
+        .instance_align = __alignof(MIPSCPU),
+        .instance_init  = mips_cpu_initfn,
+        .abstract       = true,
+        .class_size     = sizeof(MIPSCPUClass),
+        .class_init     = mips_cpu_class_init,
+    }
 };
 
+DEFINE_TYPES(mips_cpu_types)
+
 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
 {
     MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
@@ -630,7 +634,6 @@ static void mips_cpu_register_types(void)
 {
     int i;
 
-    type_register_static(&mips_cpu_type_info);
     for (i = 0; i < mips_defs_number; i++) {
         mips_register_cpudef_type(&mips_defs[i]);
     }
-- 
2.41.0

[PATCH 13/18] target/ppc: Declare CPU QOM types using DEFINE_TYPES() macro

[Philippe Mathieu-Daudé]

When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.

In few commits we are going to add more types, so replace
the type_register_static() to ease further reviews.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/ppc/cpu_init.c | 52 +++++++++++++++++++------------------------
 1 file changed, 23 insertions(+), 29 deletions(-)

diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 40fe14a6c2..055436c141 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7408,39 +7408,34 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
 #endif /* CONFIG_TCG */
 }
 
-static const TypeInfo ppc_cpu_type_info = {
-    .name = TYPE_POWERPC_CPU,
-    .parent = TYPE_CPU,
-    .instance_size = sizeof(PowerPCCPU),
-    .instance_align = __alignof__(PowerPCCPU),
-    .instance_init = ppc_cpu_instance_init,
-    .instance_finalize = ppc_cpu_instance_finalize,
-    .abstract = true,
-    .class_size = sizeof(PowerPCCPUClass),
-    .class_init = ppc_cpu_class_init,
+static const TypeInfo ppc_cpu_types[] = {
+    {
+        .name           = TYPE_POWERPC_CPU,
+        .parent         = TYPE_CPU,
+        .abstract       = true,
+        .instance_size  = sizeof(PowerPCCPU),
+        .instance_align = __alignof__(PowerPCCPU),
+        .instance_init  = ppc_cpu_instance_init,
+        .instance_finalize = ppc_cpu_instance_finalize,
+        .class_size     = sizeof(PowerPCCPUClass),
+        .class_init     = ppc_cpu_class_init,
 #ifndef CONFIG_USER_ONLY
-    .interfaces = (InterfaceInfo[]) {
-          { TYPE_INTERRUPT_STATS_PROVIDER },
-          { }
+        .interfaces     = (InterfaceInfo[]) {
+              { TYPE_INTERRUPT_STATS_PROVIDER },
+              { }
+        },
+#endif
+    },
+#ifndef CONFIG_USER_ONLY
+    {
+        .name           = TYPE_PPC_VIRTUAL_HYPERVISOR,
+        .parent         = TYPE_INTERFACE,
+        .class_size     = sizeof(PPCVirtualHypervisorClass),
     },
 #endif
 };
 
-#ifndef CONFIG_USER_ONLY
-static const TypeInfo ppc_vhyp_type_info = {
-    .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
-    .parent = TYPE_INTERFACE,
-    .class_size = sizeof(PPCVirtualHypervisorClass),
-};
-#endif
-
-static void ppc_cpu_register_types(void)
-{
-    type_register_static(&ppc_cpu_type_info);
-#ifndef CONFIG_USER_ONLY
-    type_register_static(&ppc_vhyp_type_info);
-#endif
-}
+DEFINE_TYPES(ppc_cpu_types)
 
 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 {
@@ -7635,4 +7630,3 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 #undef RGPL
 #undef RFPL
 }
-type_init(ppc_cpu_register_types)
-- 
2.41.0

[PATCH 14/18] target/sparc: Declare CPU QOM types using DEFINE_TYPES() macro

[Philippe Mathieu-Daudé]

When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.

In few commits we are going to add more types, so replace
the type_register_static() to ease further reviews.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/sparc/cpu.c | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 8ba96ae225..1e66413e94 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -924,17 +924,21 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
     cc->tcg_ops = &sparc_tcg_ops;
 }
 
-static const TypeInfo sparc_cpu_type_info = {
-    .name = TYPE_SPARC_CPU,
-    .parent = TYPE_CPU,
-    .instance_size = sizeof(SPARCCPU),
-    .instance_align = __alignof(SPARCCPU),
-    .instance_init = sparc_cpu_initfn,
-    .abstract = true,
-    .class_size = sizeof(SPARCCPUClass),
-    .class_init = sparc_cpu_class_init,
+static const TypeInfo sparc_cpu_types[] = {
+    {
+        .name           = TYPE_SPARC_CPU,
+        .parent         = TYPE_CPU,
+        .instance_size  = sizeof(SPARCCPU),
+        .instance_align = __alignof(SPARCCPU),
+        .instance_init  = sparc_cpu_initfn,
+        .abstract       = true,
+        .class_size     = sizeof(SPARCCPUClass),
+        .class_init     = sparc_cpu_class_init,
+    }
 };
 
+DEFINE_TYPES(sparc_cpu_types)
+
 static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data)
 {
     SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
@@ -959,7 +963,6 @@ static void sparc_cpu_register_types(void)
 {
     int i;
 
-    type_register_static(&sparc_cpu_type_info);
     for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
         sparc_register_cpudef_type(&sparc_defs[i]);
     }
-- 
2.41.0

[PATCH 15/18] cpus: Open code OBJECT_DECLARE_TYPE() in OBJECT_DECLARE_CPU_TYPE()

[Philippe Mathieu-Daudé]

Since the OBJECT_DECLARE_CPU_TYPE() macro uses the abstract ArchCPU
type, when declaring multiple CPUs of the same ArchCPU type we get
an error related to the indirect G_DEFINE_AUTOPTR_CLEANUP_FUNC()
use within OBJECT_DECLARE_TYPE():

  target/mips/cpu-qom.h:31:1: error: redefinition of 'glib_autoptr_clear_ArchCPU'
  OBJECT_DECLARE_CPU_TYPE(MIPS64CPU, MIPSCPUClass, MIPS64_CPU)
  ^
  include/hw/core/cpu.h:82:5: note: expanded from macro 'OBJECT_DECLARE_CPU_TYPE'
      OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
      ^
  include/qom/object.h:237:5: note: expanded from macro 'OBJECT_DECLARE_TYPE'
      G_DEFINE_AUTOPTR_CLEANUP_FUNC(InstanceType, object_unref) \
      ^
  /usr/include/glib-2.0/glib/gmacros.h:1371:3: note: expanded from macro 'G_DEFINE_AUTOPTR_CLEANUP_FUNC'
    _GLIB_DEFINE_AUTOPTR_CLEANUP_FUNCS(TypeName, TypeName, func)
    ^
  /usr/include/glib-2.0/glib/gmacros.h:1354:36: note: expanded from macro '_GLIB_DEFINE_AUTOPTR_CLEANUP_FUNCS'
    static G_GNUC_UNUSED inline void _GLIB_AUTOPTR_CLEAR_FUNC_NAME(TypeName) (TypeName *_ptr)                     \
                                     ^
  /usr/include/glib-2.0/glib/gmacros.h:1338:49: note: expanded from macro '_GLIB_AUTOPTR_CLEAR_FUNC_NAME'
  #define _GLIB_AUTOPTR_CLEAR_FUNC_NAME(TypeName) glib_autoptr_clear_##TypeName
                                                  ^
  <scratch space>:54:1: note: expanded from here
  glib_autoptr_clear_ArchCPU
  ^
  target/mips/cpu-qom.h:30:1: note: previous definition is here
  OBJECT_DECLARE_CPU_TYPE(MIPS32CPU, MIPSCPUClass, MIPS32_CPU)
  ^

Avoid that problem by expanding the OBJECT_DECLARE_TYPE() macro
within OBJECT_DECLARE_CPU_TYPE().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/core/cpu.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index e02bc5980f..ab724fab3a 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -79,7 +79,12 @@ DECLARE_CLASS_CHECKERS(CPUClass, CPU,
  */
 #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \
     typedef struct ArchCPU CpuInstanceType; \
-    OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
+    typedef struct CpuClassType CpuClassType; \
+    \
+    G_DEFINE_AUTOPTR_CLEANUP_FUNC(CpuInstanceType, object_unref) \
+    \
+    DECLARE_OBJ_CHECKERS(CpuInstanceType, CpuClassType, \
+                         CPU_MODULE_OBJ_NAME, TYPE_##CPU_MODULE_OBJ_NAME)
 
 typedef enum MMUAccessType {
     MMU_DATA_LOAD  = 0,
-- 
2.41.0

[PATCH 16/18] target/i386: Make X86_CPU common to new I386_CPU / X86_64_CPU types

[Philippe Mathieu-Daudé]

"target/foo/cpu-qom.h" can not use any target specific definitions.

Currently "target/i386/cpu-qom.h" defines TYPE_X86_CPU depending
on the i386/x86_64 build type. This doesn't scale in a heterogeneous
context where we need to access both types concurrently.

In order to do that, introduce the new I386_CPU / X86_64_CPU
types, both inheriting a common TYPE_X86_CPU base type.

Keep the current "base" and "max" CPU types as 32 or 64-bit,
depending on the binary built.

Adapt the cpu-plug-test, since the 'base' architecture is now
common to both 32/64-bit x86 targets.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/i386/cpu-qom.h       | 16 +++++++++-------
 target/i386/cpu.h           |  3 +++
 target/i386/cpu.c           | 20 ++++++++++++++++++--
 tests/qtest/cpu-plug-test.c |  2 +-
 4 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index 78207c0a7c..81f40bf91e 100644
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU x86 CPU
+ * QEMU x86 CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -24,13 +24,15 @@
 #include "qemu/notify.h"
 #include "qom/object.h"
 
-#ifdef TARGET_X86_64
-#define TYPE_X86_CPU "x86_64-cpu"
-#else
-#define TYPE_X86_CPU "i386-cpu"
-#endif
+#define TYPE_X86_CPU    "x86-cpu"
+#define TYPE_I386_CPU   "i386-cpu"
+#define TYPE_X86_64_CPU "x86_64-cpu"
 
-OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
+OBJECT_DECLARE_CPU_TYPE(I386CPU, X86CPUClass, I386_CPU)
+OBJECT_DECLARE_CPU_TYPE(X86_64CPU, X86CPUClass, X86_64_CPU)
+
+#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
+#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
 
 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 7c976971c7..5deb39a380 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -28,6 +28,9 @@
 #include "qemu/cpu-float.h"
 #include "qemu/timer.h"
 
+/* Abstract QOM X86 CPU, not exposed to other targets */
+OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
+
 #define XEN_NR_VIRQS 24
 
 /* The x86 has a strong memory model with some store-after-load re-ordering */
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8f1fd5f304..1b1dae92c6 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -8033,12 +8033,28 @@ static const TypeInfo x86_cpu_types[] = {
         .class_size     = sizeof(X86CPUClass),
         .class_init     = x86_cpu_common_class_init,
     }, {
-        .name           = X86_CPU_TYPE_NAME("base"),
+        .name           = TYPE_I386_CPU,
         .parent         = TYPE_X86_CPU,
+        .abstract       = true,
+    }, {
+        .name           = TYPE_X86_64_CPU,
+        .parent         = TYPE_X86_CPU,
+        .abstract       = true,
+    }, {
+        .name           = X86_CPU_TYPE_NAME("base"),
+#ifdef TARGET_X86_64
+        .parent         = TYPE_X86_64_CPU,
+#else
+        .parent         = TYPE_I386_CPU,
+#endif
         .class_init     = x86_cpu_base_class_init,
     }, {
         .name           = X86_CPU_TYPE_NAME("max"),
-        .parent         = TYPE_X86_CPU,
+#ifdef TARGET_X86_64
+        .parent         = TYPE_X86_64_CPU,
+#else
+        .parent         = TYPE_I386_CPU,
+#endif
         .instance_init  = max_x86_cpu_initfn,
         .class_init     = max_x86_cpu_class_init,
     }
diff --git a/tests/qtest/cpu-plug-test.c b/tests/qtest/cpu-plug-test.c
index 7f5dd5f85a..97316d131f 100644
--- a/tests/qtest/cpu-plug-test.c
+++ b/tests/qtest/cpu-plug-test.c
@@ -90,7 +90,7 @@ static void add_pc_test_case(const char *mname)
     data->machine = g_strdup(mname);
     data->cpu_model = "Haswell"; /* 1.3+ theoretically */
     data->device_model = g_strdup_printf("%s-%s-cpu", data->cpu_model,
-                                         qtest_get_arch());
+                                         qtest_get_base_arch());
     data->sockets = 1;
     data->cores = 3;
     data->threads = 2;
-- 
2.41.0

[PATCH 17/18] target/mips: Make MIPS_CPU common to new MIPS32_CPU / MIPS64_CPU types

[Philippe Mathieu-Daudé]

"target/foo/cpu-qom.h" can not use any target specific definitions.

Currently "target/mips/cpu-qom.h" defines TYPE_MIPS_CPU depending
on the mips(32)/mips64 build type. This doesn't scale in a
heterogeneous context where we need to access both types concurrently.

In order to do that, introduce the new MIPS32_CPU / MIPS64_CPU types,
both inheriting a common TYPE_MIPS_CPU base type.

Keep the current CPU types registered in mips_register_cpudef_type()
as 32 or 64-bit, but instead of depending on the binary built being
targeting 32/64-bit, check whether the CPU is 64-bit by looking at
the CPU_MIPS64 bit.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/cpu-qom.h | 13 ++++++-------
 target/mips/cpu.h     |  3 +++
 target/mips/cpu.c     | 11 ++++++++++-
 3 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 9c98ca1956..1a71509b5e 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU MIPS CPU
+ * QEMU MIPS CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -23,13 +23,12 @@
 #include "hw/core/cpu.h"
 #include "qom/object.h"
 
-#ifdef TARGET_MIPS64
-#define TYPE_MIPS_CPU "mips64-cpu"
-#else
-#define TYPE_MIPS_CPU "mips-cpu"
-#endif
+#define TYPE_MIPS_CPU   "mips-cpu"
+#define TYPE_MIPS32_CPU "mips32-cpu"
+#define TYPE_MIPS64_CPU "mips64-cpu"
 
-OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
+OBJECT_DECLARE_CPU_TYPE(MIPS32CPU, MIPSCPUClass, MIPS32_CPU)
+OBJECT_DECLARE_CPU_TYPE(MIPS64CPU, MIPSCPUClass, MIPS64_CPU)
 
 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 6b026e6bcf..3b6d0a7a8a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -10,6 +10,9 @@
 #include "hw/clock.h"
 #include "mips-defs.h"
 
+/* Abstract QOM MIPS CPU, not exposed to other targets */
+OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
+
 #define TCG_GUEST_DEFAULT_MO (0)
 
 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 83ee54f766..f43300dd5e 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -605,6 +605,14 @@ static const TypeInfo mips_cpu_types[] = {
         .abstract       = true,
         .class_size     = sizeof(MIPSCPUClass),
         .class_init     = mips_cpu_class_init,
+    }, {
+        .name           = TYPE_MIPS32_CPU,
+        .parent         = TYPE_MIPS_CPU,
+        .abstract       = true,
+    }, {
+        .name           = TYPE_MIPS64_CPU,
+        .parent         = TYPE_MIPS_CPU,
+        .abstract       = true,
     }
 };
 
@@ -621,7 +629,8 @@ static void mips_register_cpudef_type(const struct mips_def_t *def)
     char *typename = mips_cpu_type_name(def->name);
     TypeInfo ti = {
         .name = typename,
-        .parent = TYPE_MIPS_CPU,
+        .parent = def->insn_flags & CPU_MIPS64
+                  ? TYPE_MIPS64_CPU : TYPE_MIPS32_CPU,
         .class_init = mips_cpu_cpudef_class_init,
         .class_data = (void *)def,
     };
-- 
2.41.0

[PATCH 18/18] target/sparc: Make SPARC_CPU common to new SPARC32_CPU/SPARC64_CPU types

[Philippe Mathieu-Daudé]

"target/foo/cpu-qom.h" can not use any target specific definitions.

Currently "target/sparc/cpu-qom.h" defines TYPE_SPARC_CPU
depending on the sparc(32)/sparc64 build type. This doesn't
scale in a heterogeneous context where we need to access both
types concurrently.

In order to do that, introduce the new SPARC32_CPU / SPARC64_CPU
types, both inheriting a common TYPE_SPARC_CPU base type.

Keep the current CPU types registered in sparc_register_cpudef_type()
as 32 or 64-bit, depending on the binary built.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/sparc/cpu-qom.h |  9 ++++-----
 target/sparc/cpu.h     |  3 +++
 target/sparc/cpu.c     | 12 +++++++++++-
 3 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
index 86b24a254a..d08fbd4ddc 100644
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@@ -23,13 +23,12 @@
 #include "hw/core/cpu.h"
 #include "qom/object.h"
 
-#ifdef TARGET_SPARC64
-#define TYPE_SPARC_CPU "sparc64-cpu"
-#else
 #define TYPE_SPARC_CPU "sparc-cpu"
-#endif
+#define TYPE_SPARC32_CPU "sparc32-cpu"
+#define TYPE_SPARC64_CPU "sparc64-cpu"
 
-OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
+OBJECT_DECLARE_CPU_TYPE(SPARC32CPU, SPARCCPUClass, SPARC32_CPU)
+OBJECT_DECLARE_CPU_TYPE(SPARC64CPU, SPARCCPUClass, SPARC64_CPU)
 
 #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
 #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 924e83b9ce..0f94e5a442 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -12,6 +12,9 @@
 #define TARGET_DPREGS 32
 #endif
 
+/* Abstract QOM SPARC CPU, not exposed to other targets */
+OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
+
 /*#define EXCP_INTERRUPT 0x100*/
 
 /* Windowed register indexes.  */
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 1e66413e94..7d060ba488 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -934,6 +934,12 @@ static const TypeInfo sparc_cpu_types[] = {
         .abstract       = true,
         .class_size     = sizeof(SPARCCPUClass),
         .class_init     = sparc_cpu_class_init,
+    }, {
+        .name           = TYPE_SPARC32_CPU,
+        .parent         = TYPE_SPARC_CPU,
+    }, {
+        .name           = TYPE_SPARC64_CPU,
+        .parent         = TYPE_SPARC_CPU,
     }
 };
 
@@ -950,7 +956,11 @@ static void sparc_register_cpudef_type(const struct sparc_def_t *def)
     char *typename = sparc_cpu_type_name(def->name);
     TypeInfo ti = {
         .name = typename,
-        .parent = TYPE_SPARC_CPU,
+#ifdef TARGET_SPARC64
+        .parent = TYPE_SPARC64_CPU,
+#else
+        .parent = TYPE_SPARC32_CPU,
+#endif
         .class_init = sparc_cpu_cpudef_class_init,
         .class_data = (void *)def,
     };
-- 
2.41.0

Re: [PATCH 10/18] target/riscv: Inline target specific TYPE_RISCV_CPU_BASE definition

[LIU Zhiwei]

On 2023/10/10 17:28, Philippe Mathieu-Daudé wrote:
> TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64
> definitions which are target specific. Such target specific
> definition taints "cpu-qom.h".
>
> Since "cpu-qom.h" must be target agnostic, remove its target
> specific definition uses by inlining TYPE_RISCV_CPU_BASE in the
> two machines using it.
>
> "target/riscv/cpu-qom.h" is now fully target agnostic.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/riscv/cpu-qom.h | 8 +-------
>   hw/riscv/spike.c       | 8 +++++++-
>   hw/riscv/virt.c        | 8 +++++++-
>   3 files changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 8cb67b84a4..f607687384 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -1,5 +1,5 @@
>   /*
> - * QEMU RISC-V CPU QOM header
> + * QEMU RISC-V CPU QOM header (target agnostic)
>    *
>    * Copyright (c) 2023 Ventana Micro Systems Inc.
>    *
> @@ -43,12 +43,6 @@
>   #define TYPE_RISCV_CPU_VEYRON_V1        RISCV_CPU_TYPE_NAME("veyron-v1")
>   #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
>   
> -#if defined(TARGET_RISCV32)
> -# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
> -#elif defined(TARGET_RISCV64)
> -# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
> -#endif
> -
>   typedef struct CPUArchState CPURISCVState;
>   
>   OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 81f7e53aed..eae49da6d6 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -349,7 +349,13 @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
>       mc->init = spike_board_init;
>       mc->max_cpus = SPIKE_CPUS_MAX;
>       mc->is_default = true;
> -    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
> +#if defined(TARGET_RISCV32)
> +    mc->default_cpu_type = TYPE_RISCV_CPU_BASE32;
> +#elif defined(TARGET_RISCV64)
> +    mc->default_cpu_type = TYPE_RISCV_CPU_BASE64;
> +#else
> +#error unsupported target
> +#endif
>       mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
>       mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
>       mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 5edc1d98d2..620a4e5f07 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -1685,7 +1685,13 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
>       mc->desc = "RISC-V VirtIO board";
>       mc->init = virt_machine_init;
>       mc->max_cpus = VIRT_CPUS_MAX;
> -    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
> +#if defined(TARGET_RISCV32)
> +    mc->default_cpu_type = TYPE_RISCV_CPU_BASE32;
> +#elif defined(TARGET_RISCV64)
> +    mc->default_cpu_type = TYPE_RISCV_CPU_BASE64;
> +#else
> +#error unsupported target
> +#endif

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Zhiwei

>       mc->pci_allow_0_address = true;
>       mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
>       mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;

Re: [PATCH 06/18] target/loongarch: Declare QOM definitions in 'cpu-qom.h'

[gaosong]

在 2023/10/10 下午5:28, Philippe Mathieu-Daudé 写道:
> "target/foo/cpu.h" contains the target specific declarations.
> 
> A heterogeneous setup need to access target agnostic declarations
> (at least the QOM ones, to instantiate the objects).
> 
> Our convention is to add such target agnostic QOM declarations in
> the "target/foo/cpu-qom.h" header.
> 
> Extract QOM definitions from "cpu.h" to "cpu-qom.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/loongarch/cpu-qom.h | 38 ++++++++++++++++++++++++++++++++++++++
>   target/loongarch/cpu.h     | 26 +-------------------------
>   2 files changed, 39 insertions(+), 25 deletions(-)
>   create mode 100644 target/loongarch/cpu-qom.h
> 
Reviewed-by: Song Gao <gaosong@loongson.cn>

Thanks.
Song Gao

> diff --git a/target/loongarch/cpu-qom.h b/target/loongarch/cpu-qom.h
> new file mode 100644
> index 0000000000..d577af9f6e
> --- /dev/null
> +++ b/target/loongarch/cpu-qom.h
> @@ -0,0 +1,38 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * QEMU LoongArch CPU QOM header (target agnostic)
> + *
> + * Copyright (c) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#ifndef LOONGARCH_CPU_QOM_H
> +#define LOONGARCH_CPU_QOM_H
> +
> +#include "hw/core/cpu.h"
> +#include "qom/object.h"
> +
> +#define TYPE_LOONGARCH_CPU "loongarch-cpu"
> +#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
> +#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
> +
> +OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
> +                        LOONGARCH_CPU)
> +
> +#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
> +#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
> +
> +/**
> + * LoongArchCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + *
> + * A LoongArch CPU model.
> + */
> +struct LoongArchCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +};
> +
> +#endif
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index 40e70a8119..22cebc6280 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -17,6 +17,7 @@
>   #include "exec/memory.h"
>   #endif
>   #include "cpu-csr.h"
> +#include "cpu-qom.h"
>   
>   #define IOCSRF_TEMP             0
>   #define IOCSRF_NODECNT          1
> @@ -383,29 +384,6 @@ struct ArchCPU {
>       const char *dtb_compatible;
>   };
>   
> -#define TYPE_LOONGARCH_CPU "loongarch-cpu"
> -#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
> -#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
> -
> -OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
> -                        LOONGARCH_CPU)
> -
> -/**
> - * LoongArchCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - *
> - * A LoongArch CPU model.
> - */
> -struct LoongArchCPUClass {
> -    /*< private >*/
> -    CPUClass parent_class;
> -    /*< public >*/
> -
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -};
> -
>   /*
>    * LoongArch CPUs has 4 privilege levels.
>    * 0 for kernel mode, 3 for user mode.
> @@ -482,8 +460,6 @@ void loongarch_cpu_list(void);
>   
>   #include "exec/cpu-all.h"
>   
> -#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
> -#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
>   #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
>   
>   #endif /* LOONGARCH_CPU_H */
> 

Re: [PATCH 03/18] target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'

[LIU Zhiwei]

On 2023/10/10 17:28, Philippe Mathieu-Daudé wrote:
> CPU_RESOLVING_TYPE is a per-target definition, and is
> irrelevant for other targets. Move it to "cpu.h".
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/riscv/cpu-qom.h | 1 -
>   target/riscv/cpu.h     | 2 ++
>   2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 04af50983e..8cb67b84a4 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -27,7 +27,6 @@
>   
>   #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
>   #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
> -#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
>   
>   #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
>   #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index ef9cf21c0c..374b813f20 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -31,6 +31,8 @@
>   #include "qapi/qapi-types-common.h"
>   #include "cpu-qom.h"
>   
> +#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Zhiwei

> +
>   #define TCG_GUEST_DEFAULT_MO 0
>   
>   /*

Re: [PATCH 10/18] target/riscv: Inline target specific TYPE_RISCV_CPU_BASE definition

[Alistair Francis]

On Tue, Oct 10, 2023 at 7:32 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64
> definitions which are target specific. Such target specific
> definition taints "cpu-qom.h".
>
> Since "cpu-qom.h" must be target agnostic, remove its target
> specific definition uses by inlining TYPE_RISCV_CPU_BASE in the
> two machines using it.
>
> "target/riscv/cpu-qom.h" is now fully target agnostic.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu-qom.h | 8 +-------
>  hw/riscv/spike.c       | 8 +++++++-
>  hw/riscv/virt.c        | 8 +++++++-
>  3 files changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 8cb67b84a4..f607687384 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -1,5 +1,5 @@
>  /*
> - * QEMU RISC-V CPU QOM header
> + * QEMU RISC-V CPU QOM header (target agnostic)
>   *
>   * Copyright (c) 2023 Ventana Micro Systems Inc.
>   *
> @@ -43,12 +43,6 @@
>  #define TYPE_RISCV_CPU_VEYRON_V1        RISCV_CPU_TYPE_NAME("veyron-v1")
>  #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
>
> -#if defined(TARGET_RISCV32)
> -# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
> -#elif defined(TARGET_RISCV64)
> -# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
> -#endif
> -
>  typedef struct CPUArchState CPURISCVState;
>
>  OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 81f7e53aed..eae49da6d6 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -349,7 +349,13 @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
>      mc->init = spike_board_init;
>      mc->max_cpus = SPIKE_CPUS_MAX;
>      mc->is_default = true;
> -    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
> +#if defined(TARGET_RISCV32)
> +    mc->default_cpu_type = TYPE_RISCV_CPU_BASE32;
> +#elif defined(TARGET_RISCV64)
> +    mc->default_cpu_type = TYPE_RISCV_CPU_BASE64;
> +#else
> +#error unsupported target
> +#endif
>      mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
>      mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
>      mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 5edc1d98d2..620a4e5f07 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -1685,7 +1685,13 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
>      mc->desc = "RISC-V VirtIO board";
>      mc->init = virt_machine_init;
>      mc->max_cpus = VIRT_CPUS_MAX;
> -    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
> +#if defined(TARGET_RISCV32)
> +    mc->default_cpu_type = TYPE_RISCV_CPU_BASE32;
> +#elif defined(TARGET_RISCV64)
> +    mc->default_cpu_type = TYPE_RISCV_CPU_BASE64;
> +#else
> +#error unsupported target
> +#endif
>      mc->pci_allow_0_address = true;
>      mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
>      mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
> --
> 2.41.0
>
>

Re: [PATCH 04/18] target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'

[LIU Zhiwei]

On 2023/10/10 17:28, Philippe Mathieu-Daudé wrote:
> Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME()
> macro to resolve target CPU types.

Hi Philippe,

I don't understand why should we use FOO_CPU_TYPE_NAME macro to resolve 
target CPU types? In my opinion, we should pass the
CPU typename from command line for heterogeneous case.

Could you make it clearer how should we use FOO_CPU_TYPE_NAME macro to 
resolve target CPU types in heterogeneous case?

Thanks,
Zhiwei

> Move the declaration
> (along with the required FOO_CPU_TYPE_SUFFIX) to "cpu-qom.h".
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/alpha/cpu-qom.h   | 5 ++++-
>   target/alpha/cpu.h       | 2 --
>   target/avr/cpu-qom.h     | 5 ++++-
>   target/avr/cpu.h         | 2 --
>   target/cris/cpu-qom.h    | 5 ++++-
>   target/cris/cpu.h        | 2 --
>   target/i386/cpu-qom.h    | 3 +++
>   target/i386/cpu.h        | 2 --
>   target/m68k/cpu-qom.h    | 5 ++++-
>   target/m68k/cpu.h        | 2 --
>   target/mips/cpu-qom.h    | 3 +++
>   target/mips/cpu.h        | 2 --
>   target/rx/cpu-qom.h      | 5 ++++-
>   target/rx/cpu.h          | 2 --
>   target/s390x/cpu-qom.h   | 5 ++++-
>   target/s390x/cpu.h       | 2 --
>   target/sh4/cpu-qom.h     | 5 ++++-
>   target/sh4/cpu.h         | 2 --
>   target/sparc/cpu-qom.h   | 5 ++++-
>   target/sparc/cpu.h       | 2 --
>   target/tricore/cpu-qom.h | 5 +++++
>   target/tricore/cpu.h     | 2 --
>   target/xtensa/cpu-qom.h  | 5 ++++-
>   target/xtensa/cpu.h      | 2 --
>   24 files changed, 47 insertions(+), 33 deletions(-)
>
> diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
> index 1f200724b6..d596d1b69f 100644
> --- a/target/alpha/cpu-qom.h
> +++ b/target/alpha/cpu-qom.h
> @@ -1,5 +1,5 @@
>   /*
> - * QEMU Alpha CPU
> + * QEMU Alpha CPU QOM header (target agnostic)
>    *
>    * Copyright (c) 2012 SUSE LINUX Products GmbH
>    *
> @@ -27,6 +27,9 @@
>   
>   OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
>   
> +#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
> +#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
> +
>   /**
>    * AlphaCPUClass:
>    * @parent_realize: The parent class' realize handler.
> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
> index e2a467ec17..ba0d9e3468 100644
> --- a/target/alpha/cpu.h
> +++ b/target/alpha/cpu.h
> @@ -428,8 +428,6 @@ enum {
>   
>   void alpha_translate_init(void);
>   
> -#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
> -#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
>   #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
>   
>   void alpha_cpu_list(void);
> diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
> index 01ea5f160b..a810d6dc09 100644
> --- a/target/avr/cpu-qom.h
> +++ b/target/avr/cpu-qom.h
> @@ -1,5 +1,5 @@
>   /*
> - * QEMU AVR CPU
> + * QEMU AVR CPU QOM header (target agnostic)
>    *
>    * Copyright (c) 2016-2020 Michael Rolnik
>    *
> @@ -28,6 +28,9 @@
>   
>   OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
>   
> +#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
> +#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
> +
>   /**
>    *  AVRCPUClass:
>    *  @parent_realize: The parent class' realize handler.
> diff --git a/target/avr/cpu.h b/target/avr/cpu.h
> index 4ce22d8e4f..d3f0cc65d4 100644
> --- a/target/avr/cpu.h
> +++ b/target/avr/cpu.h
> @@ -28,8 +28,6 @@
>   #error "AVR 8-bit does not support user mode"
>   #endif
>   
> -#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
> -#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
>   #define CPU_RESOLVING_TYPE TYPE_AVR_CPU
>   
>   #define TCG_GUEST_DEFAULT_MO 0
> diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h
> index 431a1d536a..02a5b589b8 100644
> --- a/target/cris/cpu-qom.h
> +++ b/target/cris/cpu-qom.h
> @@ -1,5 +1,5 @@
>   /*
> - * QEMU CRIS CPU
> + * QEMU CRIS CPU QOM header (target agnostic)
>    *
>    * Copyright (c) 2012 SUSE LINUX Products GmbH
>    *
> @@ -27,6 +27,9 @@
>   
>   OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
>   
> +#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
> +#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
> +
>   /**
>    * CRISCPUClass:
>    * @parent_realize: The parent class' realize handler.
> diff --git a/target/cris/cpu.h b/target/cris/cpu.h
> index 676b8e93ca..1af7ae5ef9 100644
> --- a/target/cris/cpu.h
> +++ b/target/cris/cpu.h
> @@ -242,8 +242,6 @@ enum {
>   /* CRIS uses 8k pages.  */
>   #define MMAP_SHIFT TARGET_PAGE_BITS
>   
> -#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
> -#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
>   #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
>   
>   /* MMU modes definitions */
> diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
> index 2350f4ae60..78207c0a7c 100644
> --- a/target/i386/cpu-qom.h
> +++ b/target/i386/cpu-qom.h
> @@ -32,6 +32,9 @@
>   
>   OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
>   
> +#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
> +#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
> +
>   typedef struct X86CPUModel X86CPUModel;
>   
>   /**
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index e1875466b9..862e4f1ff5 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -2241,8 +2241,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
>   /* hw/pc.c */
>   uint64_t cpu_get_tsc(CPUX86State *env);
>   
> -#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
> -#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
>   #define CPU_RESOLVING_TYPE TYPE_X86_CPU
>   
>   #ifdef TARGET_X86_64
> diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
> index 0ec7750a92..7192ecd71f 100644
> --- a/target/m68k/cpu-qom.h
> +++ b/target/m68k/cpu-qom.h
> @@ -1,5 +1,5 @@
>   /*
> - * QEMU Motorola 68k CPU
> + * QEMU Motorola 68k CPU QOM header (target agnostic)
>    *
>    * Copyright (c) 2012 SUSE LINUX Products GmbH
>    *
> @@ -27,6 +27,9 @@
>   
>   OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
>   
> +#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
> +#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
> +
>   /*
>    * M68kCPUClass:
>    * @parent_realize: The parent class' realize handler.
> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
> index 20afb0c94d..ae144ebc2f 100644
> --- a/target/m68k/cpu.h
> +++ b/target/m68k/cpu.h
> @@ -563,8 +563,6 @@ enum {
>       ACCESS_DATA  = 0x20, /* Data load/store access        */
>   };
>   
> -#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
> -#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
>   #define CPU_RESOLVING_TYPE TYPE_M68K_CPU
>   
>   #define cpu_list m68k_cpu_list
> diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
> index 0dffab453b..9c98ca1956 100644
> --- a/target/mips/cpu-qom.h
> +++ b/target/mips/cpu-qom.h
> @@ -31,6 +31,9 @@
>   
>   OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
>   
> +#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
> +#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
> +
>   /**
>    * MIPSCPUClass:
>    * @parent_realize: The parent class' realize handler.
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 5fddceff3a..6b026e6bcf 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1303,8 +1303,6 @@ enum {
>    */
>   #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
>   
> -#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
> -#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
>   #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
>   
>   bool cpu_type_supports_cps_smp(const char *cpu_type);
> diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
> index 1c8466a187..99fe771534 100644
> --- a/target/rx/cpu-qom.h
> +++ b/target/rx/cpu-qom.h
> @@ -1,5 +1,5 @@
>   /*
> - * RX CPU
> + * QEMU RX CPU QOM header (target agnostic)
>    *
>    * Copyright (c) 2019 Yoshinori Sato
>    *
> @@ -28,6 +28,9 @@
>   
>   OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
>   
> +#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
> +#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
> +
>   /*
>    * RXCPUClass:
>    * @parent_realize: The parent class' realize handler.
> diff --git a/target/rx/cpu.h b/target/rx/cpu.h
> index f66754eb8a..f89d88a37f 100644
> --- a/target/rx/cpu.h
> +++ b/target/rx/cpu.h
> @@ -114,8 +114,6 @@ struct ArchCPU {
>       CPURXState env;
>   };
>   
> -#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
> -#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
>   #define CPU_RESOLVING_TYPE TYPE_RX_CPU
>   
>   const char *rx_crname(uint8_t cr);
> diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
> index 00cae2b131..463fe16386 100644
> --- a/target/s390x/cpu-qom.h
> +++ b/target/s390x/cpu-qom.h
> @@ -1,5 +1,5 @@
>   /*
> - * QEMU S/390 CPU
> + * QEMU S/390 CPU QOM header (target agnostic)
>    *
>    * Copyright (c) 2012 SUSE LINUX Products GmbH
>    *
> @@ -27,6 +27,9 @@
>   
>   OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU)
>   
> +#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
> +#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
> +
>   typedef struct S390CPUModel S390CPUModel;
>   typedef struct S390CPUDef S390CPUDef;
>   
> diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
> index 7bea7075e1..3e161862e5 100644
> --- a/target/s390x/cpu.h
> +++ b/target/s390x/cpu.h
> @@ -810,8 +810,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
>   
>   
>   /* helper.c */
> -#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
> -#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
>   #define CPU_RESOLVING_TYPE TYPE_S390_CPU
>   
>   /* interrupt.c */
> diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
> index 89785a90f0..ed2de98949 100644
> --- a/target/sh4/cpu-qom.h
> +++ b/target/sh4/cpu-qom.h
> @@ -1,5 +1,5 @@
>   /*
> - * QEMU SuperH CPU
> + * QEMU SuperH CPU QOM header (target agnostic)
>    *
>    * Copyright (c) 2012 SUSE LINUX Products GmbH
>    *
> @@ -31,6 +31,9 @@
>   
>   OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
>   
> +#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
> +#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
> +
>   /**
>    * SuperHCPUClass:
>    * @parent_realize: The parent class' realize handler.
> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
> index f75a235973..f44b3e5b25 100644
> --- a/target/sh4/cpu.h
> +++ b/target/sh4/cpu.h
> @@ -252,8 +252,6 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
>   
>   void cpu_load_tlb(CPUSH4State * env);
>   
> -#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
> -#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
>   #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU
>   
>   #define cpu_list sh4_cpu_list
> diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
> index 78bf00b9a2..86b24a254a 100644
> --- a/target/sparc/cpu-qom.h
> +++ b/target/sparc/cpu-qom.h
> @@ -1,5 +1,5 @@
>   /*
> - * QEMU SPARC CPU
> + * QEMU SPARC CPU QOM header (target agnostic)
>    *
>    * Copyright (c) 2012 SUSE LINUX Products GmbH
>    *
> @@ -31,6 +31,9 @@
>   
>   OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
>   
> +#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
> +#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
> +
>   typedef struct sparc_def_t sparc_def_t;
>   /**
>    * SPARCCPUClass:
> diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
> index b3a98f1d74..924e83b9ce 100644
> --- a/target/sparc/cpu.h
> +++ b/target/sparc/cpu.h
> @@ -650,8 +650,6 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
>   #endif
>   #endif
>   
> -#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
> -#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
>   #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU
>   
>   #define cpu_list sparc_cpu_list
> diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h
> index 612731daa0..5368689bd9 100644
> --- a/target/tricore/cpu-qom.h
> +++ b/target/tricore/cpu-qom.h
> @@ -1,4 +1,6 @@
>   /*
> + * QEMU TriCore CPU QOM header (target agnostic)
> + *
>    *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
>    *
>    * This library is free software; you can redistribute it and/or
> @@ -26,6 +28,9 @@
>   
>   OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)
>   
> +#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
> +#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
> +
>   struct TriCoreCPUClass {
>       /*< private >*/
>       CPUClass parent_class;
> diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
> index a357b573f2..fc09590a4f 100644
> --- a/target/tricore/cpu.h
> +++ b/target/tricore/cpu.h
> @@ -270,8 +270,6 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc,
>       *flags = new_flags;
>   }
>   
> -#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
> -#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
>   #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU
>   
>   /* helpers.c */
> diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h
> index 419c7d8e4a..710ffa0403 100644
> --- a/target/xtensa/cpu-qom.h
> +++ b/target/xtensa/cpu-qom.h
> @@ -1,5 +1,5 @@
>   /*
> - * QEMU Xtensa CPU
> + * QEMU Xtensa CPU QOM header (target agnostic)
>    *
>    * Copyright (c) 2012 SUSE LINUX Products GmbH
>    * All rights reserved.
> @@ -36,6 +36,9 @@
>   
>   OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU)
>   
> +#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
> +#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
> +
>   typedef struct XtensaConfig XtensaConfig;
>   
>   /**
> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> index c6bbef1e5d..20ea6826e4 100644
> --- a/target/xtensa/cpu.h
> +++ b/target/xtensa/cpu.h
> @@ -588,8 +588,6 @@ G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
>   
>   #define cpu_list xtensa_cpu_list
>   
> -#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
> -#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
>   #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
>   
>   #if TARGET_BIG_ENDIAN

Re: [PATCH 04/18] target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'

[Philippe Mathieu-Daudé]

Hi Zhiwei,

On 11/10/23 04:51, LIU Zhiwei wrote:
> 
> On 2023/10/10 17:28, Philippe Mathieu-Daudé wrote:
>> Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME()
>> macro to resolve target CPU types.
> 
> Hi Philippe,
> 
> I don't understand why should we use FOO_CPU_TYPE_NAME macro to resolve 
> target CPU types? In my opinion, we should pass the
> CPU typename from command line for heterogeneous case.
> 
> Could you make it clearer how should we use FOO_CPU_TYPE_NAME macro to 
> resolve target CPU types in heterogeneous case?

To be honest I start to feel a bit lost with the "cpu
resolving type" design.

We are not quite there yet to "create from command line"
or "create from QMP", so I'm prototyping in plain C.
One of my test is:

   #include "target/arm/cpu-qom.h"
   #include "target/hexagon/cpu-qom.h"
   ...

   static void
   my_machine3_init((MachineState *machine)
   {
     CPUState cpu[2];
     ...

     cpu[0] = CPU(object_new(ARM_CPU_TYPE_NAME("cortex-a72")));
     cpu[1] = CPU(object_new(HEXAGON_CPU_TYPE_NAME("v68")));
     ...
   }

The machine code need access to the per-target
FOO_CPU_TYPE_NAME() macros. I'm not sure what each macro
expands to is considered stable, so IIUC I can't inline and use:

     cpu[0] = CPU(object_new("cortex-a72-arm-cpu"));
     cpu[1] = CPU(object_new("v68"-hexagon-cpu));

That said, maybe I'm mistaken.

Kinda related discussion with Gavin/Igor:
https://lore.kernel.org/qemu-devel/35653f53-a977-02ea-28f6-6fe85b1efd5a@redhat.com/
(related to 
https://lore.kernel.org/qemu-devel/20230907003553.1636896-1-gshan@redhat.com/).

> 
> Thanks,
> Zhiwei
> 
>> Move the declaration
>> (along with the required FOO_CPU_TYPE_SUFFIX) to "cpu-qom.h".
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   target/alpha/cpu-qom.h   | 5 ++++-
>>   target/alpha/cpu.h       | 2 --
>>   target/avr/cpu-qom.h     | 5 ++++-
>>   target/avr/cpu.h         | 2 --
>>   target/cris/cpu-qom.h    | 5 ++++-
>>   target/cris/cpu.h        | 2 --
>>   target/i386/cpu-qom.h    | 3 +++
>>   target/i386/cpu.h        | 2 --
>>   target/m68k/cpu-qom.h    | 5 ++++-
>>   target/m68k/cpu.h        | 2 --
>>   target/mips/cpu-qom.h    | 3 +++
>>   target/mips/cpu.h        | 2 --
>>   target/rx/cpu-qom.h      | 5 ++++-
>>   target/rx/cpu.h          | 2 --
>>   target/s390x/cpu-qom.h   | 5 ++++-
>>   target/s390x/cpu.h       | 2 --
>>   target/sh4/cpu-qom.h     | 5 ++++-
>>   target/sh4/cpu.h         | 2 --
>>   target/sparc/cpu-qom.h   | 5 ++++-
>>   target/sparc/cpu.h       | 2 --
>>   target/tricore/cpu-qom.h | 5 +++++
>>   target/tricore/cpu.h     | 2 --
>>   target/xtensa/cpu-qom.h  | 5 ++++-
>>   target/xtensa/cpu.h      | 2 --
>>   24 files changed, 47 insertions(+), 33 deletions(-)
>>
>> diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
>> index 1f200724b6..d596d1b69f 100644
>> --- a/target/alpha/cpu-qom.h
>> +++ b/target/alpha/cpu-qom.h
>> @@ -1,5 +1,5 @@
>>   /*
>> - * QEMU Alpha CPU
>> + * QEMU Alpha CPU QOM header (target agnostic)
>>    *
>>    * Copyright (c) 2012 SUSE LINUX Products GmbH
>>    *
>> @@ -27,6 +27,9 @@
>>   OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
>> +#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
>> +#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
>> +
>>   /**
>>    * AlphaCPUClass:
>>    * @parent_realize: The parent class' realize handler.
>> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
>> index e2a467ec17..ba0d9e3468 100644
>> --- a/target/alpha/cpu.h
>> +++ b/target/alpha/cpu.h
>> @@ -428,8 +428,6 @@ enum {
>>   void alpha_translate_init(void);
>> -#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
>> -#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
>>   #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
>>   void alpha_cpu_list(void);
[...]

Re: [PATCH 04/18] target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'

[LIU Zhiwei]

On 2023/10/11 11:21, Philippe Mathieu-Daudé wrote:
> Hi Zhiwei,
>
> On 11/10/23 04:51, LIU Zhiwei wrote:
>>
>> On 2023/10/10 17:28, Philippe Mathieu-Daudé wrote:
>>> Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME()
>>> macro to resolve target CPU types.
>>
>> Hi Philippe,
>>
>> I don't understand why should we use FOO_CPU_TYPE_NAME macro to 
>> resolve target CPU types? In my opinion, we should pass the
>> CPU typename from command line for heterogeneous case.
>>
>> Could you make it clearer how should we use FOO_CPU_TYPE_NAME macro 
>> to resolve target CPU types in heterogeneous case?
>
> To be honest I start to feel a bit lost with the "cpu
> resolving type" design.
>
> We are not quite there yet to "create from command line"
> or "create from QMP", so I'm prototyping in plain C.
> One of my test is:
>
>   #include "target/arm/cpu-qom.h"
>   #include "target/hexagon/cpu-qom.h"
>   ...
>
>   static void
>   my_machine3_init((MachineState *machine)
>   {
>     CPUState cpu[2];
>     ...
>
>     cpu[0] = CPU(object_new(ARM_CPU_TYPE_NAME("cortex-a72")));
>     cpu[1] = CPU(object_new(HEXAGON_CPU_TYPE_NAME("v68")));
>     ...
>   }
>
> The machine code need access to the per-target
> FOO_CPU_TYPE_NAME() macros. 

I see what you mean. It works if we will pass the cpu model instead of 
cpu typename to the machine state(Not yet).

Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Zhiwei

> I'm not sure what each macro
> expands to is considered stable, so IIUC I can't inline and use:
>
>     cpu[0] = CPU(object_new("cortex-a72-arm-cpu"));
>     cpu[1] = CPU(object_new("v68"-hexagon-cpu));
>
> That said, maybe I'm mistaken.
>
> Kinda related discussion with Gavin/Igor:
> https://lore.kernel.org/qemu-devel/35653f53-a977-02ea-28f6-6fe85b1efd5a@redhat.com/ 
>
> (related to 
> https://lore.kernel.org/qemu-devel/20230907003553.1636896-1-gshan@redhat.com/).
>
>>
>> Thanks,
>> Zhiwei
>>
>>> Move the declaration
>>> (along with the required FOO_CPU_TYPE_SUFFIX) to "cpu-qom.h".
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>> ---
>>>   target/alpha/cpu-qom.h   | 5 ++++-
>>>   target/alpha/cpu.h       | 2 --
>>>   target/avr/cpu-qom.h     | 5 ++++-
>>>   target/avr/cpu.h         | 2 --
>>>   target/cris/cpu-qom.h    | 5 ++++-
>>>   target/cris/cpu.h        | 2 --
>>>   target/i386/cpu-qom.h    | 3 +++
>>>   target/i386/cpu.h        | 2 --
>>>   target/m68k/cpu-qom.h    | 5 ++++-
>>>   target/m68k/cpu.h        | 2 --
>>>   target/mips/cpu-qom.h    | 3 +++
>>>   target/mips/cpu.h        | 2 --
>>>   target/rx/cpu-qom.h      | 5 ++++-
>>>   target/rx/cpu.h          | 2 --
>>>   target/s390x/cpu-qom.h   | 5 ++++-
>>>   target/s390x/cpu.h       | 2 --
>>>   target/sh4/cpu-qom.h     | 5 ++++-
>>>   target/sh4/cpu.h         | 2 --
>>>   target/sparc/cpu-qom.h   | 5 ++++-
>>>   target/sparc/cpu.h       | 2 --
>>>   target/tricore/cpu-qom.h | 5 +++++
>>>   target/tricore/cpu.h     | 2 --
>>>   target/xtensa/cpu-qom.h  | 5 ++++-
>>>   target/xtensa/cpu.h      | 2 --
>>>   24 files changed, 47 insertions(+), 33 deletions(-)
>>>
>>> diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
>>> index 1f200724b6..d596d1b69f 100644
>>> --- a/target/alpha/cpu-qom.h
>>> +++ b/target/alpha/cpu-qom.h
>>> @@ -1,5 +1,5 @@
>>>   /*
>>> - * QEMU Alpha CPU
>>> + * QEMU Alpha CPU QOM header (target agnostic)
>>>    *
>>>    * Copyright (c) 2012 SUSE LINUX Products GmbH
>>>    *
>>> @@ -27,6 +27,9 @@
>>>   OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
>>> +#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
>>> +#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
>>> +
>>>   /**
>>>    * AlphaCPUClass:
>>>    * @parent_realize: The parent class' realize handler.
>>> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
>>> index e2a467ec17..ba0d9e3468 100644
>>> --- a/target/alpha/cpu.h
>>> +++ b/target/alpha/cpu.h
>>> @@ -428,8 +428,6 @@ enum {
>>>   void alpha_translate_init(void);
>>> -#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
>>> -#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
>>>   #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
>>>   void alpha_cpu_list(void);
> [...]

Re: [PATCH 01/18] target: Mention 'cpu-qom.h' is target agnostic

[Richard Henderson]

On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
> "target/foo/cpu-qom.h" is supposed to be target agnostic
> (include-able by any target). Add such mention in the
> header.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH 02/18] target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'

[Richard Henderson]

On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
> CPU_RESOLVING_TYPE is a per-target definition, and is
> irrelevant for other targets. Move it to "cpu.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/ppc/cpu-qom.h | 3 +--
>   target/ppc/cpu.h     | 2 ++
>   2 files changed, 3 insertions(+), 2 deletions(-)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH 03/18] target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'

[Richard Henderson]

On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
> CPU_RESOLVING_TYPE is a per-target definition, and is
> irrelevant for other targets. Move it to "cpu.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/riscv/cpu-qom.h | 1 -
>   target/riscv/cpu.h     | 2 ++
>   2 files changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH 04/18] target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'

[Richard Henderson]

On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
> Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME()
> macro to resolve target CPU types. Move the declaration
> (along with the required FOO_CPU_TYPE_SUFFIX) to "cpu-qom.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/alpha/cpu-qom.h   | 5 ++++-
>   target/alpha/cpu.h       | 2 --
>   target/avr/cpu-qom.h     | 5 ++++-
>   target/avr/cpu.h         | 2 --
>   target/cris/cpu-qom.h    | 5 ++++-
>   target/cris/cpu.h        | 2 --
>   target/i386/cpu-qom.h    | 3 +++
>   target/i386/cpu.h        | 2 --
>   target/m68k/cpu-qom.h    | 5 ++++-
>   target/m68k/cpu.h        | 2 --
>   target/mips/cpu-qom.h    | 3 +++
>   target/mips/cpu.h        | 2 --
>   target/rx/cpu-qom.h      | 5 ++++-
>   target/rx/cpu.h          | 2 --
>   target/s390x/cpu-qom.h   | 5 ++++-
>   target/s390x/cpu.h       | 2 --
>   target/sh4/cpu-qom.h     | 5 ++++-
>   target/sh4/cpu.h         | 2 --
>   target/sparc/cpu-qom.h   | 5 ++++-
>   target/sparc/cpu.h       | 2 --
>   target/tricore/cpu-qom.h | 5 +++++
>   target/tricore/cpu.h     | 2 --
>   target/xtensa/cpu-qom.h  | 5 ++++-
>   target/xtensa/cpu.h      | 2 --
>   24 files changed, 47 insertions(+), 33 deletions(-)

Seems ok.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH 05/18] target/hexagon: Declare QOM definitions in 'cpu-qom.h'

[Richard Henderson]

On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
> "target/foo/cpu.h" contains the target specific declarations.
> 
> A heterogeneous setup need to access target agnostic declarations
> (at least the QOM ones, to instantiate the objects).
> 
> Our convention is to add such target agnostic QOM declarations in
> the "target/foo/cpu-qom.h" header.
> 
> Extract QOM definitions from "cpu.h" to "cpu-qom.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/hexagon/cpu-qom.h | 35 +++++++++++++++++++++++++++++++++++
>   target/hexagon/cpu.h     | 23 +----------------------
>   2 files changed, 36 insertions(+), 22 deletions(-)
>   create mode 100644 target/hexagon/cpu-qom.h
> 
> diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h
> new file mode 100644
> index 0000000000..cd45850c64
> --- /dev/null
> +++ b/target/hexagon/cpu-qom.h
> @@ -0,0 +1,35 @@
> +/*
> + * QEMU Hexagon CPU QOM header (target agnostic)
> + *
> + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef QEMU_HEXAGON_CPU_QOM_H
> +#define QEMU_HEXAGON_CPU_QOM_H
> +
> +#include "hw/core/cpu.h"
> +#include "qom/object.h"
> +
> +#define TYPE_HEXAGON_CPU "hexagon-cpu"
> +
> +#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
> +#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
> +
> +#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
> +#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
> +#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
> +#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
> +#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
> +
> +OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
> +
> +typedef struct HexagonCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +} HexagonCPUClass;

I can't imagine the class structure being any more useful generically than the object 
structure.  All we need at this point is the typedef, provided by OBJECT_DECLARE_TYPE.

I know this makes hexagon match others, but I think its the wrong direction of cleanup.


r~

Re: [PATCH 09/18] target/i386: Inline target specific TARGET_DEFAULT_CPU_TYPE definition

[Richard Henderson]

On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
> TARGET_DEFAULT_CPU_TYPE depends on the TARGET_X86_64 definition
> which is target specific. Such target specific definition taint
> "cpu-qom.h".
> 
> Since "cpu-qom.h" must be target agnostic, remove this target
> specific definition uses by inlining TARGET_DEFAULT_CPU_TYPE in
> the two machines using it.
> 
> "target/i386/cpu-qom.h" is now fully target agnostic.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/i386/cpu.h | 6 ------
>   hw/i386/microvm.c | 6 +++++-
>   hw/i386/pc.c      | 6 +++++-
>   3 files changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 862e4f1ff5..7c976971c7 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -2243,12 +2243,6 @@ uint64_t cpu_get_tsc(CPUX86State *env);
>   
>   #define CPU_RESOLVING_TYPE TYPE_X86_CPU
>   
> -#ifdef TARGET_X86_64
> -#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
> -#else
> -#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
> -#endif
> -
>   #define cpu_list x86_cpu_list

This isn't cpu-qom.h, so the entire patch description is off...


r~

Re: [PATCH 10/18] target/riscv: Inline target specific TYPE_RISCV_CPU_BASE definition

[Richard Henderson]

On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
> TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64
> definitions which are target specific. Such target specific
> definition taints "cpu-qom.h".
> 
> Since "cpu-qom.h" must be target agnostic, remove its target
> specific definition uses by inlining TYPE_RISCV_CPU_BASE in the
> two machines using it.
> 
> "target/riscv/cpu-qom.h" is now fully target agnostic.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/riscv/cpu-qom.h | 8 +-------
>   hw/riscv/spike.c       | 8 +++++++-
>   hw/riscv/virt.c        | 8 +++++++-
>   3 files changed, 15 insertions(+), 9 deletions(-)
> 
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 8cb67b84a4..f607687384 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -1,5 +1,5 @@
>   /*
> - * QEMU RISC-V CPU QOM header
> + * QEMU RISC-V CPU QOM header (target agnostic)
>    *
>    * Copyright (c) 2023 Ventana Micro Systems Inc.
>    *
> @@ -43,12 +43,6 @@
>   #define TYPE_RISCV_CPU_VEYRON_V1        RISCV_CPU_TYPE_NAME("veyron-v1")
>   #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
>   
> -#if defined(TARGET_RISCV32)
> -# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
> -#elif defined(TARGET_RISCV64)
> -# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
> -#endif

Move to cpu.h (or elsewhere) instead of replicating in two hw/ files?


r~

Re: [PATCH 11/18] target/i386: Declare CPU QOM types using DEFINE_TYPES() macro

[Richard Henderson]

On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
> When multiple QOM types are registered in the same file,
> it is simpler to use the the DEFINE_TYPES() macro. In
> particular because type array declared with such macro
> are easier to review.
> 
> In few commits we are going to add more types, so replace
> the type_register_static() to ease further reviews.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH 12/18] target/mips: Declare CPU QOM types using DEFINE_TYPES() macro

[Richard Henderson]

On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
> When multiple QOM types are registered in the same file,
> it is simpler to use the the DEFINE_TYPES() macro. In
> particular because type array declared with such macro
> are easier to review.
> 
> In few commits we are going to add more types, so replace
> the type_register_static() to ease further reviews.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/cpu.c | 23 +++++++++++++----------
>   1 file changed, 13 insertions(+), 10 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH 13/18] target/ppc: Declare CPU QOM types using DEFINE_TYPES() macro

[Richard Henderson]

On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
> When multiple QOM types are registered in the same file,
> it is simpler to use the the DEFINE_TYPES() macro. In
> particular because type array declared with such macro
> are easier to review.
> 
> In few commits we are going to add more types, so replace
> the type_register_static() to ease further reviews.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/ppc/cpu_init.c | 52 +++++++++++++++++++------------------------
>   1 file changed, 23 insertions(+), 29 deletions(-)'

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 14/18] target/sparc: Declare CPU QOM types using DEFINE_TYPES() macro

[Richard Henderson]

On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
> When multiple QOM types are registered in the same file,
> it is simpler to use the the DEFINE_TYPES() macro. In
> particular because type array declared with such macro
> are easier to review.
> 
> In few commits we are going to add more types, so replace
> the type_register_static() to ease further reviews.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/sparc/cpu.c | 23 +++++++++++++----------
>   1 file changed, 13 insertions(+), 10 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH 15/18] cpus: Open code OBJECT_DECLARE_TYPE() in OBJECT_DECLARE_CPU_TYPE()

[Richard Henderson]

On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
> Since the OBJECT_DECLARE_CPU_TYPE() macro uses the abstract ArchCPU
> type, when declaring multiple CPUs of the same ArchCPU type we get
> an error related to the indirect G_DEFINE_AUTOPTR_CLEANUP_FUNC()
> use within OBJECT_DECLARE_TYPE():
> 
>    target/mips/cpu-qom.h:31:1: error: redefinition of 'glib_autoptr_clear_ArchCPU'
>    OBJECT_DECLARE_CPU_TYPE(MIPS64CPU, MIPSCPUClass, MIPS64_CPU)
>    ^
>    include/hw/core/cpu.h:82:5: note: expanded from macro 'OBJECT_DECLARE_CPU_TYPE'
>        OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
>        ^
>    include/qom/object.h:237:5: note: expanded from macro 'OBJECT_DECLARE_TYPE'
>        G_DEFINE_AUTOPTR_CLEANUP_FUNC(InstanceType, object_unref) \
>        ^
>    /usr/include/glib-2.0/glib/gmacros.h:1371:3: note: expanded from macro 'G_DEFINE_AUTOPTR_CLEANUP_FUNC'
>      _GLIB_DEFINE_AUTOPTR_CLEANUP_FUNCS(TypeName, TypeName, func)
>      ^
>    /usr/include/glib-2.0/glib/gmacros.h:1354:36: note: expanded from macro '_GLIB_DEFINE_AUTOPTR_CLEANUP_FUNCS'
>      static G_GNUC_UNUSED inline void _GLIB_AUTOPTR_CLEAR_FUNC_NAME(TypeName) (TypeName *_ptr)                     \
>                                       ^
>    /usr/include/glib-2.0/glib/gmacros.h:1338:49: note: expanded from macro '_GLIB_AUTOPTR_CLEAR_FUNC_NAME'
>    #define _GLIB_AUTOPTR_CLEAR_FUNC_NAME(TypeName) glib_autoptr_clear_##TypeName
>                                                    ^
>    <scratch space>:54:1: note: expanded from here
>    glib_autoptr_clear_ArchCPU
>    ^
>    target/mips/cpu-qom.h:30:1: note: previous definition is here
>    OBJECT_DECLARE_CPU_TYPE(MIPS32CPU, MIPSCPUClass, MIPS32_CPU)
>    ^
> 
> Avoid that problem by expanding the OBJECT_DECLARE_TYPE() macro
> within OBJECT_DECLARE_CPU_TYPE().
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   include/hw/core/cpu.h | 7 ++++++-
>   1 file changed, 6 insertions(+), 1 deletion(-)

Unfortunate, but I suppose this isn't so bad.

Acked-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 16/18] target/i386: Make X86_CPU common to new I386_CPU / X86_64_CPU types

[Richard Henderson]

On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
> "target/foo/cpu-qom.h" can not use any target specific definitions.
> 
> Currently "target/i386/cpu-qom.h" defines TYPE_X86_CPU depending
> on the i386/x86_64 build type. This doesn't scale in a heterogeneous
> context where we need to access both types concurrently.
> 
> In order to do that, introduce the new I386_CPU / X86_64_CPU
> types, both inheriting a common TYPE_X86_CPU base type.
> 
> Keep the current "base" and "max" CPU types as 32 or 64-bit,
> depending on the binary built.
> 
> Adapt the cpu-plug-test, since the 'base' architecture is now
> common to both 32/64-bit x86 targets.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/i386/cpu-qom.h       | 16 +++++++++-------
>   target/i386/cpu.h           |  3 +++
>   target/i386/cpu.c           | 20 ++++++++++++++++++--
>   tests/qtest/cpu-plug-test.c |  2 +-
>   4 files changed, 31 insertions(+), 10 deletions(-)

I suppose the concurrent existence of these two types will be used by follow-on cleanups?

Acked-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH 17/18] target/mips: Make MIPS_CPU common to new MIPS32_CPU / MIPS64_CPU types

[Richard Henderson]

On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
> "target/foo/cpu-qom.h" can not use any target specific definitions.
> 
> Currently "target/mips/cpu-qom.h" defines TYPE_MIPS_CPU depending
> on the mips(32)/mips64 build type. This doesn't scale in a
> heterogeneous context where we need to access both types concurrently.
> 
> In order to do that, introduce the new MIPS32_CPU / MIPS64_CPU types,
> both inheriting a common TYPE_MIPS_CPU base type.
> 
> Keep the current CPU types registered in mips_register_cpudef_type()
> as 32 or 64-bit, but instead of depending on the binary built being
> targeting 32/64-bit, check whether the CPU is 64-bit by looking at
> the CPU_MIPS64 bit.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/cpu-qom.h | 13 ++++++-------
>   target/mips/cpu.h     |  3 +++
>   target/mips/cpu.c     | 11 ++++++++++-
>   3 files changed, 19 insertions(+), 8 deletions(-)
> 
> diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
> index 9c98ca1956..1a71509b5e 100644
> --- a/target/mips/cpu-qom.h
> +++ b/target/mips/cpu-qom.h
> @@ -1,5 +1,5 @@
>   /*
> - * QEMU MIPS CPU
> + * QEMU MIPS CPU QOM header (target agnostic)
>    *
>    * Copyright (c) 2012 SUSE LINUX Products GmbH
>    *
> @@ -23,13 +23,12 @@
>   #include "hw/core/cpu.h"
>   #include "qom/object.h"
>   
> -#ifdef TARGET_MIPS64
> -#define TYPE_MIPS_CPU "mips64-cpu"
> -#else
> -#define TYPE_MIPS_CPU "mips-cpu"
> -#endif
> +#define TYPE_MIPS_CPU   "mips-cpu"
> +#define TYPE_MIPS32_CPU "mips32-cpu"
> +#define TYPE_MIPS64_CPU "mips64-cpu"
>   
> -OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
> +OBJECT_DECLARE_CPU_TYPE(MIPS32CPU, MIPSCPUClass, MIPS32_CPU)
> +OBJECT_DECLARE_CPU_TYPE(MIPS64CPU, MIPSCPUClass, MIPS64_CPU)
>   
>   #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
>   #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 6b026e6bcf..3b6d0a7a8a 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -10,6 +10,9 @@
>   #include "hw/clock.h"
>   #include "mips-defs.h"
>   
> +/* Abstract QOM MIPS CPU, not exposed to other targets */
> +OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)

Why is this one moved back to cpu.h?
You exposed TYPE_X86_CPU in i386/cpu-qom.h...


r~

Re: [PATCH 05/18] target/hexagon: Declare QOM definitions in 'cpu-qom.h'

[Philippe Mathieu-Daudé]

On 13/10/23 06:06, Richard Henderson wrote:
> On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
>> "target/foo/cpu.h" contains the target specific declarations.
>>
>> A heterogeneous setup need to access target agnostic declarations
>> (at least the QOM ones, to instantiate the objects).
>>
>> Our convention is to add such target agnostic QOM declarations in
>> the "target/foo/cpu-qom.h" header.
>>
>> Extract QOM definitions from "cpu.h" to "cpu-qom.h".
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   target/hexagon/cpu-qom.h | 35 +++++++++++++++++++++++++++++++++++
>>   target/hexagon/cpu.h     | 23 +----------------------
>>   2 files changed, 36 insertions(+), 22 deletions(-)
>>   create mode 100644 target/hexagon/cpu-qom.h


>> +OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
>> +
>> +typedef struct HexagonCPUClass {
>> +    CPUClass parent_class;
>> +
>> +    DeviceRealize parent_realize;
>> +    ResettablePhases parent_phases;
>> +} HexagonCPUClass;
> 
> I can't imagine the class structure being any more useful generically 
> than the object structure.  All we need at this point is the typedef, 
> provided by OBJECT_DECLARE_TYPE.

Right.

> I know this makes hexagon match others, but I think its the wrong 
> direction of cleanup.

I agree.

Re: [PATCH 15/18] cpus: Open code OBJECT_DECLARE_TYPE() in OBJECT_DECLARE_CPU_TYPE()

[Richard Henderson]

On 10/12/23 21:27, Richard Henderson wrote:
> On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
>> Since the OBJECT_DECLARE_CPU_TYPE() macro uses the abstract ArchCPU
>> type, when declaring multiple CPUs of the same ArchCPU type we get
>> an error related to the indirect G_DEFINE_AUTOPTR_CLEANUP_FUNC()
>> use within OBJECT_DECLARE_TYPE():
>>
>>    target/mips/cpu-qom.h:31:1: error: redefinition of 'glib_autoptr_clear_ArchCPU'
>>    OBJECT_DECLARE_CPU_TYPE(MIPS64CPU, MIPSCPUClass, MIPS64_CPU)
>>    ^
>>    include/hw/core/cpu.h:82:5: note: expanded from macro 'OBJECT_DECLARE_CPU_TYPE'
>>        OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
>>        ^
>>    include/qom/object.h:237:5: note: expanded from macro 'OBJECT_DECLARE_TYPE'
>>        G_DEFINE_AUTOPTR_CLEANUP_FUNC(InstanceType, object_unref) \
>>        ^
>>    /usr/include/glib-2.0/glib/gmacros.h:1371:3: note: expanded from macro 
>> 'G_DEFINE_AUTOPTR_CLEANUP_FUNC'
>>      _GLIB_DEFINE_AUTOPTR_CLEANUP_FUNCS(TypeName, TypeName, func)
>>      ^
>>    /usr/include/glib-2.0/glib/gmacros.h:1354:36: note: expanded from macro 
>> '_GLIB_DEFINE_AUTOPTR_CLEANUP_FUNCS'
>>      static G_GNUC_UNUSED inline void _GLIB_AUTOPTR_CLEAR_FUNC_NAME(TypeName) (TypeName 
>> *_ptr)                     \
>>                                       ^
>>    /usr/include/glib-2.0/glib/gmacros.h:1338:49: note: expanded from macro 
>> '_GLIB_AUTOPTR_CLEAR_FUNC_NAME'
>>    #define _GLIB_AUTOPTR_CLEAR_FUNC_NAME(TypeName) glib_autoptr_clear_##TypeName
>>                                                    ^
>>    <scratch space>:54:1: note: expanded from here
>>    glib_autoptr_clear_ArchCPU
>>    ^
>>    target/mips/cpu-qom.h:30:1: note: previous definition is here
>>    OBJECT_DECLARE_CPU_TYPE(MIPS32CPU, MIPSCPUClass, MIPS32_CPU)
>>    ^
>>
>> Avoid that problem by expanding the OBJECT_DECLARE_TYPE() macro
>> within OBJECT_DECLARE_CPU_TYPE().
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   include/hw/core/cpu.h | 7 ++++++-
>>   1 file changed, 6 insertions(+), 1 deletion(-)
> 
> Unfortunate, but I suppose this isn't so bad.
> 
> Acked-by: Richard Henderson <richard.henderson@linaro.org>

What about adding an OBJECT_DECLARE_CPU_SUBTYPE that omits half the stuff instead?
We don't need another object typedef at all, for instance.


r~

Re: [PATCH 10/18] target/riscv: Inline target specific TYPE_RISCV_CPU_BASE definition

[Philippe Mathieu-Daudé]

On 13/10/23 06:13, Richard Henderson wrote:
> On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
>> TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64
>> definitions which are target specific. Such target specific
>> definition taints "cpu-qom.h".
>>
>> Since "cpu-qom.h" must be target agnostic, remove its target
>> specific definition uses by inlining TYPE_RISCV_CPU_BASE in the
>> two machines using it.
>>
>> "target/riscv/cpu-qom.h" is now fully target agnostic.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   target/riscv/cpu-qom.h | 8 +-------
>>   hw/riscv/spike.c       | 8 +++++++-
>>   hw/riscv/virt.c        | 8 +++++++-
>>   3 files changed, 15 insertions(+), 9 deletions(-)


>> @@ -43,12 +43,6 @@
>>   #define TYPE_RISCV_CPU_VEYRON_V1        
>> RISCV_CPU_TYPE_NAME("veyron-v1")
>>   #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
>> -#if defined(TARGET_RISCV32)
>> -# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
>> -#elif defined(TARGET_RISCV64)
>> -# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
>> -#endif
> 
> Move to cpu.h (or elsewhere) instead of replicating in two hw/ files?

Yes, better.

Re: [PATCH 14/18] target/sparc: Declare CPU QOM types using DEFINE_TYPES() macro

[Mark Cave-Ayland]

On 10/10/2023 10:28, Philippe Mathieu-Daudé wrote:

> When multiple QOM types are registered in the same file,
> it is simpler to use the the DEFINE_TYPES() macro. In
> particular because type array declared with such macro
> are easier to review.
> 
> In few commits we are going to add more types, so replace
> the type_register_static() to ease further reviews.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/sparc/cpu.c | 23 +++++++++++++----------
>   1 file changed, 13 insertions(+), 10 deletions(-)
> 
> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
> index 8ba96ae225..1e66413e94 100644
> --- a/target/sparc/cpu.c
> +++ b/target/sparc/cpu.c
> @@ -924,17 +924,21 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
>       cc->tcg_ops = &sparc_tcg_ops;
>   }
>   
> -static const TypeInfo sparc_cpu_type_info = {
> -    .name = TYPE_SPARC_CPU,
> -    .parent = TYPE_CPU,
> -    .instance_size = sizeof(SPARCCPU),
> -    .instance_align = __alignof(SPARCCPU),
> -    .instance_init = sparc_cpu_initfn,
> -    .abstract = true,
> -    .class_size = sizeof(SPARCCPUClass),
> -    .class_init = sparc_cpu_class_init,
> +static const TypeInfo sparc_cpu_types[] = {
> +    {
> +        .name           = TYPE_SPARC_CPU,
> +        .parent         = TYPE_CPU,
> +        .instance_size  = sizeof(SPARCCPU),
> +        .instance_align = __alignof(SPARCCPU),
> +        .instance_init  = sparc_cpu_initfn,
> +        .abstract       = true,
> +        .class_size     = sizeof(SPARCCPUClass),
> +        .class_init     = sparc_cpu_class_init,
> +    }
>   };
>   
> +DEFINE_TYPES(sparc_cpu_types)
> +
>   static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data)
>   {
>       SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
> @@ -959,7 +963,6 @@ static void sparc_cpu_register_types(void)
>   {
>       int i;
>   
> -    type_register_static(&sparc_cpu_type_info);
>       for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
>           sparc_register_cpudef_type(&sparc_defs[i]);
>       }

Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


ATB,

Mark.

Re: [PATCH 18/18] target/sparc: Make SPARC_CPU common to new SPARC32_CPU/SPARC64_CPU types

[Mark Cave-Ayland]

On 10/10/2023 10:29, Philippe Mathieu-Daudé wrote:

> "target/foo/cpu-qom.h" can not use any target specific definitions.
> 
> Currently "target/sparc/cpu-qom.h" defines TYPE_SPARC_CPU
> depending on the sparc(32)/sparc64 build type. This doesn't
> scale in a heterogeneous context where we need to access both
> types concurrently.
> 
> In order to do that, introduce the new SPARC32_CPU / SPARC64_CPU
> types, both inheriting a common TYPE_SPARC_CPU base type.
> 
> Keep the current CPU types registered in sparc_register_cpudef_type()
> as 32 or 64-bit, depending on the binary built.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/sparc/cpu-qom.h |  9 ++++-----
>   target/sparc/cpu.h     |  3 +++
>   target/sparc/cpu.c     | 12 +++++++++++-
>   3 files changed, 18 insertions(+), 6 deletions(-)
> 
> diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
> index 86b24a254a..d08fbd4ddc 100644
> --- a/target/sparc/cpu-qom.h
> +++ b/target/sparc/cpu-qom.h
> @@ -23,13 +23,12 @@
>   #include "hw/core/cpu.h"
>   #include "qom/object.h"
>   
> -#ifdef TARGET_SPARC64
> -#define TYPE_SPARC_CPU "sparc64-cpu"
> -#else
>   #define TYPE_SPARC_CPU "sparc-cpu"
> -#endif
> +#define TYPE_SPARC32_CPU "sparc32-cpu"
> +#define TYPE_SPARC64_CPU "sparc64-cpu"
>   
> -OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
> +OBJECT_DECLARE_CPU_TYPE(SPARC32CPU, SPARCCPUClass, SPARC32_CPU)
> +OBJECT_DECLARE_CPU_TYPE(SPARC64CPU, SPARCCPUClass, SPARC64_CPU)
>   
>   #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
>   #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
> diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
> index 924e83b9ce..0f94e5a442 100644
> --- a/target/sparc/cpu.h
> +++ b/target/sparc/cpu.h
> @@ -12,6 +12,9 @@
>   #define TARGET_DPREGS 32
>   #endif
>   
> +/* Abstract QOM SPARC CPU, not exposed to other targets */
> +OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
> +
>   /*#define EXCP_INTERRUPT 0x100*/
>   
>   /* Windowed register indexes.  */
> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
> index 1e66413e94..7d060ba488 100644
> --- a/target/sparc/cpu.c
> +++ b/target/sparc/cpu.c
> @@ -934,6 +934,12 @@ static const TypeInfo sparc_cpu_types[] = {
>           .abstract       = true,
>           .class_size     = sizeof(SPARCCPUClass),
>           .class_init     = sparc_cpu_class_init,
> +    }, {
> +        .name           = TYPE_SPARC32_CPU,
> +        .parent         = TYPE_SPARC_CPU,
> +    }, {
> +        .name           = TYPE_SPARC64_CPU,
> +        .parent         = TYPE_SPARC_CPU,
>       }
>   };
>   
> @@ -950,7 +956,11 @@ static void sparc_register_cpudef_type(const struct sparc_def_t *def)
>       char *typename = sparc_cpu_type_name(def->name);
>       TypeInfo ti = {
>           .name = typename,
> -        .parent = TYPE_SPARC_CPU,
> +#ifdef TARGET_SPARC64
> +        .parent = TYPE_SPARC64_CPU,
> +#else
> +        .parent = TYPE_SPARC32_CPU,
> +#endif
>           .class_init = sparc_cpu_cpudef_class_init,
>           .class_data = (void *)def,
>       };

I do have a long-standing TODO which is to look at better separation between 32-bit 
and 64-bit SPARC, however for now:

Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


ATB,

Mark.

Re: [PATCH 17/18] target/mips: Make MIPS_CPU common to new MIPS32_CPU / MIPS64_CPU types

[Philippe Mathieu-Daudé]

On 13/10/23 06:34, Richard Henderson wrote:
> On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
>> "target/foo/cpu-qom.h" can not use any target specific definitions.
>>
>> Currently "target/mips/cpu-qom.h" defines TYPE_MIPS_CPU depending
>> on the mips(32)/mips64 build type. This doesn't scale in a
>> heterogeneous context where we need to access both types concurrently.
>>
>> In order to do that, introduce the new MIPS32_CPU / MIPS64_CPU types,
>> both inheriting a common TYPE_MIPS_CPU base type.
>>
>> Keep the current CPU types registered in mips_register_cpudef_type()
>> as 32 or 64-bit, but instead of depending on the binary built being
>> targeting 32/64-bit, check whether the CPU is 64-bit by looking at
>> the CPU_MIPS64 bit.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   target/mips/cpu-qom.h | 13 ++++++-------
>>   target/mips/cpu.h     |  3 +++
>>   target/mips/cpu.c     | 11 ++++++++++-
>>   3 files changed, 19 insertions(+), 8 deletions(-)
>>
>> diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
>> index 9c98ca1956..1a71509b5e 100644
>> --- a/target/mips/cpu-qom.h
>> +++ b/target/mips/cpu-qom.h
>> @@ -1,5 +1,5 @@
>>   /*
>> - * QEMU MIPS CPU
>> + * QEMU MIPS CPU QOM header (target agnostic)
>>    *
>>    * Copyright (c) 2012 SUSE LINUX Products GmbH
>>    *
>> @@ -23,13 +23,12 @@
>>   #include "hw/core/cpu.h"
>>   #include "qom/object.h"
>> -#ifdef TARGET_MIPS64
>> -#define TYPE_MIPS_CPU "mips64-cpu"
>> -#else
>> -#define TYPE_MIPS_CPU "mips-cpu"
>> -#endif
>> +#define TYPE_MIPS_CPU   "mips-cpu"
>> +#define TYPE_MIPS32_CPU "mips32-cpu"
>> +#define TYPE_MIPS64_CPU "mips64-cpu"
>> -OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
>> +OBJECT_DECLARE_CPU_TYPE(MIPS32CPU, MIPSCPUClass, MIPS32_CPU)
>> +OBJECT_DECLARE_CPU_TYPE(MIPS64CPU, MIPSCPUClass, MIPS64_CPU)
>>   #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
>>   #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
>> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
>> index 6b026e6bcf..3b6d0a7a8a 100644
>> --- a/target/mips/cpu.h
>> +++ b/target/mips/cpu.h
>> @@ -10,6 +10,9 @@
>>   #include "hw/clock.h"
>>   #include "mips-defs.h"
>> +/* Abstract QOM MIPS CPU, not exposed to other targets */
>> +OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
> 
> Why is this one moved back to cpu.h?
> You exposed TYPE_X86_CPU in i386/cpu-qom.h...

First thinking was to expose the base TYPE, so we can use QOM methods
to enumerate implementations, but not expose QOM state/class getter
for the base type (except in target/foo/). HW would use concrete
32 or 64b type state/class getter. I might be wrong, so I'll keep
the base type exposed for now. We might restrict later.

Re: [PATCH 17/18] target/mips: Make MIPS_CPU common to new MIPS32_CPU / MIPS64_CPU types

[Philippe Mathieu-Daudé]

On 15/3/24 13:22, Philippe Mathieu-Daudé wrote:
> On 13/10/23 06:34, Richard Henderson wrote:
>> On 10/10/23 02:28, Philippe Mathieu-Daudé wrote:
>>> "target/foo/cpu-qom.h" can not use any target specific definitions.
>>>
>>> Currently "target/mips/cpu-qom.h" defines TYPE_MIPS_CPU depending
>>> on the mips(32)/mips64 build type. This doesn't scale in a
>>> heterogeneous context where we need to access both types concurrently.
>>>
>>> In order to do that, introduce the new MIPS32_CPU / MIPS64_CPU types,
>>> both inheriting a common TYPE_MIPS_CPU base type.
>>>
>>> Keep the current CPU types registered in mips_register_cpudef_type()
>>> as 32 or 64-bit, but instead of depending on the binary built being
>>> targeting 32/64-bit, check whether the CPU is 64-bit by looking at
>>> the CPU_MIPS64 bit.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>> ---
>>>   target/mips/cpu-qom.h | 13 ++++++-------
>>>   target/mips/cpu.h     |  3 +++
>>>   target/mips/cpu.c     | 11 ++++++++++-
>>>   3 files changed, 19 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
>>> index 9c98ca1956..1a71509b5e 100644
>>> --- a/target/mips/cpu-qom.h
>>> +++ b/target/mips/cpu-qom.h
>>> @@ -1,5 +1,5 @@
>>>   /*
>>> - * QEMU MIPS CPU
>>> + * QEMU MIPS CPU QOM header (target agnostic)
>>>    *
>>>    * Copyright (c) 2012 SUSE LINUX Products GmbH
>>>    *
>>> @@ -23,13 +23,12 @@
>>>   #include "hw/core/cpu.h"
>>>   #include "qom/object.h"
>>> -#ifdef TARGET_MIPS64
>>> -#define TYPE_MIPS_CPU "mips64-cpu"
>>> -#else
>>> -#define TYPE_MIPS_CPU "mips-cpu"
>>> -#endif
>>> +#define TYPE_MIPS_CPU   "mips-cpu"
>>> +#define TYPE_MIPS32_CPU "mips32-cpu"
>>> +#define TYPE_MIPS64_CPU "mips64-cpu"
>>> -OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
>>> +OBJECT_DECLARE_CPU_TYPE(MIPS32CPU, MIPSCPUClass, MIPS32_CPU)
>>> +OBJECT_DECLARE_CPU_TYPE(MIPS64CPU, MIPSCPUClass, MIPS64_CPU)
>>>   #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
>>>   #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
>>> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
>>> index 6b026e6bcf..3b6d0a7a8a 100644
>>> --- a/target/mips/cpu.h
>>> +++ b/target/mips/cpu.h
>>> @@ -10,6 +10,9 @@
>>>   #include "hw/clock.h"
>>>   #include "mips-defs.h"
>>> +/* Abstract QOM MIPS CPU, not exposed to other targets */
>>> +OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
>>
>> Why is this one moved back to cpu.h?
>> You exposed TYPE_X86_CPU in i386/cpu-qom.h...
> 
> First thinking was to expose the base TYPE, so we can use QOM methods
> to enumerate implementations, but not expose QOM state/class getter
> for the base type (except in target/foo/). HW would use concrete
> 32 or 64b type state/class getter. I might be wrong, so I'll keep
> the base type exposed for now. We might restrict later.

With retrospective I was indeed wrong, as it seems useful for a
heterogeneous board to check "is there any vCPU based on Arch FOO"
without having to worry for FOO being 32 or 64. I'll expose the
base arch as QOM definition.