From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Andrey Smirnov" <andrew.smirnov@gmail.com>,
qemu-arm@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 3/8] hw/pci-host/designware: Add 'host_mem' variable for clarity
Date: Thu, 12 Oct 2023 14:18:51 +0200 [thread overview]
Message-ID: <20231012121857.31873-4-philmd@linaro.org> (raw)
In-Reply-To: <20231012121857.31873-1-philmd@linaro.org>
designware_pcie_root_realize() uses get_system_memory()
as the "host side memory region", as opposed to the "PCI
side" one. Introduce the 'host_mem' variable for clarity.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/pci-host/designware.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 692e0731cd..bacb2bdb2d 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -393,6 +393,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
{
DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev);
DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
+ MemoryRegion *host_mem = get_system_memory();
MemoryRegion *address_space = &host->pci.memory;
PCIBridge *br = PCI_BRIDGE(dev);
DesignwarePCIEViewport *viewport;
@@ -433,7 +434,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM;
source = &host->pci.address_space_root;
- destination = get_system_memory();
+ destination = host_mem;
direction = "Inbound";
/*
@@ -458,7 +459,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
destination = &host->pci.memory;
direction = "Outbound";
- source = get_system_memory();
+ source = host_mem;
/*
* Configure MemoryRegion implementing CPU -> PCI memory
--
2.41.0
next prev parent reply other threads:[~2023-10-12 12:22 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-12 12:18 [PATCH 0/8] hw/pci-host/designware: QOM shuffling (Host bridge <-> Root function) Philippe Mathieu-Daudé
2023-10-12 12:18 ` [PATCH 1/8] hw/pci-host/designware: Declare CPU QOM types using DEFINE_TYPES() macro Philippe Mathieu-Daudé
2023-10-17 16:31 ` Peter Maydell
2024-08-19 4:21 ` Gustavo Romero
2024-09-10 14:33 ` Philippe Mathieu-Daudé
2023-10-12 12:18 ` [PATCH 2/8] hw/pci-host/designware: Initialize root function in host bridge realize Philippe Mathieu-Daudé
2023-10-17 16:32 ` Peter Maydell
2024-02-06 16:35 ` Philippe Mathieu-Daudé
2024-08-19 4:21 ` Gustavo Romero
2023-10-12 12:18 ` Philippe Mathieu-Daudé [this message]
2023-10-17 16:33 ` [PATCH 3/8] hw/pci-host/designware: Add 'host_mem' variable for clarity Peter Maydell
2024-08-19 4:21 ` Gustavo Romero
2023-10-12 12:18 ` [PATCH 4/8] hw/pci-host/designware: Hoist host controller in root function #0 Philippe Mathieu-Daudé
2024-08-19 4:22 ` Gustavo Romero
2023-10-12 12:18 ` [PATCH 5/8] hw/pci-host/designware: Keep host reference in DesignwarePCIEViewport Philippe Mathieu-Daudé
2024-08-19 4:22 ` Gustavo Romero
2023-10-12 12:18 ` [PATCH 6/8] hw/pci-host/designware: Move viewports from root func to host bridge Philippe Mathieu-Daudé
2024-08-19 4:23 ` Gustavo Romero
2023-10-12 12:18 ` [PATCH 7/8] hw/pci-host/designware: Move MSI registers " Philippe Mathieu-Daudé
2024-08-19 4:23 ` Gustavo Romero
2023-10-12 12:18 ` [PATCH 8/8] hw/pci-host/designware: Create ViewPorts during host bridge realization Philippe Mathieu-Daudé
2024-08-19 4:23 ` Gustavo Romero
2023-10-27 12:18 ` [PATCH 0/8] hw/pci-host/designware: QOM shuffling (Host bridge <-> Root function) Peter Maydell
2023-11-15 14:47 ` [PATCH-for-9.0 " Philippe Mathieu-Daudé
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