From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Salil Mehta <salil.mehta@huawei.com>
Cc: <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>, <maz@kernel.org>,
<jean-philippe@linaro.org>, <lpieralisi@kernel.org>,
<peter.maydell@linaro.org>, <richard.henderson@linaro.org>,
<imammedo@redhat.com>, <andrew.jones@linux.dev>,
<david@redhat.com>, <philmd@linaro.org>, <eric.auger@redhat.com>,
<oliver.upton@linux.dev>, <pbonzini@redhat.com>, <mst@redhat.com>,
<will@kernel.org>, <gshan@redhat.com>, <rafael@kernel.org>,
<alex.bennee@linaro.org>, <linux@armlinux.org.uk>,
<darren@os.amperecomputing.com>, <ilkka@os.amperecomputing.com>,
<vishnu@os.amperecomputing.com>, <karl.heubaum@oracle.com>,
<miguel.luis@oracle.com>, <salil.mehta@opnsrc.net>,
<zhukeqian1@huawei.com>, <wangxiongfeng2@huawei.com>,
<wangyanan55@huawei.com>, <jiakernel2@gmail.com>,
<maobibo@loongson.cn>, <lixianglai@loongson.cn>,
<linuxarm@huawei.com>
Subject: Re: [PATCH V5 5/9] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change
Date: Thu, 12 Oct 2023 15:49:04 +0100 [thread overview]
Message-ID: <20231012154904.0000728e@Huawei.com> (raw)
In-Reply-To: <20231011194355.15628-6-salil.mehta@huawei.com>
On Wed, 11 Oct 2023 20:43:51 +0100
Salil Mehta <salil.mehta@huawei.com> wrote:
> CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based on
> PCI and is IO port based and hence existing CPUs AML code assumes _CRS objects
> would evaluate to a system resource which describes IO Port address. But on ARM
> arch CPUs control device(\\_SB.PRES) register interface is memory-mapped hence
> _CRS object should evaluate to system resource which describes memory-mapped
> base address. Update build CPUs AML function to accept both IO/MEMORY region
> spaces and accordingly update the _CRS object.
>
> Legacy CPU Hotplug uses Generic ACPI GPE Block Bit 2 (GPE.2) event handler to
> notify OSPM about any CPU hot(un)plug events. GED framework uses new register
> interface for cpu-(ctrl)dev. Make AML for GPE.2 event handler conditional.
>
> Co-developed-by: Keqian Zhu <zhukeqian1@huawei.com>
> Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
> Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
> Reviewed-by: Gavin Shan <gshan@redhat.com>
> Tested-by: Vishnu Pajjuri <vishnu@os.amperecomputing.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Salil Mehta <salil.mehta@huawei.com>
Cc: <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>, <maz@kernel.org>,
<jean-philippe@linaro.org>, <lpieralisi@kernel.org>,
<peter.maydell@linaro.org>, <richard.henderson@linaro.org>,
<imammedo@redhat.com>, <andrew.jones@linux.dev>,
<david@redhat.com>, <philmd@linaro.org>, <eric.auger@redhat.com>,
<oliver.upton@linux.dev>, <pbonzini@redhat.com>, <mst@redhat.com>,
<will@kernel.org>, <gshan@redhat.com>, <rafael@kernel.org>,
<alex.bennee@linaro.org>, <linux@armlinux.org.uk>,
<darren@os.amperecomputing.com>, <ilkka@os.amperecomputing.com>,
<vishnu@os.amperecomputing.com>, <karl.heubaum@oracle.com>,
<miguel.luis@oracle.com>, <salil.mehta@opnsrc.net>,
<zhukeqian1@huawei.com>, <wangxiongfeng2@huawei.com>,
<wangyanan55@huawei.com>, <jiakernel2@gmail.com>,
<maobibo@loongson.cn>, <lixianglai@loongson.cn>,
<linuxarm@huawei.com>
Subject: Re: [PATCH V5 5/9] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change
Date: Thu, 12 Oct 2023 15:49:04 +0100 [thread overview]
Message-ID: <20231012154904.0000728e@Huawei.com> (raw)
Message-ID: <20231012144904.gblN0JzZqOF88LGMUA7hbS5v0V6pp52ymTzmXpHeZUk@z> (raw)
In-Reply-To: <20231011194355.15628-6-salil.mehta@huawei.com>
On Wed, 11 Oct 2023 20:43:51 +0100
Salil Mehta <salil.mehta@huawei.com> wrote:
> CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is based on
> PCI and is IO port based and hence existing CPUs AML code assumes _CRS objects
> would evaluate to a system resource which describes IO Port address. But on ARM
> arch CPUs control device(\\_SB.PRES) register interface is memory-mapped hence
> _CRS object should evaluate to system resource which describes memory-mapped
> base address. Update build CPUs AML function to accept both IO/MEMORY region
> spaces and accordingly update the _CRS object.
>
> Legacy CPU Hotplug uses Generic ACPI GPE Block Bit 2 (GPE.2) event handler to
> notify OSPM about any CPU hot(un)plug events. GED framework uses new register
> interface for cpu-(ctrl)dev. Make AML for GPE.2 event handler conditional.
>
> Co-developed-by: Keqian Zhu <zhukeqian1@huawei.com>
> Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
> Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
> Reviewed-by: Gavin Shan <gshan@redhat.com>
> Tested-by: Vishnu Pajjuri <vishnu@os.amperecomputing.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
next prev parent reply other threads:[~2023-10-12 14:49 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-11 19:43 [PATCH V5 0/9] Add architecture agnostic code to support vCPU Hotplug Salil Mehta via
2023-10-11 19:43 ` Salil Mehta
2023-10-11 19:43 ` [PATCH V5 1/9] accel/kvm: Extract common KVM vCPU {creation, parking} code Salil Mehta via
2023-10-11 19:43 ` Salil Mehta
2023-10-12 14:36 ` [PATCH V5 1/9] accel/kvm: Extract common KVM vCPU {creation,parking} code Jonathan Cameron via
2023-10-12 14:36 ` Jonathan Cameron
2023-10-12 14:38 ` Salil Mehta via
2023-10-12 14:38 ` Salil Mehta
2023-10-16 2:45 ` [PATCH V5 1/9] accel/kvm: Extract common KVM vCPU {creation, parking} code Shaoqin Huang
2023-10-16 2:47 ` Shaoqin Huang
2023-10-11 19:43 ` [PATCH V5 2/9] hw/acpi: Move CPU ctrl-dev MMIO region len macro to common header file Salil Mehta via
2023-10-11 19:43 ` Salil Mehta
2023-10-11 19:43 ` [PATCH V5 3/9] hw/acpi: Add ACPI CPU hotplug init stub Salil Mehta via
2023-10-11 19:43 ` Salil Mehta
2023-10-11 19:43 ` [PATCH V5 4/9] hw/acpi: Init GED framework with CPU hotplug events Salil Mehta via
2023-10-11 19:43 ` Salil Mehta
2023-10-16 2:53 ` Shaoqin Huang
2023-10-16 10:01 ` Salil Mehta via
2023-10-16 10:01 ` Salil Mehta
2023-10-11 19:43 ` [PATCH V5 5/9] hw/acpi: Update CPUs AML with cpu-(ctrl)dev change Salil Mehta via
2023-10-11 19:43 ` Salil Mehta
2023-10-12 14:49 ` Jonathan Cameron via [this message]
2023-10-12 14:49 ` Jonathan Cameron
2023-10-11 19:43 ` [PATCH V5 6/9] hw/acpi: Update GED _EVT method AML with CPU scan Salil Mehta via
2023-10-11 19:43 ` Salil Mehta
2023-10-11 19:43 ` [PATCH V5 7/9] hw/acpi: Update ACPI GED framework to support vCPU Hotplug Salil Mehta via
2023-10-11 19:43 ` Salil Mehta
2023-10-11 19:43 ` [PATCH V5 8/9] physmem: Add helper function to destroy CPU AddressSpace Salil Mehta via
2023-10-11 19:43 ` Salil Mehta
2023-10-11 23:31 ` Gavin Shan
2023-10-12 0:04 ` Salil Mehta
2023-10-12 0:18 ` Gavin Shan
2023-10-12 9:22 ` Salil Mehta via
2023-10-12 9:22 ` Salil Mehta
2023-10-11 19:43 ` [PATCH V5 9/9] gdbstub: Add helper function to unregister GDB register space Salil Mehta via
2023-10-11 19:43 ` Salil Mehta
2023-10-12 0:07 ` Gavin Shan
2023-10-12 9:19 ` Salil Mehta via
2023-10-12 9:19 ` Salil Mehta
2023-10-13 3:58 ` [PATCH V5 0/9] Add architecture agnostic code to support vCPU Hotplug lixianglai
2023-10-13 10:21 ` Salil Mehta via
2023-10-13 10:21 ` Salil Mehta
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