[PATCH 0/4] target/riscv: rename ext_i* to ext_zi*

[PATCH 0/4] target/riscv: rename ext_i* to ext_zi*

[Daniel Henrique Barboza]

Hi,

This series renames the following internal extensions flags:

ext_ifencei, ext_icsr, ext_icbom, ext_icboz

To add a leading 'z':

ext_zifencei, ext_zicsr, ext_zicbom, ext_zicboz

This was proposed by Andrew Jones. The motivation, in his own words:

"I'd prefer we name the booleans with their 'z' to improve grepping.
When one wants to search for uses of zifencei, I imagine they're more
likely to do 'grep -i zifencei' than 'grep -i ifencei', particularly
because the 's' is maintained for S extensions. "


Aside from that, these are the only 4 Z-extension flags that don't use a
leading 'z' in their name, so there's also the benefit of making
everything equal.



Daniel Henrique Barboza (4):
  target/riscv: rename ext_ifencei to ext_zifencei
  target/riscv: rename ext_icsr to ext_zicsr
  target/riscv: rename ext_icbom to ext_zicbom
  target/riscv: rename ext_icboz to ext_zicboz

 hw/riscv/boot.c                             |  2 +-
 hw/riscv/virt.c                             |  4 +-
 target/riscv/cpu.c                          | 56 ++++++++++-----------
 target/riscv/cpu_cfg.h                      |  8 +--
 target/riscv/csr.c                          |  2 +-
 target/riscv/gdbstub.c                      |  2 +-
 target/riscv/insn_trans/trans_rvi.c.inc     |  2 +-
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 +++---
 target/riscv/kvm/kvm-cpu.c                  | 12 ++---
 target/riscv/tcg/tcg-cpu.c                  | 20 ++++----
 10 files changed, 62 insertions(+), 62 deletions(-)

-- 
2.41.0

[PATCH 1/4] target/riscv: rename ext_ifencei to ext_zifencei

[Daniel Henrique Barboza]

Add a leading 'z' to improve grepping. When one wants to search for uses
of zifencei they're more likely to do 'grep -i zifencei' than 'grep -i
ifencei'.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c                      | 22 +++++++++++-----------
 target/riscv/cpu_cfg.h                  |  2 +-
 target/riscv/insn_trans/trans_rvi.c.inc |  2 +-
 target/riscv/tcg/tcg-cpu.c              |  8 ++++----
 4 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5425bceac1..caf42ce68d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -80,7 +80,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
     ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
     ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
-    ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
+    ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei),
     ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
     ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
     ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
@@ -382,7 +382,7 @@ static void riscv_any_cpu_init(Object *obj)
     env->priv_ver = PRIV_VERSION_LATEST;
 
     /* inherited from parent obj via riscv_cpu_init() */
-    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_zifencei = true;
     cpu->cfg.ext_icsr = true;
     cpu->cfg.mmu = true;
     cpu->cfg.pmp = true;
@@ -430,7 +430,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
-    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_zifencei = true;
     cpu->cfg.ext_icsr = true;
     cpu->cfg.mmu = true;
     cpu->cfg.pmp = true;
@@ -448,7 +448,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
-    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_zifencei = true;
     cpu->cfg.ext_icsr = true;
     cpu->cfg.pmp = true;
 }
@@ -494,7 +494,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
 
     /* Enable ISA extensions */
     cpu->cfg.mmu = true;
-    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_zifencei = true;
     cpu->cfg.ext_icsr = true;
     cpu->cfg.pmp = true;
     cpu->cfg.ext_icbom = true;
@@ -566,7 +566,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
-    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_zifencei = true;
     cpu->cfg.ext_icsr = true;
     cpu->cfg.mmu = true;
     cpu->cfg.pmp = true;
@@ -584,7 +584,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
-    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_zifencei = true;
     cpu->cfg.ext_icsr = true;
     cpu->cfg.pmp = true;
 }
@@ -602,7 +602,7 @@ static void rv32_ibex_cpu_init(Object *obj)
     cpu->cfg.epmp = true;
 
     /* inherited from parent obj via riscv_cpu_init() */
-    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_zifencei = true;
     cpu->cfg.ext_icsr = true;
     cpu->cfg.pmp = true;
 }
@@ -619,7 +619,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
-    cpu->cfg.ext_ifencei = true;
+    cpu->cfg.ext_zifencei = true;
     cpu->cfg.ext_icsr = true;
     cpu->cfg.pmp = true;
 }
@@ -1242,7 +1242,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit)
 const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Defaults for standard extensions */
     MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
-    MULTI_EXT_CFG_BOOL("zifencei", ext_ifencei, true),
+    MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
     MULTI_EXT_CFG_BOOL("zicsr", ext_icsr, true),
     MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
     MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
@@ -1347,7 +1347,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
 
 /* Deprecated entries marked for future removal */
 const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
-    MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
+    MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true),
     MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
     MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
     MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 0e6a0f245c..a3f96eb878 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -61,7 +61,7 @@ struct RISCVCPUConfig {
     bool ext_zksed;
     bool ext_zksh;
     bool ext_zkt;
-    bool ext_ifencei;
+    bool ext_zifencei;
     bool ext_icsr;
     bool ext_icbom;
     bool ext_icboz;
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 25cb60558a..faf6d65064 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -799,7 +799,7 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a)
 
 static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
 {
-    if (!ctx->cfg_ptr->ext_ifencei) {
+    if (!ctx->cfg_ptr->ext_zifencei) {
         return false;
     }
 
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index a28918ab30..9b8f3f54a7 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -278,7 +278,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
           riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
           riscv_has_ext(env, RVD) &&
-          cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
+          cpu->cfg.ext_icsr && cpu->cfg.ext_zifencei)) {
 
         if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
             !cpu->cfg.ext_icsr) {
@@ -286,15 +286,15 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
             return;
         }
 
-        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
-            !cpu->cfg.ext_ifencei) {
+        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei)) &&
+            !cpu->cfg.ext_zifencei) {
             error_setg(errp, "RVG requires Zifencei but user set "
                        "Zifencei to false");
             return;
         }
 
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zifencei), true);
 
         env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
         env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
-- 
2.41.0

[PATCH 2/4] target/riscv: rename ext_icsr to ext_zicsr

[Daniel Henrique Barboza]

Add a leading 'z' to improve grepping. When one wants to search for uses
of zicsr they're more likely to do 'grep -i zicsr' than 'grep -i icsr'.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 hw/riscv/boot.c            |  2 +-
 target/riscv/cpu.c         | 22 +++++++++++-----------
 target/riscv/cpu_cfg.h     |  2 +-
 target/riscv/csr.c         |  2 +-
 target/riscv/gdbstub.c     |  2 +-
 target/riscv/tcg/tcg-cpu.c | 14 +++++++-------
 6 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 52bf8e67de..0ffca05189 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -414,7 +414,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
         reset_vec[4] = 0x0182b283;   /*     ld     t0, 24(t0) */
     }
 
-    if (!harts->harts[0].cfg.ext_icsr) {
+    if (!harts->harts[0].cfg.ext_zicsr) {
         /*
          * The Zicsr extension has been disabled, so let's ensure we don't
          * run the CSR instruction. Let's fill the address with a non
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index caf42ce68d..fdbbafe7b3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -79,7 +79,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
     ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
     ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
-    ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
+    ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
     ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei),
     ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
     ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
@@ -383,7 +383,7 @@ static void riscv_any_cpu_init(Object *obj)
 
     /* inherited from parent obj via riscv_cpu_init() */
     cpu->cfg.ext_zifencei = true;
-    cpu->cfg.ext_icsr = true;
+    cpu->cfg.ext_zicsr = true;
     cpu->cfg.mmu = true;
     cpu->cfg.pmp = true;
 }
@@ -431,7 +431,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
 
     /* inherited from parent obj via riscv_cpu_init() */
     cpu->cfg.ext_zifencei = true;
-    cpu->cfg.ext_icsr = true;
+    cpu->cfg.ext_zicsr = true;
     cpu->cfg.mmu = true;
     cpu->cfg.pmp = true;
 }
@@ -449,7 +449,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
 
     /* inherited from parent obj via riscv_cpu_init() */
     cpu->cfg.ext_zifencei = true;
-    cpu->cfg.ext_icsr = true;
+    cpu->cfg.ext_zicsr = true;
     cpu->cfg.pmp = true;
 }
 
@@ -495,7 +495,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
     /* Enable ISA extensions */
     cpu->cfg.mmu = true;
     cpu->cfg.ext_zifencei = true;
-    cpu->cfg.ext_icsr = true;
+    cpu->cfg.ext_zicsr = true;
     cpu->cfg.pmp = true;
     cpu->cfg.ext_icbom = true;
     cpu->cfg.cbom_blocksize = 64;
@@ -567,7 +567,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
 
     /* inherited from parent obj via riscv_cpu_init() */
     cpu->cfg.ext_zifencei = true;
-    cpu->cfg.ext_icsr = true;
+    cpu->cfg.ext_zicsr = true;
     cpu->cfg.mmu = true;
     cpu->cfg.pmp = true;
 }
@@ -585,7 +585,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
 
     /* inherited from parent obj via riscv_cpu_init() */
     cpu->cfg.ext_zifencei = true;
-    cpu->cfg.ext_icsr = true;
+    cpu->cfg.ext_zicsr = true;
     cpu->cfg.pmp = true;
 }
 
@@ -603,7 +603,7 @@ static void rv32_ibex_cpu_init(Object *obj)
 
     /* inherited from parent obj via riscv_cpu_init() */
     cpu->cfg.ext_zifencei = true;
-    cpu->cfg.ext_icsr = true;
+    cpu->cfg.ext_zicsr = true;
     cpu->cfg.pmp = true;
 }
 
@@ -620,7 +620,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
 
     /* inherited from parent obj via riscv_cpu_init() */
     cpu->cfg.ext_zifencei = true;
-    cpu->cfg.ext_icsr = true;
+    cpu->cfg.ext_zicsr = true;
     cpu->cfg.pmp = true;
 }
 #endif
@@ -1243,7 +1243,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Defaults for standard extensions */
     MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
     MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
-    MULTI_EXT_CFG_BOOL("zicsr", ext_icsr, true),
+    MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
     MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
     MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
     MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
@@ -1348,7 +1348,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
 /* Deprecated entries marked for future removal */
 const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
     MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true),
-    MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
+    MULTI_EXT_CFG_BOOL("Zicsr", ext_zicsr, true),
     MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
     MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
     MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index a3f96eb878..9ea30da7e0 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -62,7 +62,7 @@ struct RISCVCPUConfig {
     bool ext_zksh;
     bool ext_zkt;
     bool ext_zifencei;
-    bool ext_icsr;
+    bool ext_zicsr;
     bool ext_icbom;
     bool ext_icboz;
     bool ext_zicond;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4b4ab56c40..30cc21e979 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3858,7 +3858,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
     int csr_min_priv = csr_ops[csrno].min_priv_ver;
 
     /* ensure the CSR extension is enabled */
-    if (!riscv_cpu_cfg(env)->ext_icsr) {
+    if (!riscv_cpu_cfg(env)->ext_zicsr) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 524bede865..58b3ace0fe 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -342,7 +342,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
         g_assert_not_reached();
     }
 
-    if (cpu->cfg.ext_icsr) {
+    if (cpu->cfg.ext_zicsr) {
         int base_reg = cs->gdb_num_regs;
         gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
                                  riscv_gen_dynamic_csr_xml(cs, base_reg),
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 9b8f3f54a7..418b040d6d 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -278,10 +278,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
           riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
           riscv_has_ext(env, RVD) &&
-          cpu->cfg.ext_icsr && cpu->cfg.ext_zifencei)) {
+          cpu->cfg.ext_zicsr && cpu->cfg.ext_zifencei)) {
 
-        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
-            !cpu->cfg.ext_icsr) {
+        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr)) &&
+            !cpu->cfg.ext_zicsr) {
             error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
             return;
         }
@@ -293,7 +293,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
             return;
         }
 
-        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zicsr), true);
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zifencei), true);
 
         env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
@@ -329,7 +329,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
+    if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) {
         error_setg(errp, "F extension requires Zicsr");
         return;
     }
@@ -434,7 +434,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
     }
 
     if (cpu->cfg.ext_zfinx) {
-        if (!cpu->cfg.ext_icsr) {
+        if (!cpu->cfg.ext_zicsr) {
             error_setg(errp, "Zfinx extension requires Zicsr");
             return;
         }
@@ -494,7 +494,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
+    if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) {
         error_setg(errp, "Zcmt extension requires Zicsr extension");
         return;
     }
-- 
2.41.0

[PATCH 3/4] target/riscv: rename ext_icbom to ext_zicbom

[Daniel Henrique Barboza]

Add a leading 'z' to improve grepping. When one wants to search for uses
of zicbom they're more likely to do 'grep -i zicbom' than 'grep -i
icbom'.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 hw/riscv/virt.c                             | 2 +-
 target/riscv/cpu.c                          | 6 +++---
 target/riscv/cpu_cfg.h                      | 2 +-
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 8 ++++----
 target/riscv/kvm/kvm-cpu.c                  | 6 +++---
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 9de578c756..54e0fe8ecc 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -263,7 +263,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
         qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
         g_free(name);
 
-        if (cpu_ptr->cfg.ext_icbom) {
+        if (cpu_ptr->cfg.ext_zicbom) {
             qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size",
                                   cpu_ptr->cfg.cbom_blocksize);
         }
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fdbbafe7b3..c9020653cd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -76,7 +76,7 @@ const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
  * instead.
  */
 const RISCVIsaExtData isa_edata_arr[] = {
-    ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
+    ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom),
     ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
     ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
     ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
@@ -497,7 +497,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
     cpu->cfg.ext_zifencei = true;
     cpu->cfg.ext_zicsr = true;
     cpu->cfg.pmp = true;
-    cpu->cfg.ext_icbom = true;
+    cpu->cfg.ext_zicbom = true;
     cpu->cfg.cbom_blocksize = 64;
     cpu->cfg.cboz_blocksize = 64;
     cpu->cfg.ext_icboz = true;
@@ -1284,7 +1284,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false),
     MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
 
-    MULTI_EXT_CFG_BOOL("zicbom", ext_icbom, true),
+    MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true),
     MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true),
 
     MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 9ea30da7e0..e6bef0070f 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -63,7 +63,7 @@ struct RISCVCPUConfig {
     bool ext_zkt;
     bool ext_zifencei;
     bool ext_zicsr;
-    bool ext_icbom;
+    bool ext_zicbom;
     bool ext_icboz;
     bool ext_zicond;
     bool ext_zihintntl;
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index e5a7704f54..e6ed548376 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -16,10 +16,10 @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#define REQUIRE_ZICBOM(ctx) do {    \
-    if (!ctx->cfg_ptr->ext_icbom) { \
-        return false;               \
-    }                               \
+#define REQUIRE_ZICBOM(ctx) do {     \
+    if (!ctx->cfg_ptr->ext_zicbom) { \
+        return false;                \
+    }                                \
 } while (0)
 
 #define REQUIRE_ZICBOZ(ctx) do {    \
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 090d617627..ad48c9bf30 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -213,7 +213,7 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs)
      .kvm_reg_id = _reg_id}
 
 static KVMCPUConfig kvm_multi_ext_cfgs[] = {
-    KVM_EXT_CFG("zicbom", ext_icbom, KVM_RISCV_ISA_EXT_ZICBOM),
+    KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM),
     KVM_EXT_CFG("zicboz", ext_icboz, KVM_RISCV_ISA_EXT_ZICBOZ),
     KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE),
     KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB),
@@ -804,7 +804,7 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu,
         kvm_cpu_cfg_set(cpu, multi_ext_cfg, val);
     }
 
-    if (cpu->cfg.ext_icbom) {
+    if (cpu->cfg.ext_zicbom) {
         kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
     }
 
@@ -897,7 +897,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
         kvm_cpu_cfg_set(cpu, multi_ext_cfg, val);
     }
 
-    if (cpu->cfg.ext_icbom) {
+    if (cpu->cfg.ext_zicbom) {
         kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
     }
 
-- 
2.41.0

[PATCH 4/4] target/riscv: rename ext_icboz to ext_zicboz

[Daniel Henrique Barboza]

Add a leading 'z' to improve grepping. When one wants to search for uses
of zicboz they're more likely to do 'grep -i zicboz' than 'grep -i
icboz'.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 hw/riscv/virt.c                             | 2 +-
 target/riscv/cpu.c                          | 6 +++---
 target/riscv/cpu_cfg.h                      | 2 +-
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 8 ++++----
 target/riscv/kvm/kvm-cpu.c                  | 6 +++---
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 54e0fe8ecc..1732c42915 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -268,7 +268,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
                                   cpu_ptr->cfg.cbom_blocksize);
         }
 
-        if (cpu_ptr->cfg.ext_icboz) {
+        if (cpu_ptr->cfg.ext_zicboz) {
             qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size",
                                   cpu_ptr->cfg.cboz_blocksize);
         }
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c9020653cd..46a256fccc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -77,7 +77,7 @@ const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
  */
 const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom),
-    ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
+    ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz),
     ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
     ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
     ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei),
@@ -500,7 +500,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
     cpu->cfg.ext_zicbom = true;
     cpu->cfg.cbom_blocksize = 64;
     cpu->cfg.cboz_blocksize = 64;
-    cpu->cfg.ext_icboz = true;
+    cpu->cfg.ext_zicboz = true;
     cpu->cfg.ext_smaia = true;
     cpu->cfg.ext_ssaia = true;
     cpu->cfg.ext_sscofpmf = true;
@@ -1285,7 +1285,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
 
     MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true),
-    MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true),
+    MULTI_EXT_CFG_BOOL("zicboz", ext_zicboz, true),
 
     MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
 
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index e6bef0070f..208cac1c7c 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -64,7 +64,7 @@ struct RISCVCPUConfig {
     bool ext_zifencei;
     bool ext_zicsr;
     bool ext_zicbom;
-    bool ext_icboz;
+    bool ext_zicboz;
     bool ext_zicond;
     bool ext_zihintntl;
     bool ext_zihintpause;
diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index e6ed548376..d5d7095903 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -22,10 +22,10 @@
     }                                \
 } while (0)
 
-#define REQUIRE_ZICBOZ(ctx) do {    \
-    if (!ctx->cfg_ptr->ext_icboz) { \
-        return false;               \
-    }                               \
+#define REQUIRE_ZICBOZ(ctx) do {     \
+    if (!ctx->cfg_ptr->ext_zicboz) { \
+        return false;                \
+    }                                \
 } while (0)
 
 static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index ad48c9bf30..5695f2face 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -214,7 +214,7 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs)
 
 static KVMCPUConfig kvm_multi_ext_cfgs[] = {
     KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM),
-    KVM_EXT_CFG("zicboz", ext_icboz, KVM_RISCV_ISA_EXT_ZICBOZ),
+    KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ),
     KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE),
     KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB),
     KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA),
@@ -808,7 +808,7 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu,
         kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
     }
 
-    if (cpu->cfg.ext_icboz) {
+    if (cpu->cfg.ext_zicboz) {
         kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize);
     }
 }
@@ -901,7 +901,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
         kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
     }
 
-    if (cpu->cfg.ext_icboz) {
+    if (cpu->cfg.ext_zicboz) {
         kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize);
     }
 }
-- 
2.41.0

Re: [PATCH 0/4] target/riscv: rename ext_i* to ext_zi*

[Andrew Jones]

On Thu, Oct 12, 2023 at 01:46:00PM -0300, Daniel Henrique Barboza wrote:
> Hi,
> 
> This series renames the following internal extensions flags:
> 
> ext_ifencei, ext_icsr, ext_icbom, ext_icboz
> 
> To add a leading 'z':
> 
> ext_zifencei, ext_zicsr, ext_zicbom, ext_zicboz
> 
> This was proposed by Andrew Jones. The motivation, in his own words:
> 
> "I'd prefer we name the booleans with their 'z' to improve grepping.
> When one wants to search for uses of zifencei, I imagine they're more
> likely to do 'grep -i zifencei' than 'grep -i ifencei', particularly
> because the 's' is maintained for S extensions. "
> 
> 
> Aside from that, these are the only 4 Z-extension flags that don't use a
> leading 'z' in their name, so there's also the benefit of making
> everything equal.
>

For the series,

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Thanks,
drew

Re: [PATCH 1/4] target/riscv: rename ext_ifencei to ext_zifencei

[Alistair Francis]

On Fri, Oct 13, 2023 at 2:47 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Add a leading 'z' to improve grepping. When one wants to search for uses
> of zifencei they're more likely to do 'grep -i zifencei' than 'grep -i
> ifencei'.
>
> Suggested-by: Andrew Jones <ajones@ventanamicro.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c                      | 22 +++++++++++-----------
>  target/riscv/cpu_cfg.h                  |  2 +-
>  target/riscv/insn_trans/trans_rvi.c.inc |  2 +-
>  target/riscv/tcg/tcg-cpu.c              |  8 ++++----
>  4 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 5425bceac1..caf42ce68d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -80,7 +80,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
>      ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
>      ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
> -    ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
> +    ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei),
>      ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
>      ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
>      ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
> @@ -382,7 +382,7 @@ static void riscv_any_cpu_init(Object *obj)
>      env->priv_ver = PRIV_VERSION_LATEST;
>
>      /* inherited from parent obj via riscv_cpu_init() */
> -    cpu->cfg.ext_ifencei = true;
> +    cpu->cfg.ext_zifencei = true;
>      cpu->cfg.ext_icsr = true;
>      cpu->cfg.mmu = true;
>      cpu->cfg.pmp = true;
> @@ -430,7 +430,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
>  #endif
>
>      /* inherited from parent obj via riscv_cpu_init() */
> -    cpu->cfg.ext_ifencei = true;
> +    cpu->cfg.ext_zifencei = true;
>      cpu->cfg.ext_icsr = true;
>      cpu->cfg.mmu = true;
>      cpu->cfg.pmp = true;
> @@ -448,7 +448,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
>  #endif
>
>      /* inherited from parent obj via riscv_cpu_init() */
> -    cpu->cfg.ext_ifencei = true;
> +    cpu->cfg.ext_zifencei = true;
>      cpu->cfg.ext_icsr = true;
>      cpu->cfg.pmp = true;
>  }
> @@ -494,7 +494,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
>
>      /* Enable ISA extensions */
>      cpu->cfg.mmu = true;
> -    cpu->cfg.ext_ifencei = true;
> +    cpu->cfg.ext_zifencei = true;
>      cpu->cfg.ext_icsr = true;
>      cpu->cfg.pmp = true;
>      cpu->cfg.ext_icbom = true;
> @@ -566,7 +566,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
>  #endif
>
>      /* inherited from parent obj via riscv_cpu_init() */
> -    cpu->cfg.ext_ifencei = true;
> +    cpu->cfg.ext_zifencei = true;
>      cpu->cfg.ext_icsr = true;
>      cpu->cfg.mmu = true;
>      cpu->cfg.pmp = true;
> @@ -584,7 +584,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
>  #endif
>
>      /* inherited from parent obj via riscv_cpu_init() */
> -    cpu->cfg.ext_ifencei = true;
> +    cpu->cfg.ext_zifencei = true;
>      cpu->cfg.ext_icsr = true;
>      cpu->cfg.pmp = true;
>  }
> @@ -602,7 +602,7 @@ static void rv32_ibex_cpu_init(Object *obj)
>      cpu->cfg.epmp = true;
>
>      /* inherited from parent obj via riscv_cpu_init() */
> -    cpu->cfg.ext_ifencei = true;
> +    cpu->cfg.ext_zifencei = true;
>      cpu->cfg.ext_icsr = true;
>      cpu->cfg.pmp = true;
>  }
> @@ -619,7 +619,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
>  #endif
>
>      /* inherited from parent obj via riscv_cpu_init() */
> -    cpu->cfg.ext_ifencei = true;
> +    cpu->cfg.ext_zifencei = true;
>      cpu->cfg.ext_icsr = true;
>      cpu->cfg.pmp = true;
>  }
> @@ -1242,7 +1242,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit)
>  const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>      /* Defaults for standard extensions */
>      MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
> -    MULTI_EXT_CFG_BOOL("zifencei", ext_ifencei, true),
> +    MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
>      MULTI_EXT_CFG_BOOL("zicsr", ext_icsr, true),
>      MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
>      MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
> @@ -1347,7 +1347,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
>
>  /* Deprecated entries marked for future removal */
>  const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
> -    MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
> +    MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true),
>      MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
>      MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
>      MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 0e6a0f245c..a3f96eb878 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -61,7 +61,7 @@ struct RISCVCPUConfig {
>      bool ext_zksed;
>      bool ext_zksh;
>      bool ext_zkt;
> -    bool ext_ifencei;
> +    bool ext_zifencei;
>      bool ext_icsr;
>      bool ext_icbom;
>      bool ext_icboz;
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index 25cb60558a..faf6d65064 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -799,7 +799,7 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a)
>
>  static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
>  {
> -    if (!ctx->cfg_ptr->ext_ifencei) {
> +    if (!ctx->cfg_ptr->ext_zifencei) {
>          return false;
>      }
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index a28918ab30..9b8f3f54a7 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -278,7 +278,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
>            riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
>            riscv_has_ext(env, RVD) &&
> -          cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
> +          cpu->cfg.ext_icsr && cpu->cfg.ext_zifencei)) {
>
>          if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
>              !cpu->cfg.ext_icsr) {
> @@ -286,15 +286,15 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>              return;
>          }
>
> -        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
> -            !cpu->cfg.ext_ifencei) {
> +        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei)) &&
> +            !cpu->cfg.ext_zifencei) {
>              error_setg(errp, "RVG requires Zifencei but user set "
>                         "Zifencei to false");
>              return;
>          }
>
>          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
> -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
> +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zifencei), true);
>
>          env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
>          env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
> --
> 2.41.0
>
>

Re: [PATCH 2/4] target/riscv: rename ext_icsr to ext_zicsr

[Alistair Francis]

On Fri, Oct 13, 2023 at 4:27 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Add a leading 'z' to improve grepping. When one wants to search for uses
> of zicsr they're more likely to do 'grep -i zicsr' than 'grep -i icsr'.
>
> Suggested-by: Andrew Jones <ajones@ventanamicro.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/boot.c            |  2 +-
>  target/riscv/cpu.c         | 22 +++++++++++-----------
>  target/riscv/cpu_cfg.h     |  2 +-
>  target/riscv/csr.c         |  2 +-
>  target/riscv/gdbstub.c     |  2 +-
>  target/riscv/tcg/tcg-cpu.c | 14 +++++++-------
>  6 files changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index 52bf8e67de..0ffca05189 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -414,7 +414,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
>          reset_vec[4] = 0x0182b283;   /*     ld     t0, 24(t0) */
>      }
>
> -    if (!harts->harts[0].cfg.ext_icsr) {
> +    if (!harts->harts[0].cfg.ext_zicsr) {
>          /*
>           * The Zicsr extension has been disabled, so let's ensure we don't
>           * run the CSR instruction. Let's fill the address with a non
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index caf42ce68d..fdbbafe7b3 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -79,7 +79,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
>      ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
>      ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
> -    ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
> +    ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
>      ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei),
>      ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
>      ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
> @@ -383,7 +383,7 @@ static void riscv_any_cpu_init(Object *obj)
>
>      /* inherited from parent obj via riscv_cpu_init() */
>      cpu->cfg.ext_zifencei = true;
> -    cpu->cfg.ext_icsr = true;
> +    cpu->cfg.ext_zicsr = true;
>      cpu->cfg.mmu = true;
>      cpu->cfg.pmp = true;
>  }
> @@ -431,7 +431,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
>
>      /* inherited from parent obj via riscv_cpu_init() */
>      cpu->cfg.ext_zifencei = true;
> -    cpu->cfg.ext_icsr = true;
> +    cpu->cfg.ext_zicsr = true;
>      cpu->cfg.mmu = true;
>      cpu->cfg.pmp = true;
>  }
> @@ -449,7 +449,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
>
>      /* inherited from parent obj via riscv_cpu_init() */
>      cpu->cfg.ext_zifencei = true;
> -    cpu->cfg.ext_icsr = true;
> +    cpu->cfg.ext_zicsr = true;
>      cpu->cfg.pmp = true;
>  }
>
> @@ -495,7 +495,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
>      /* Enable ISA extensions */
>      cpu->cfg.mmu = true;
>      cpu->cfg.ext_zifencei = true;
> -    cpu->cfg.ext_icsr = true;
> +    cpu->cfg.ext_zicsr = true;
>      cpu->cfg.pmp = true;
>      cpu->cfg.ext_icbom = true;
>      cpu->cfg.cbom_blocksize = 64;
> @@ -567,7 +567,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
>
>      /* inherited from parent obj via riscv_cpu_init() */
>      cpu->cfg.ext_zifencei = true;
> -    cpu->cfg.ext_icsr = true;
> +    cpu->cfg.ext_zicsr = true;
>      cpu->cfg.mmu = true;
>      cpu->cfg.pmp = true;
>  }
> @@ -585,7 +585,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
>
>      /* inherited from parent obj via riscv_cpu_init() */
>      cpu->cfg.ext_zifencei = true;
> -    cpu->cfg.ext_icsr = true;
> +    cpu->cfg.ext_zicsr = true;
>      cpu->cfg.pmp = true;
>  }
>
> @@ -603,7 +603,7 @@ static void rv32_ibex_cpu_init(Object *obj)
>
>      /* inherited from parent obj via riscv_cpu_init() */
>      cpu->cfg.ext_zifencei = true;
> -    cpu->cfg.ext_icsr = true;
> +    cpu->cfg.ext_zicsr = true;
>      cpu->cfg.pmp = true;
>  }
>
> @@ -620,7 +620,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
>
>      /* inherited from parent obj via riscv_cpu_init() */
>      cpu->cfg.ext_zifencei = true;
> -    cpu->cfg.ext_icsr = true;
> +    cpu->cfg.ext_zicsr = true;
>      cpu->cfg.pmp = true;
>  }
>  #endif
> @@ -1243,7 +1243,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>      /* Defaults for standard extensions */
>      MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
>      MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
> -    MULTI_EXT_CFG_BOOL("zicsr", ext_icsr, true),
> +    MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
>      MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
>      MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
>      MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
> @@ -1348,7 +1348,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
>  /* Deprecated entries marked for future removal */
>  const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
>      MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true),
> -    MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true),
> +    MULTI_EXT_CFG_BOOL("Zicsr", ext_zicsr, true),
>      MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
>      MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
>      MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index a3f96eb878..9ea30da7e0 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -62,7 +62,7 @@ struct RISCVCPUConfig {
>      bool ext_zksh;
>      bool ext_zkt;
>      bool ext_zifencei;
> -    bool ext_icsr;
> +    bool ext_zicsr;
>      bool ext_icbom;
>      bool ext_icboz;
>      bool ext_zicond;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4b4ab56c40..30cc21e979 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3858,7 +3858,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
>      int csr_min_priv = csr_ops[csrno].min_priv_ver;
>
>      /* ensure the CSR extension is enabled */
> -    if (!riscv_cpu_cfg(env)->ext_icsr) {
> +    if (!riscv_cpu_cfg(env)->ext_zicsr) {
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 524bede865..58b3ace0fe 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -342,7 +342,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
>          g_assert_not_reached();
>      }
>
> -    if (cpu->cfg.ext_icsr) {
> +    if (cpu->cfg.ext_zicsr) {
>          int base_reg = cs->gdb_num_regs;
>          gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
>                                   riscv_gen_dynamic_csr_xml(cs, base_reg),
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 9b8f3f54a7..418b040d6d 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -278,10 +278,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
>            riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
>            riscv_has_ext(env, RVD) &&
> -          cpu->cfg.ext_icsr && cpu->cfg.ext_zifencei)) {
> +          cpu->cfg.ext_zicsr && cpu->cfg.ext_zifencei)) {
>
> -        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
> -            !cpu->cfg.ext_icsr) {
> +        if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr)) &&
> +            !cpu->cfg.ext_zicsr) {
>              error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
>              return;
>          }
> @@ -293,7 +293,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>              return;
>          }
>
> -        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
> +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zicsr), true);
>          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zifencei), true);
>
>          env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
> @@ -329,7 +329,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          return;
>      }
>
> -    if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
> +    if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) {
>          error_setg(errp, "F extension requires Zicsr");
>          return;
>      }
> @@ -434,7 +434,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>      }
>
>      if (cpu->cfg.ext_zfinx) {
> -        if (!cpu->cfg.ext_icsr) {
> +        if (!cpu->cfg.ext_zicsr) {
>              error_setg(errp, "Zfinx extension requires Zicsr");
>              return;
>          }
> @@ -494,7 +494,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          return;
>      }
>
> -    if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
> +    if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) {
>          error_setg(errp, "Zcmt extension requires Zicsr extension");
>          return;
>      }
> --
> 2.41.0
>
>

Re: [PATCH 3/4] target/riscv: rename ext_icbom to ext_zicbom

[Alistair Francis]

On Fri, Oct 13, 2023 at 2:47 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Add a leading 'z' to improve grepping. When one wants to search for uses
> of zicbom they're more likely to do 'grep -i zicbom' than 'grep -i
> icbom'.
>
> Suggested-by: Andrew Jones <ajones@ventanamicro.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/virt.c                             | 2 +-
>  target/riscv/cpu.c                          | 6 +++---
>  target/riscv/cpu_cfg.h                      | 2 +-
>  target/riscv/insn_trans/trans_rvzicbo.c.inc | 8 ++++----
>  target/riscv/kvm/kvm-cpu.c                  | 6 +++---
>  5 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 9de578c756..54e0fe8ecc 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -263,7 +263,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
>          qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
>          g_free(name);
>
> -        if (cpu_ptr->cfg.ext_icbom) {
> +        if (cpu_ptr->cfg.ext_zicbom) {
>              qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size",
>                                    cpu_ptr->cfg.cbom_blocksize);
>          }
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index fdbbafe7b3..c9020653cd 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -76,7 +76,7 @@ const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
>   * instead.
>   */
>  const RISCVIsaExtData isa_edata_arr[] = {
> -    ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
> +    ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom),
>      ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
>      ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
>      ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
> @@ -497,7 +497,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
>      cpu->cfg.ext_zifencei = true;
>      cpu->cfg.ext_zicsr = true;
>      cpu->cfg.pmp = true;
> -    cpu->cfg.ext_icbom = true;
> +    cpu->cfg.ext_zicbom = true;
>      cpu->cfg.cbom_blocksize = 64;
>      cpu->cfg.cboz_blocksize = 64;
>      cpu->cfg.ext_icboz = true;
> @@ -1284,7 +1284,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>      MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false),
>      MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
>
> -    MULTI_EXT_CFG_BOOL("zicbom", ext_icbom, true),
> +    MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true),
>      MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true),
>
>      MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 9ea30da7e0..e6bef0070f 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -63,7 +63,7 @@ struct RISCVCPUConfig {
>      bool ext_zkt;
>      bool ext_zifencei;
>      bool ext_zicsr;
> -    bool ext_icbom;
> +    bool ext_zicbom;
>      bool ext_icboz;
>      bool ext_zicond;
>      bool ext_zihintntl;
> diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
> index e5a7704f54..e6ed548376 100644
> --- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
> @@ -16,10 +16,10 @@
>   * this program.  If not, see <http://www.gnu.org/licenses/>.
>   */
>
> -#define REQUIRE_ZICBOM(ctx) do {    \
> -    if (!ctx->cfg_ptr->ext_icbom) { \
> -        return false;               \
> -    }                               \
> +#define REQUIRE_ZICBOM(ctx) do {     \
> +    if (!ctx->cfg_ptr->ext_zicbom) { \
> +        return false;                \
> +    }                                \
>  } while (0)
>
>  #define REQUIRE_ZICBOZ(ctx) do {    \
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index 090d617627..ad48c9bf30 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -213,7 +213,7 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs)
>       .kvm_reg_id = _reg_id}
>
>  static KVMCPUConfig kvm_multi_ext_cfgs[] = {
> -    KVM_EXT_CFG("zicbom", ext_icbom, KVM_RISCV_ISA_EXT_ZICBOM),
> +    KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM),
>      KVM_EXT_CFG("zicboz", ext_icboz, KVM_RISCV_ISA_EXT_ZICBOZ),
>      KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE),
>      KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB),
> @@ -804,7 +804,7 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu,
>          kvm_cpu_cfg_set(cpu, multi_ext_cfg, val);
>      }
>
> -    if (cpu->cfg.ext_icbom) {
> +    if (cpu->cfg.ext_zicbom) {
>          kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
>      }
>
> @@ -897,7 +897,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
>          kvm_cpu_cfg_set(cpu, multi_ext_cfg, val);
>      }
>
> -    if (cpu->cfg.ext_icbom) {
> +    if (cpu->cfg.ext_zicbom) {
>          kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
>      }
>
> --
> 2.41.0
>
>

Re: [PATCH 4/4] target/riscv: rename ext_icboz to ext_zicboz

[Alistair Francis]

On Fri, Oct 13, 2023 at 4:07 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Add a leading 'z' to improve grepping. When one wants to search for uses
> of zicboz they're more likely to do 'grep -i zicboz' than 'grep -i
> icboz'.
>
> Suggested-by: Andrew Jones <ajones@ventanamicro.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/virt.c                             | 2 +-
>  target/riscv/cpu.c                          | 6 +++---
>  target/riscv/cpu_cfg.h                      | 2 +-
>  target/riscv/insn_trans/trans_rvzicbo.c.inc | 8 ++++----
>  target/riscv/kvm/kvm-cpu.c                  | 6 +++---
>  5 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 54e0fe8ecc..1732c42915 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -268,7 +268,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
>                                    cpu_ptr->cfg.cbom_blocksize);
>          }
>
> -        if (cpu_ptr->cfg.ext_icboz) {
> +        if (cpu_ptr->cfg.ext_zicboz) {
>              qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size",
>                                    cpu_ptr->cfg.cboz_blocksize);
>          }
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c9020653cd..46a256fccc 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -77,7 +77,7 @@ const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
>   */
>  const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom),
> -    ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
> +    ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz),
>      ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
>      ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
>      ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei),
> @@ -500,7 +500,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
>      cpu->cfg.ext_zicbom = true;
>      cpu->cfg.cbom_blocksize = 64;
>      cpu->cfg.cboz_blocksize = 64;
> -    cpu->cfg.ext_icboz = true;
> +    cpu->cfg.ext_zicboz = true;
>      cpu->cfg.ext_smaia = true;
>      cpu->cfg.ext_ssaia = true;
>      cpu->cfg.ext_sscofpmf = true;
> @@ -1285,7 +1285,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>      MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
>
>      MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true),
> -    MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true),
> +    MULTI_EXT_CFG_BOOL("zicboz", ext_zicboz, true),
>
>      MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
>
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index e6bef0070f..208cac1c7c 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -64,7 +64,7 @@ struct RISCVCPUConfig {
>      bool ext_zifencei;
>      bool ext_zicsr;
>      bool ext_zicbom;
> -    bool ext_icboz;
> +    bool ext_zicboz;
>      bool ext_zicond;
>      bool ext_zihintntl;
>      bool ext_zihintpause;
> diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
> index e6ed548376..d5d7095903 100644
> --- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
> @@ -22,10 +22,10 @@
>      }                                \
>  } while (0)
>
> -#define REQUIRE_ZICBOZ(ctx) do {    \
> -    if (!ctx->cfg_ptr->ext_icboz) { \
> -        return false;               \
> -    }                               \
> +#define REQUIRE_ZICBOZ(ctx) do {     \
> +    if (!ctx->cfg_ptr->ext_zicboz) { \
> +        return false;                \
> +    }                                \
>  } while (0)
>
>  static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index ad48c9bf30..5695f2face 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -214,7 +214,7 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs)
>
>  static KVMCPUConfig kvm_multi_ext_cfgs[] = {
>      KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM),
> -    KVM_EXT_CFG("zicboz", ext_icboz, KVM_RISCV_ISA_EXT_ZICBOZ),
> +    KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ),
>      KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE),
>      KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB),
>      KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA),
> @@ -808,7 +808,7 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu,
>          kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
>      }
>
> -    if (cpu->cfg.ext_icboz) {
> +    if (cpu->cfg.ext_zicboz) {
>          kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize);
>      }
>  }
> @@ -901,7 +901,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
>          kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize);
>      }
>
> -    if (cpu->cfg.ext_icboz) {
> +    if (cpu->cfg.ext_zicboz) {
>          kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize);
>      }
>  }
> --
> 2.41.0
>
>

Re: [PATCH 0/4] target/riscv: rename ext_i* to ext_zi*

[Alistair Francis]

On Fri, Oct 13, 2023 at 2:47 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> This series renames the following internal extensions flags:
>
> ext_ifencei, ext_icsr, ext_icbom, ext_icboz
>
> To add a leading 'z':
>
> ext_zifencei, ext_zicsr, ext_zicbom, ext_zicboz
>
> This was proposed by Andrew Jones. The motivation, in his own words:
>
> "I'd prefer we name the booleans with their 'z' to improve grepping.
> When one wants to search for uses of zifencei, I imagine they're more
> likely to do 'grep -i zifencei' than 'grep -i ifencei', particularly
> because the 's' is maintained for S extensions. "
>
>
> Aside from that, these are the only 4 Z-extension flags that don't use a
> leading 'z' in their name, so there's also the benefit of making
> everything equal.
>
>
>
> Daniel Henrique Barboza (4):
>   target/riscv: rename ext_ifencei to ext_zifencei
>   target/riscv: rename ext_icsr to ext_zicsr
>   target/riscv: rename ext_icbom to ext_zicbom
>   target/riscv: rename ext_icboz to ext_zicboz

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  hw/riscv/boot.c                             |  2 +-
>  hw/riscv/virt.c                             |  4 +-
>  target/riscv/cpu.c                          | 56 ++++++++++-----------
>  target/riscv/cpu_cfg.h                      |  8 +--
>  target/riscv/csr.c                          |  2 +-
>  target/riscv/gdbstub.c                      |  2 +-
>  target/riscv/insn_trans/trans_rvi.c.inc     |  2 +-
>  target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 +++---
>  target/riscv/kvm/kvm-cpu.c                  | 12 ++---
>  target/riscv/tcg/tcg-cpu.c                  | 20 ++++----
>  10 files changed, 62 insertions(+), 62 deletions(-)
>
> --
> 2.41.0
>
>