[PATCH v2 00/16] target: Make 'cpu-qom.h' really target agnostic

[PATCH v2 00/16] target: Make 'cpu-qom.h' really target agnostic

[Philippe Mathieu-Daudé]

Since v1:
- Added R-b tags
- Addressed Richard comments
- Postponed OBJECT_DECLARE_CPU_TYPE() changes

A heterogeneous machine must be able to instantiate CPUs
from different architectures. In order to do that, the
common hw/ code has to access to the QOM CPU definitions
from various architecture.

Those QOM definitions are published in "target/foo/cpu-qom.h".
All 'cpu-qom.h' must be target agnostic, so hw/ can include
multiple of them in order to create a heterogeneous machine.

This series strengthen all (except PPC...) target 'cpu-qom.h',
making them target agnostic.

For various targets it is just a matter of moving definitions
where they belong (either 'cpu.h' or 'cpu-qom.h').

For few (mips/riscv/sparc/x86) we have to remove the target
specific definitions (which 'taint' the header as target specific).

For mips/sparc/x86 this implies splitting the base target
definition by making it explicit to the build type (32 or 64-bit).

PPC is missing because CPU types are currently registered
indistinctly, and whether a CPU is 32/64 bit can not be detected
at build time (it is done in each cpu_class_init() handler,
*after* the type is registered).

Based-on: <20231010074952.79165-1-philmd@linaro.org>
  Introduce qtest_get_base_arch() / qtest_get_arch_bits()

Philippe Mathieu-Daudé (16):
  target: Unify QOM style
  target: Mention 'cpu-qom.h' is target agnostic
  target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h'
  target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'
  target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'
  target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'
  target/hexagon: Declare QOM definitions in 'cpu-qom.h'
  target/loongarch: Declare QOM definitions in 'cpu-qom.h'
  target/nios2: Declare QOM definitions in 'cpu-qom.h'
  target/openrisc: Declare QOM definitions in 'cpu-qom.h'
  target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h'
  target: Move ArchCPUClass definition to 'cpu.h'
  target/i386: Declare CPU QOM types using DEFINE_TYPES() macro
  target/mips: Declare CPU QOM types using DEFINE_TYPES() macro
  target/ppc: Declare CPU QOM types using DEFINE_TYPES() macro
  target/sparc: Declare CPU QOM types using DEFINE_TYPES() macro

 target/alpha/cpu-qom.h      | 21 ++-----------
 target/alpha/cpu.h          | 17 ++++++++---
 target/arm/cpu-qom.h        | 61 +------------------------------------
 target/arm/cpu.h            | 55 +++++++++++++++++++++++++++++++--
 target/avr/cpu-qom.h        | 20 ++----------
 target/avr/cpu.h            | 18 ++++++++---
 target/cris/cpu-qom.h       | 24 ++-------------
 target/cris/cpu.h           | 20 +++++++++---
 target/hexagon/cpu-qom.h    | 27 ++++++++++++++++
 target/hexagon/cpu.h        | 20 ++----------
 target/hppa/cpu-qom.h       | 20 +-----------
 target/hppa/cpu.h           | 16 ++++++++--
 target/i386/cpu-qom.h       | 42 ++-----------------------
 target/i386/cpu.h           | 39 +++++++++++++++++++++---
 target/loongarch/cpu-qom.h  | 23 ++++++++++++++
 target/loongarch/cpu.h      | 14 +--------
 target/m68k/cpu-qom.h       | 21 ++-----------
 target/m68k/cpu.h           | 17 ++++++++---
 target/microblaze/cpu-qom.h | 20 +-----------
 target/microblaze/cpu.h     | 15 +++++++--
 target/mips/cpu-qom.h       | 23 ++------------
 target/mips/cpu.h           | 21 ++++++++++---
 target/nios2/cpu-qom.h      | 18 +++++++++++
 target/nios2/cpu.h          | 11 +------
 target/openrisc/cpu-qom.h   | 21 +++++++++++++
 target/openrisc/cpu.h       | 14 +--------
 target/ppc/cpu-qom.h        |  3 +-
 target/ppc/cpu.h            |  4 +--
 target/riscv/cpu-qom.h      | 26 ++--------------
 target/riscv/cpu.h          | 24 +++++++++++++--
 target/rx/cpu-qom.h         | 20 ++----------
 target/rx/cpu.h             | 18 ++++++++---
 target/s390x/cpu-qom.h      | 41 +++----------------------
 target/s390x/cpu.h          | 34 ++++++++++++++++++---
 target/s390x/cpu_models.h   |  8 ++---
 target/sh4/cpu-qom.h        | 28 ++---------------
 target/sh4/cpu.h            | 24 ++++++++++++---
 target/sparc/cpu-qom.h      | 23 ++------------
 target/sparc/cpu.h          | 22 +++++++++----
 target/tricore/cpu-qom.h    | 15 +++------
 target/tricore/cpu.h        | 10 +++---
 target/xtensa/cpu-qom.h     | 26 ++--------------
 target/xtensa/cpu.h         | 24 +++++++++++----
 target/i386/cpu.c           | 50 ++++++++++++++----------------
 target/mips/cpu.c           | 23 ++++++++------
 target/ppc/cpu_init.c       | 52 ++++++++++++++-----------------
 target/sparc/cpu.c          | 23 ++++++++------
 47 files changed, 528 insertions(+), 588 deletions(-)
 create mode 100644 target/hexagon/cpu-qom.h
 create mode 100644 target/loongarch/cpu-qom.h
 create mode 100644 target/nios2/cpu-qom.h
 create mode 100644 target/openrisc/cpu-qom.h

-- 
2.41.0

[PATCH v2 01/16] target: Unify QOM style

[Philippe Mathieu-Daudé]

Enforce the style described by commit 067109a11c ("docs/devel:
mention the spacing requirement for QOM"):

  The first declaration of a storage or class structure should
  always be the parent and leave a visual space between that
  declaration and the new code. It is also useful to separate
  backing for properties (options driven by the user) and internal
  state to make navigation easier.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/alpha/cpu-qom.h      | 2 --
 target/alpha/cpu.h          | 2 --
 target/arm/cpu-qom.h        | 4 ----
 target/arm/cpu.h            | 2 --
 target/avr/cpu-qom.h        | 3 +--
 target/avr/cpu.h            | 2 --
 target/cris/cpu-qom.h       | 2 --
 target/cris/cpu.h           | 2 --
 target/hexagon/cpu.h        | 5 +----
 target/hppa/cpu-qom.h       | 2 --
 target/hppa/cpu.h           | 2 --
 target/i386/cpu-qom.h       | 2 --
 target/i386/cpu.h           | 2 --
 target/loongarch/cpu.h      | 4 ----
 target/m68k/cpu-qom.h       | 2 --
 target/m68k/cpu.h           | 2 --
 target/microblaze/cpu-qom.h | 2 --
 target/microblaze/cpu.h     | 2 --
 target/mips/cpu-qom.h       | 2 --
 target/mips/cpu.h           | 2 --
 target/nios2/cpu.h          | 4 ----
 target/openrisc/cpu.h       | 4 ----
 target/ppc/cpu.h            | 2 --
 target/riscv/cpu-qom.h      | 3 +--
 target/riscv/cpu.h          | 2 --
 target/rx/cpu-qom.h         | 2 --
 target/rx/cpu.h             | 2 --
 target/s390x/cpu-qom.h      | 3 +--
 target/s390x/cpu.h          | 2 --
 target/sh4/cpu-qom.h        | 2 --
 target/sh4/cpu.h            | 2 --
 target/sparc/cpu-qom.h      | 2 --
 target/sparc/cpu.h          | 2 --
 target/tricore/cpu-qom.h    | 2 --
 target/tricore/cpu.h        | 2 --
 target/xtensa/cpu-qom.h     | 2 --
 target/xtensa/cpu.h         | 2 --
 37 files changed, 4 insertions(+), 84 deletions(-)

diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
index 1f200724b6..c5fbd8f11a 100644
--- a/target/alpha/cpu-qom.h
+++ b/target/alpha/cpu-qom.h
@@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
  * An Alpha CPU model.
  */
 struct AlphaCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index e2a467ec17..c8d97ac27a 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -259,9 +259,7 @@ typedef struct CPUArchState {
  * An Alpha CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUAlphaState env;
 
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index d06c08a734..153865d1bb 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -46,9 +46,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info);
  * An ARM CPU model.
  */
 struct ARMCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     const ARMCPUInfo *info;
     DeviceRealize parent_realize;
@@ -62,9 +60,7 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
                        TYPE_AARCH64_CPU)
 
 struct AArch64CPUClass {
-    /*< private >*/
     ARMCPUClass parent_class;
-    /*< public >*/
 };
 
 void register_cp_regs_for_features(ARMCPU *cpu);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a9edfb8353..fb1b08371c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -852,9 +852,7 @@ typedef struct {
  * An ARM CPU core.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUARMState env;
 
diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
index 01ea5f160b..d89be01e0f 100644
--- a/target/avr/cpu-qom.h
+++ b/target/avr/cpu-qom.h
@@ -36,9 +36,8 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
  *  A AVR CPU model.
  */
 struct AVRCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
+
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
 };
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 4ce22d8e4f..f8b065ed79 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -144,9 +144,7 @@ typedef struct CPUArchState {
  *  A AVR CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUAVRState env;
 };
diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h
index 431a1d536a..c2fee242f4 100644
--- a/target/cris/cpu-qom.h
+++ b/target/cris/cpu-qom.h
@@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
  * A CRIS CPU model.
  */
 struct CRISCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 676b8e93ca..6aa445348f 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -174,9 +174,7 @@ typedef struct CPUArchState {
  * A CRIS CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUCRISState env;
 };
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 10cd1efd57..035ac4fb6d 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -130,17 +130,14 @@ typedef struct CPUArchState {
 OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
 
 typedef struct HexagonCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
+
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
 } HexagonCPUClass;
 
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUHexagonState env;
 
diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h
index b96e0318c7..67f12422c4 100644
--- a/target/hppa/cpu-qom.h
+++ b/target/hppa/cpu-qom.h
@@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU)
  * An HPPA CPU model.
  */
 struct HPPACPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 798d0c26d7..518ea94f4f 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -233,9 +233,7 @@ typedef struct CPUArchState {
  * An HPPA CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUHPPAState env;
     QEMUTimer *alarm_timer;
diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index 2350f4ae60..58145717ef 100644
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -47,9 +47,7 @@ typedef struct X86CPUModel X86CPUModel;
  * An x86 CPU model or family.
  */
 struct X86CPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     /* CPU definition, automatically loaded by instance_init if not NULL.
      * Should be eventually replaced by subclass-specific property defaults.
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e1875466b9..a600468698 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1897,9 +1897,7 @@ struct kvm_msrs;
  * An x86 CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUX86State env;
     VMChangeStateEntry *vmsentry;
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 40e70a8119..2b8b828114 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -371,9 +371,7 @@ typedef struct CPUArchState {
  * A LoongArch CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPULoongArchState env;
     QEMUTimer timer;
@@ -398,9 +396,7 @@ OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
  * A LoongArch CPU model.
  */
 struct LoongArchCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
index 0ec7750a92..13d94c9fe3 100644
--- a/target/m68k/cpu-qom.h
+++ b/target/m68k/cpu-qom.h
@@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
  * A Motorola 68k CPU model.
  */
 struct M68kCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 20afb0c94d..9ea18028ad 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -164,9 +164,7 @@ typedef struct CPUArchState {
  * A Motorola 68k CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUM68KState env;
 };
diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
index cda9220fa9..2a734e644d 100644
--- a/target/microblaze/cpu-qom.h
+++ b/target/microblaze/cpu-qom.h
@@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
  * A MicroBlaze CPU model.
  */
 struct MicroBlazeCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e43c49d4af..e8000237d8 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -343,9 +343,7 @@ typedef struct {
  * A MicroBlaze CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUMBState env;
 
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 0dffab453b..c70b4a34be 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -39,9 +39,7 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
  * A MIPS CPU model.
  */
 struct MIPSCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 5fddceff3a..617c373797 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1209,9 +1209,7 @@ typedef struct CPUArchState {
  * A MIPS CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUMIPSState env;
 
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 70b6377a4f..ede1ba2140 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -42,9 +42,7 @@ OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
  * A Nios2 CPU model.
  */
 struct Nios2CPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
@@ -214,9 +212,7 @@ typedef struct {
  * A Nios2 CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUNios2State env;
 
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 334997e9a1..29cda7279c 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -39,9 +39,7 @@ OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
  * A OpenRISC CPU model.
  */
 struct OpenRISCCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
@@ -301,9 +299,7 @@ typedef struct CPUArchState {
  * A OpenRISC CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUOpenRISCState env;
 };
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 4b8b5d3d3e..cf4629036d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1407,9 +1407,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
  * A PowerPC CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUPPCState env;
 
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index f3fbe37a2c..b9164a8e5b 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -63,9 +63,8 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
  * A RISCV CPU model.
  */
 struct RISCVCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
+
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
 };
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f8ffa5ee38..f0dc257a75 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -389,9 +389,7 @@ struct CPUArchState {
  * A RISCV CPU.
  */
 struct ArchCPU {
-    /* < private > */
     CPUState parent_obj;
-    /* < public > */
 
     CPURISCVState env;
 
diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
index 1c8466a187..f4cd5664e5 100644
--- a/target/rx/cpu-qom.h
+++ b/target/rx/cpu-qom.h
@@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
  * A RX CPU model.
  */
 struct RXCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index f66754eb8a..8379f4a150 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -107,9 +107,7 @@ typedef struct CPUArchState {
  * A RX CPU
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPURXState env;
 };
diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
index 00cae2b131..1088965fd5 100644
--- a/target/s390x/cpu-qom.h
+++ b/target/s390x/cpu-qom.h
@@ -49,9 +49,8 @@ typedef enum cpu_reset_type {
  * An S/390 CPU model.
  */
 struct S390CPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
+
     const S390CPUDef *cpu_def;
     bool kvm_required;
     bool is_static;
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 7bea7075e1..e56982dd69 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -166,9 +166,7 @@ static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
  * An S/390 CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUS390XState env;
     S390CPUModel *model;
diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
index 89785a90f0..08fbebc996 100644
--- a/target/sh4/cpu-qom.h
+++ b/target/sh4/cpu-qom.h
@@ -42,9 +42,7 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
  * A SuperH CPU model.
  */
 struct SuperHCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index f75a235973..dc0561b73b 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -204,9 +204,7 @@ typedef struct CPUArchState {
  * A SuperH CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUSH4State env;
 };
diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
index 78bf00b9a2..b4a0db84ce 100644
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@@ -40,9 +40,7 @@ typedef struct sparc_def_t sparc_def_t;
  * A SPARC CPU model.
  */
 struct SPARCCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index b3a98f1d74..691287f134 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -557,9 +557,7 @@ struct CPUArchState {
  * A SPARC CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUSPARCState env;
 };
diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h
index 612731daa0..b3b6c75a3a 100644
--- a/target/tricore/cpu-qom.h
+++ b/target/tricore/cpu-qom.h
@@ -27,9 +27,7 @@
 OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)
 
 struct TriCoreCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index a357b573f2..b4a6ab141d 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -63,9 +63,7 @@ typedef struct CPUArchState {
  * A TriCore CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUTriCoreState env;
 };
diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h
index 419c7d8e4a..424bcbd8dd 100644
--- a/target/xtensa/cpu-qom.h
+++ b/target/xtensa/cpu-qom.h
@@ -47,9 +47,7 @@ typedef struct XtensaConfig XtensaConfig;
  * An Xtensa CPU model.
  */
 struct XtensaCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index c6bbef1e5d..85aab1bdf8 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -556,9 +556,7 @@ struct CPUArchState {
  * An Xtensa CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUXtensaState env;
     Clock *clock;
-- 
2.41.0

[PATCH v2 02/16] target: Mention 'cpu-qom.h' is target agnostic

[Philippe Mathieu-Daudé]

"target/foo/cpu-qom.h" is supposed to be target agnostic
(include-able by any target). Add such mention in the
header.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu-qom.h        | 2 +-
 target/hppa/cpu-qom.h       | 2 +-
 target/microblaze/cpu-qom.h | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index 153865d1bb..dfb9d5b827 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU ARM CPU
+ * QEMU ARM CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h
index 67f12422c4..4b1d48f7ca 100644
--- a/target/hppa/cpu-qom.h
+++ b/target/hppa/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU HPPA CPU
+ * QEMU HPPA CPU QOM header (target agnostic)
  *
  * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
  *
diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
index 2a734e644d..78f549b57d 100644
--- a/target/microblaze/cpu-qom.h
+++ b/target/microblaze/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU MicroBlaze CPU
+ * QEMU MicroBlaze CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
-- 
2.41.0

[PATCH v2 03/16] target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h'

[Philippe Mathieu-Daudé]

These definitions and declarations are only used by
target/arm/, no need to expose them to generic hw/.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/cpu-qom.h | 28 ----------------------------
 target/arm/cpu.h     | 28 ++++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index dfb9d5b827..35c3b0924e 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -35,9 +35,6 @@ typedef struct ARMCPUInfo {
     void (*class_init)(ObjectClass *oc, void *data);
 } ARMCPUInfo;
 
-void arm_cpu_register(const ARMCPUInfo *info);
-void aarch64_cpu_register(const ARMCPUInfo *info);
-
 /**
  * ARMCPUClass:
  * @parent_realize: The parent class' realize handler.
@@ -63,29 +60,4 @@ struct AArch64CPUClass {
     ARMCPUClass parent_class;
 };
 
-void register_cp_regs_for_features(ARMCPU *cpu);
-void init_cpreg_list(ARMCPU *cpu);
-
-/* Callback functions for the generic timer's timers. */
-void arm_gt_ptimer_cb(void *opaque);
-void arm_gt_vtimer_cb(void *opaque);
-void arm_gt_htimer_cb(void *opaque);
-void arm_gt_stimer_cb(void *opaque);
-void arm_gt_hvtimer_cb(void *opaque);
-
-#define ARM_AFF0_SHIFT 0
-#define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
-#define ARM_AFF1_SHIFT 8
-#define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
-#define ARM_AFF2_SHIFT 16
-#define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
-#define ARM_AFF3_SHIFT 32
-#define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
-#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
-
-#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
-#define ARM64_AFFINITY_MASK \
-    (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
-#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
-
 #endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fb1b08371c..06f92dacb9 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1116,11 +1116,39 @@ struct ArchCPU {
     uint64_t gt_cntfrq_hz;
 };
 
+/* Callback functions for the generic timer's timers. */
+void arm_gt_ptimer_cb(void *opaque);
+void arm_gt_vtimer_cb(void *opaque);
+void arm_gt_htimer_cb(void *opaque);
+void arm_gt_stimer_cb(void *opaque);
+void arm_gt_hvtimer_cb(void *opaque);
+
 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
 
 void arm_cpu_post_init(Object *obj);
 
+void arm_cpu_register(const ARMCPUInfo *info);
+void aarch64_cpu_register(const ARMCPUInfo *info);
+
+void register_cp_regs_for_features(ARMCPU *cpu);
+void init_cpreg_list(ARMCPU *cpu);
+
+#define ARM_AFF0_SHIFT 0
+#define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
+#define ARM_AFF1_SHIFT 8
+#define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
+#define ARM_AFF2_SHIFT 16
+#define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
+#define ARM_AFF3_SHIFT 32
+#define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
+#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
+
+#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
+#define ARM64_AFFINITY_MASK \
+    (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
+#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
+
 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
 
 #ifndef CONFIG_USER_ONLY
-- 
2.41.0

[PATCH v2 04/16] target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'

[Philippe Mathieu-Daudé]

CPU_RESOLVING_TYPE is a per-target definition, and is
irrelevant for other targets. Move it to "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/cpu-qom.h | 3 +--
 target/ppc/cpu.h     | 2 ++
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 6d39ad451c..a8e0dcf2de 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU PowerPC CPU
+ * QEMU PowerPC CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -32,7 +32,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU)
 
 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
-#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
 
 #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host")
 
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index cf4629036d..f8101ffa29 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -27,6 +27,8 @@
 #include "qom/object.h"
 #include "hw/registerfields.h"
 
+#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
+
 #define TCG_GUEST_DEFAULT_MO 0
 
 #define TARGET_PAGE_BITS_64K 16
-- 
2.41.0

[PATCH v2 05/16] target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'

[Philippe Mathieu-Daudé]

CPU_RESOLVING_TYPE is a per-target definition, and is
irrelevant for other targets. Move it to "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/cpu-qom.h | 1 -
 target/riscv/cpu.h     | 2 ++
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index b9164a8e5b..b78169093f 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -27,7 +27,6 @@
 
 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
-#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
 
 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
 #define TYPE_RISCV_CPU_MAX              RISCV_CPU_TYPE_NAME("max")
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f0dc257a75..144cc94cce 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -32,6 +32,8 @@
 #include "qapi/qapi-types-common.h"
 #include "cpu-qom.h"
 
+#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
+
 #define TCG_GUEST_DEFAULT_MO 0
 
 /*
-- 
2.41.0

[PATCH v2 06/16] target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'

[Philippe Mathieu-Daudé]

Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME()
macro to resolve target CPU types. Move the declaration
(along with the required FOO_CPU_TYPE_SUFFIX) to "cpu-qom.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/alpha/cpu-qom.h   | 5 ++++-
 target/alpha/cpu.h       | 2 --
 target/avr/cpu-qom.h     | 5 ++++-
 target/avr/cpu.h         | 2 --
 target/cris/cpu-qom.h    | 5 ++++-
 target/cris/cpu.h        | 2 --
 target/i386/cpu-qom.h    | 3 +++
 target/i386/cpu.h        | 2 --
 target/m68k/cpu-qom.h    | 5 ++++-
 target/m68k/cpu.h        | 2 --
 target/mips/cpu-qom.h    | 3 +++
 target/mips/cpu.h        | 2 --
 target/rx/cpu-qom.h      | 5 ++++-
 target/rx/cpu.h          | 2 --
 target/s390x/cpu-qom.h   | 5 ++++-
 target/s390x/cpu.h       | 2 --
 target/sh4/cpu-qom.h     | 5 ++++-
 target/sh4/cpu.h         | 2 --
 target/sparc/cpu-qom.h   | 5 ++++-
 target/sparc/cpu.h       | 2 --
 target/tricore/cpu-qom.h | 5 +++++
 target/tricore/cpu.h     | 2 --
 target/xtensa/cpu-qom.h  | 5 ++++-
 target/xtensa/cpu.h      | 2 --
 24 files changed, 47 insertions(+), 33 deletions(-)

diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
index c5fbd8f11a..c4a4523993 100644
--- a/target/alpha/cpu-qom.h
+++ b/target/alpha/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU Alpha CPU
+ * QEMU Alpha CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -27,6 +27,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
 
+#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
+#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
+
 /**
  * AlphaCPUClass:
  * @parent_realize: The parent class' realize handler.
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index c8d97ac27a..3bff56c565 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -426,8 +426,6 @@ enum {
 
 void alpha_translate_init(void);
 
-#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
-#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
 
 void alpha_cpu_list(void);
diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
index d89be01e0f..75590cdd97 100644
--- a/target/avr/cpu-qom.h
+++ b/target/avr/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU AVR CPU
+ * QEMU AVR CPU QOM header (target agnostic)
  *
  * Copyright (c) 2016-2020 Michael Rolnik
  *
@@ -28,6 +28,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
 
+#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
+#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
+
 /**
  *  AVRCPUClass:
  *  @parent_realize: The parent class' realize handler.
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index f8b065ed79..0487399cb2 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -28,8 +28,6 @@
 #error "AVR 8-bit does not support user mode"
 #endif
 
-#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
-#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
 #define CPU_RESOLVING_TYPE TYPE_AVR_CPU
 
 #define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h
index c2fee242f4..d7e5f33e62 100644
--- a/target/cris/cpu-qom.h
+++ b/target/cris/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU CRIS CPU
+ * QEMU CRIS CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -27,6 +27,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
 
+#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
+#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
+
 /**
  * CRISCPUClass:
  * @parent_realize: The parent class' realize handler.
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 6aa445348f..b821bb7983 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -240,8 +240,6 @@ enum {
 /* CRIS uses 8k pages.  */
 #define MMAP_SHIFT TARGET_PAGE_BITS
 
-#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
-#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
 #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
 
 /* MMU modes definitions */
diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index 58145717ef..dffc74c1ce 100644
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -32,6 +32,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
 
+#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
+#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
+
 typedef struct X86CPUModel X86CPUModel;
 
 /**
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index a600468698..2dea4df086 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2239,8 +2239,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
 /* hw/pc.c */
 uint64_t cpu_get_tsc(CPUX86State *env);
 
-#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
-#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
 
 #ifdef TARGET_X86_64
diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
index 13d94c9fe3..df0cc8b7a3 100644
--- a/target/m68k/cpu-qom.h
+++ b/target/m68k/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU Motorola 68k CPU
+ * QEMU Motorola 68k CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -27,6 +27,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
 
+#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
+#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
+
 /*
  * M68kCPUClass:
  * @parent_realize: The parent class' realize handler.
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 9ea18028ad..7f34686a6f 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -561,8 +561,6 @@ enum {
     ACCESS_DATA  = 0x20, /* Data load/store access        */
 };
 
-#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
-#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_M68K_CPU
 
 #define cpu_list m68k_cpu_list
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index c70b4a34be..5822dfb1d2 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -31,6 +31,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
 
+#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
+#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
+
 /**
  * MIPSCPUClass:
  * @parent_realize: The parent class' realize handler.
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 617c373797..12cc1bfafd 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1301,8 +1301,6 @@ enum {
  */
 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
 
-#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
-#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
 
 bool cpu_type_supports_cps_smp(const char *cpu_type);
diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
index f4cd5664e5..6213d877f7 100644
--- a/target/rx/cpu-qom.h
+++ b/target/rx/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * RX CPU
+ * QEMU RX CPU QOM header (target agnostic)
  *
  * Copyright (c) 2019 Yoshinori Sato
  *
@@ -28,6 +28,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
 
+#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
+#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
+
 /*
  * RXCPUClass:
  * @parent_realize: The parent class' realize handler.
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 8379f4a150..c81613770c 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -112,8 +112,6 @@ struct ArchCPU {
     CPURXState env;
 };
 
-#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
-#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_RX_CPU
 
 const char *rx_crname(uint8_t cr);
diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
index 1088965fd5..fcd70daddf 100644
--- a/target/s390x/cpu-qom.h
+++ b/target/s390x/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU S/390 CPU
+ * QEMU S/390 CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -27,6 +27,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU)
 
+#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
+#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
+
 typedef struct S390CPUModel S390CPUModel;
 typedef struct S390CPUDef S390CPUDef;
 
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index e56982dd69..988e2954a4 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -808,8 +808,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
 
 
 /* helper.c */
-#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
-#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
 #define CPU_RESOLVING_TYPE TYPE_S390_CPU
 
 /* interrupt.c */
diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
index 08fbebc996..bd0ef49fa1 100644
--- a/target/sh4/cpu-qom.h
+++ b/target/sh4/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU SuperH CPU
+ * QEMU SuperH CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -31,6 +31,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
 
+#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
+#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
+
 /**
  * SuperHCPUClass:
  * @parent_realize: The parent class' realize handler.
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index dc0561b73b..dbe00e29c2 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -250,8 +250,6 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
 
 void cpu_load_tlb(CPUSH4State * env);
 
-#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
-#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU
 
 #define cpu_list sh4_cpu_list
diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
index b4a0db84ce..aca29415b4 100644
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU SPARC CPU
+ * QEMU SPARC CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  *
@@ -31,6 +31,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
 
+#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
+#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
+
 typedef struct sparc_def_t sparc_def_t;
 /**
  * SPARCCPUClass:
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 691287f134..31772c9b73 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -648,8 +648,6 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
 #endif
 #endif
 
-#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
-#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU
 
 #define cpu_list sparc_cpu_list
diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h
index b3b6c75a3a..2598651008 100644
--- a/target/tricore/cpu-qom.h
+++ b/target/tricore/cpu-qom.h
@@ -1,4 +1,6 @@
 /*
+ * QEMU TriCore CPU QOM header (target agnostic)
+ *
  *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
  *
  * This library is free software; you can redistribute it and/or
@@ -26,6 +28,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)
 
+#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
+#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
+
 struct TriCoreCPUClass {
     CPUClass parent_class;
 
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index b4a6ab141d..c537a33ee8 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -268,8 +268,6 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc,
     *flags = new_flags;
 }
 
-#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
-#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU
 
 /* helpers.c */
diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h
index 424bcbd8dd..03873ea50b 100644
--- a/target/xtensa/cpu-qom.h
+++ b/target/xtensa/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU Xtensa CPU
+ * QEMU Xtensa CPU QOM header (target agnostic)
  *
  * Copyright (c) 2012 SUSE LINUX Products GmbH
  * All rights reserved.
@@ -36,6 +36,9 @@
 
 OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU)
 
+#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
+#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
+
 typedef struct XtensaConfig XtensaConfig;
 
 /**
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 85aab1bdf8..d6d2fb1f4e 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -586,8 +586,6 @@ G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 
 #define cpu_list xtensa_cpu_list
 
-#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
-#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
 
 #if TARGET_BIG_ENDIAN
-- 
2.41.0

[PATCH v2 07/16] target/hexagon: Declare QOM definitions in 'cpu-qom.h'

[Philippe Mathieu-Daudé]

"target/foo/cpu.h" contains the target specific declarations.

A heterogeneous setup need to access target agnostic declarations
(at least the QOM ones, to instantiate the objects).

Our convention is to add such target agnostic QOM declarations in
the "target/foo/cpu-qom.h" header.

Extract QOM definitions from "cpu.h" to "cpu-qom.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/hexagon/cpu-qom.h | 28 ++++++++++++++++++++++++++++
 target/hexagon/cpu.h     | 15 +--------------
 2 files changed, 29 insertions(+), 14 deletions(-)
 create mode 100644 target/hexagon/cpu-qom.h

diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h
new file mode 100644
index 0000000000..f02df7ee6f
--- /dev/null
+++ b/target/hexagon/cpu-qom.h
@@ -0,0 +1,28 @@
+/*
+ * QEMU Hexagon CPU QOM header (target agnostic)
+ *
+ * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef QEMU_HEXAGON_CPU_QOM_H
+#define QEMU_HEXAGON_CPU_QOM_H
+
+#include "hw/core/cpu.h"
+#include "qom/object.h"
+
+#define TYPE_HEXAGON_CPU "hexagon-cpu"
+
+#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
+#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
+
+#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
+#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
+#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
+#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
+#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
+
+OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
+
+#endif
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 035ac4fb6d..7d16083c6a 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -20,11 +20,10 @@
 
 #include "fpu/softfloat-types.h"
 
+#include "cpu-qom.h"
 #include "exec/cpu-defs.h"
 #include "hex_regs.h"
 #include "mmvec/mmvec.h"
-#include "qom/object.h"
-#include "hw/core/cpu.h"
 #include "hw/registerfields.h"
 
 #define NUM_PREGS 4
@@ -36,18 +35,8 @@
 #define PRED_WRITES_MAX 5                   /* 4 insns + endloop */
 #define VSTORES_MAX 2
 
-#define TYPE_HEXAGON_CPU "hexagon-cpu"
-
-#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
-#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU
 
-#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
-#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
-#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
-#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
-#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
-
 void hexagon_cpu_list(void);
 #define cpu_list hexagon_cpu_list
 
@@ -127,8 +116,6 @@ typedef struct CPUArchState {
     VTCMStoreLog vtcm_log;
 } CPUHexagonState;
 
-OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
-
 typedef struct HexagonCPUClass {
     CPUClass parent_class;
 
-- 
2.41.0

[PATCH v2 08/16] target/loongarch: Declare QOM definitions in 'cpu-qom.h'

[Philippe Mathieu-Daudé]

"target/foo/cpu.h" contains the target specific declarations.

A heterogeneous setup need to access target agnostic declarations
(at least the QOM ones, to instantiate the objects).

Our convention is to add such target agnostic QOM declarations in
the "target/foo/cpu-qom.h" header.

Extract QOM definitions from "cpu.h" to "cpu-qom.h".

Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/loongarch/cpu-qom.h | 24 ++++++++++++++++++++++++
 target/loongarch/cpu.h     | 10 +---------
 2 files changed, 25 insertions(+), 9 deletions(-)
 create mode 100644 target/loongarch/cpu-qom.h

diff --git a/target/loongarch/cpu-qom.h b/target/loongarch/cpu-qom.h
new file mode 100644
index 0000000000..82c86d146d
--- /dev/null
+++ b/target/loongarch/cpu-qom.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch CPU QOM header (target agnostic)
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_CPU_QOM_H
+#define LOONGARCH_CPU_QOM_H
+
+#include "hw/core/cpu.h"
+#include "qom/object.h"
+
+#define TYPE_LOONGARCH_CPU "loongarch-cpu"
+#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
+#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
+
+OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
+                        LOONGARCH_CPU)
+
+#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
+#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
+
+#endif
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 2b8b828114..2b759aba5e 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -17,6 +17,7 @@
 #include "exec/memory.h"
 #endif
 #include "cpu-csr.h"
+#include "cpu-qom.h"
 
 #define IOCSRF_TEMP             0
 #define IOCSRF_NODECNT          1
@@ -381,13 +382,6 @@ struct ArchCPU {
     const char *dtb_compatible;
 };
 
-#define TYPE_LOONGARCH_CPU "loongarch-cpu"
-#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
-#define TYPE_LOONGARCH64_CPU "loongarch64-cpu"
-
-OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
-                        LOONGARCH_CPU)
-
 /**
  * LoongArchCPUClass:
  * @parent_realize: The parent class' realize handler.
@@ -478,8 +472,6 @@ void loongarch_cpu_list(void);
 
 #include "exec/cpu-all.h"
 
-#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU
-#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
 
 #endif /* LOONGARCH_CPU_H */
-- 
2.41.0

[PATCH v2 09/16] target/nios2: Declare QOM definitions in 'cpu-qom.h'

[Philippe Mathieu-Daudé]

"target/foo/cpu.h" contains the target specific declarations.

A heterogeneous setup need to access target agnostic declarations
(at least the QOM ones, to instantiate the objects).

Our convention is to add such target agnostic QOM declarations in
the "target/foo/cpu-qom.h" header.

Extract QOM definitions from "cpu.h" to "cpu-qom.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/nios2/cpu-qom.h | 19 +++++++++++++++++++
 target/nios2/cpu.h     |  7 +------
 2 files changed, 20 insertions(+), 6 deletions(-)
 create mode 100644 target/nios2/cpu-qom.h

diff --git a/target/nios2/cpu-qom.h b/target/nios2/cpu-qom.h
new file mode 100644
index 0000000000..931bc69b10
--- /dev/null
+++ b/target/nios2/cpu-qom.h
@@ -0,0 +1,19 @@
+/*
+ * QEMU Nios II CPU QOM header (target agnostic)
+ *
+ * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef QEMU_NIOS2_CPU_QOM_H
+#define QEMU_NIOS2_CPU_QOM_H
+
+#include "hw/core/cpu.h"
+#include "qom/object.h"
+
+#define TYPE_NIOS2_CPU "nios2-cpu"
+
+OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
+
+#endif
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index ede1ba2140..2d79b5b298 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -21,20 +21,15 @@
 #ifndef NIOS2_CPU_H
 #define NIOS2_CPU_H
 
+#include "cpu-qom.h"
 #include "exec/cpu-defs.h"
-#include "hw/core/cpu.h"
 #include "hw/registerfields.h"
-#include "qom/object.h"
 
 typedef struct CPUArchState CPUNios2State;
 #if !defined(CONFIG_USER_ONLY)
 #include "mmu.h"
 #endif
 
-#define TYPE_NIOS2_CPU "nios2-cpu"
-
-OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
-
 /**
  * Nios2CPUClass:
  * @parent_phases: The parent class' reset phase handlers.
-- 
2.41.0

[PATCH v2 10/16] target/openrisc: Declare QOM definitions in 'cpu-qom.h'

[Philippe Mathieu-Daudé]

"target/foo/cpu.h" contains the target specific declarations.

A heterogeneous setup need to access target agnostic declarations
(at least the QOM ones, to instantiate the objects).

Our convention is to add such target agnostic QOM declarations in
the "target/foo/cpu-qom.h" header.

Extract QOM definitions from "cpu.h" to "cpu-qom.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/openrisc/cpu-qom.h | 22 ++++++++++++++++++++++
 target/openrisc/cpu.h     | 10 +---------
 2 files changed, 23 insertions(+), 9 deletions(-)
 create mode 100644 target/openrisc/cpu-qom.h

diff --git a/target/openrisc/cpu-qom.h b/target/openrisc/cpu-qom.h
new file mode 100644
index 0000000000..1ba9fb0a4c
--- /dev/null
+++ b/target/openrisc/cpu-qom.h
@@ -0,0 +1,22 @@
+/*
+ * QEMU OpenRISC CPU QOM header (target agnostic)
+ *
+ * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef QEMU_OPENRISC_CPU_QOM_H
+#define QEMU_OPENRISC_CPU_QOM_H
+
+#include "hw/core/cpu.h"
+#include "qom/object.h"
+
+#define TYPE_OPENRISC_CPU "or1k-cpu"
+
+OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
+
+#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU
+#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
+
+#endif
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 29cda7279c..dedeb89f8e 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -20,17 +20,12 @@
 #ifndef OPENRISC_CPU_H
 #define OPENRISC_CPU_H
 
+#include "cpu-qom.h"
 #include "exec/cpu-defs.h"
 #include "fpu/softfloat-types.h"
-#include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TCG_GUEST_DEFAULT_MO (0)
 
-#define TYPE_OPENRISC_CPU "or1k-cpu"
-
-OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
-
 /**
  * OpenRISCCPUClass:
  * @parent_realize: The parent class' realize handler.
@@ -304,7 +299,6 @@ struct ArchCPU {
     CPUOpenRISCState env;
 };
 
-
 void cpu_openrisc_list(void);
 void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -339,8 +333,6 @@ void cpu_openrisc_count_start(OpenRISCCPU *cpu);
 void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
 #endif
 
-#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU
-#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
 #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
 
 #include "exec/cpu-all.h"
-- 
2.41.0

[PATCH v2 11/16] target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h'

[Philippe Mathieu-Daudé]

TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64
definitions which are target specific. Such target specific
definition taints "cpu-qom.h".

Since "cpu-qom.h" must be target agnostic, remove its target
specific definition uses by moving TYPE_RISCV_CPU_BASE to
"target/riscv/cpu.h".

"target/riscv/cpu-qom.h" is now fully target agnostic.

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/cpu-qom.h | 8 +-------
 target/riscv/cpu.h     | 6 ++++++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index b78169093f..76efb614a6 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -1,5 +1,5 @@
 /*
- * QEMU RISC-V CPU QOM header
+ * QEMU RISC-V CPU QOM header (target agnostic)
  *
  * Copyright (c) 2023 Ventana Micro Systems Inc.
  *
@@ -44,12 +44,6 @@
 #define TYPE_RISCV_CPU_VEYRON_V1        RISCV_CPU_TYPE_NAME("veyron-v1")
 #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
 
-#if defined(TARGET_RISCV32)
-# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
-#elif defined(TARGET_RISCV64)
-# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
-#endif
-
 typedef struct CPUArchState CPURISCVState;
 
 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 144cc94cce..d832696418 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -34,6 +34,12 @@
 
 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
 
+#if defined(TARGET_RISCV32)
+# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
+#elif defined(TARGET_RISCV64)
+# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
+#endif
+
 #define TCG_GUEST_DEFAULT_MO 0
 
 /*
-- 
2.41.0

[PATCH v2 12/16] target: Move ArchCPUClass definition to 'cpu.h'

[Philippe Mathieu-Daudé]

The OBJECT_DECLARE_CPU_TYPE() macro forward-declares each
ArchCPUClass type. These forward declarations are sufficient
for code in hw/ to use the QOM definitions. No need to expose
these structure definitions. Keep each local to their target/
by moving them to the corresponding "cpu.h" header.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/alpha/cpu-qom.h      | 16 ---------------
 target/alpha/cpu.h          | 13 +++++++++++++
 target/arm/cpu-qom.h        | 27 -------------------------
 target/arm/cpu.h            | 25 ++++++++++++++++++++++++
 target/avr/cpu-qom.h        | 16 ---------------
 target/avr/cpu.h            | 14 +++++++++++++
 target/cris/cpu-qom.h       | 19 ------------------
 target/cris/cpu.h           | 16 +++++++++++++++
 target/hexagon/cpu-qom.h    |  1 -
 target/hppa/cpu-qom.h       | 16 ---------------
 target/hppa/cpu.h           | 14 +++++++++++++
 target/i386/cpu-qom.h       | 39 -------------------------------------
 target/i386/cpu.h           | 35 +++++++++++++++++++++++++++++++++
 target/loongarch/cpu-qom.h  |  1 -
 target/m68k/cpu-qom.h       | 16 ---------------
 target/m68k/cpu.h           | 13 +++++++++++++
 target/microblaze/cpu-qom.h | 16 ---------------
 target/microblaze/cpu.h     | 13 +++++++++++++
 target/mips/cpu-qom.h       | 20 -------------------
 target/mips/cpu.h           | 17 ++++++++++++++++
 target/nios2/cpu-qom.h      |  1 -
 target/openrisc/cpu-qom.h   |  1 -
 target/riscv/cpu-qom.h      | 16 +--------------
 target/riscv/cpu.h          | 14 +++++++++++++
 target/rx/cpu-qom.h         | 15 --------------
 target/rx/cpu.h             | 14 +++++++++++++
 target/s390x/cpu-qom.h      | 37 +----------------------------------
 target/s390x/cpu.h          | 30 ++++++++++++++++++++++++++++
 target/s390x/cpu_models.h   |  8 ++++----
 target/sh4/cpu-qom.h        | 23 ----------------------
 target/sh4/cpu.h            | 20 +++++++++++++++++++
 target/sparc/cpu-qom.h      | 18 -----------------
 target/sparc/cpu.h          | 18 +++++++++++++++--
 target/tricore/cpu-qom.h    | 10 ----------
 target/tricore/cpu.h        |  6 ++++++
 target/xtensa/cpu-qom.h     | 21 --------------------
 target/xtensa/cpu.h         | 20 +++++++++++++++++--
 37 files changed, 284 insertions(+), 335 deletions(-)

diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
index c4a4523993..1b32b18d34 100644
--- a/target/alpha/cpu-qom.h
+++ b/target/alpha/cpu-qom.h
@@ -21,7 +21,6 @@
 #define QEMU_ALPHA_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_ALPHA_CPU "alpha-cpu"
 
@@ -30,19 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
 #define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
 #define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
 
-/**
- * AlphaCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
- *
- * An Alpha CPU model.
- */
-struct AlphaCPUClass {
-    CPUClass parent_class;
-
-    DeviceRealize parent_realize;
-    DeviceReset parent_reset;
-};
-
-
 #endif
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 3bff56c565..d672e911dd 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -267,6 +267,19 @@ struct ArchCPU {
     QEMUTimer *alarm_timer;
 };
 
+/**
+ * AlphaCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_reset: The parent class' reset handler.
+ *
+ * An Alpha CPU model.
+ */
+struct AlphaCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    DeviceReset parent_reset;
+};
 
 #ifndef CONFIG_USER_ONLY
 extern const VMStateDescription vmstate_alpha_cpu;
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index 35c3b0924e..02b914c876 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -21,7 +21,6 @@
 #define QEMU_ARM_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_ARM_CPU "arm-cpu"
 
@@ -29,35 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
 
 #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
 
-typedef struct ARMCPUInfo {
-    const char *name;
-    void (*initfn)(Object *obj);
-    void (*class_init)(ObjectClass *oc, void *data);
-} ARMCPUInfo;
-
-/**
- * ARMCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * An ARM CPU model.
- */
-struct ARMCPUClass {
-    CPUClass parent_class;
-
-    const ARMCPUInfo *info;
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-};
-
-
 #define TYPE_AARCH64_CPU "aarch64-cpu"
 typedef struct AArch64CPUClass AArch64CPUClass;
 DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
                        TYPE_AARCH64_CPU)
 
-struct AArch64CPUClass {
-    ARMCPUClass parent_class;
-};
-
 #endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 06f92dacb9..ad2f32efd5 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1116,6 +1116,31 @@ struct ArchCPU {
     uint64_t gt_cntfrq_hz;
 };
 
+typedef struct ARMCPUInfo {
+    const char *name;
+    void (*initfn)(Object *obj);
+    void (*class_init)(ObjectClass *oc, void *data);
+} ARMCPUInfo;
+
+/**
+ * ARMCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * An ARM CPU model.
+ */
+struct ARMCPUClass {
+    CPUClass parent_class;
+
+    const ARMCPUInfo *info;
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
+
+struct AArch64CPUClass {
+    ARMCPUClass parent_class;
+};
+
 /* Callback functions for the generic timer's timers. */
 void arm_gt_ptimer_cb(void *opaque);
 void arm_gt_vtimer_cb(void *opaque);
diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
index 75590cdd97..38dbcc0535 100644
--- a/target/avr/cpu-qom.h
+++ b/target/avr/cpu-qom.h
@@ -22,7 +22,6 @@
 #define TARGET_AVR_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_AVR_CPU "avr-cpu"
 
@@ -31,19 +30,4 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
 #define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
 #define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
 
-/**
- *  AVRCPUClass:
- *  @parent_realize: The parent class' realize handler.
- *  @parent_phases: The parent class' reset phase handlers.
- *
- *  A AVR CPU model.
- */
-struct AVRCPUClass {
-    CPUClass parent_class;
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-};
-
-
 #endif /* TARGET_AVR_CPU_QOM_H */
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 0487399cb2..8a17862737 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -147,6 +147,20 @@ struct ArchCPU {
     CPUAVRState env;
 };
 
+/**
+ *  AVRCPUClass:
+ *  @parent_realize: The parent class' realize handler.
+ *  @parent_phases: The parent class' reset phase handlers.
+ *
+ *  A AVR CPU model.
+ */
+struct AVRCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
+
 extern const struct VMStateDescription vms_avr_cpu;
 
 void avr_cpu_do_interrupt(CPUState *cpu);
diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h
index d7e5f33e62..741ca97a1b 100644
--- a/target/cris/cpu-qom.h
+++ b/target/cris/cpu-qom.h
@@ -21,7 +21,6 @@
 #define QEMU_CRIS_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_CRIS_CPU "cris-cpu"
 
@@ -30,22 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
 #define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
 #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
 
-/**
- * CRISCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- * @vr: Version Register value.
- *
- * A CRIS CPU model.
- */
-struct CRISCPUClass {
-    CPUClass parent_class;
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-
-    uint32_t vr;
-};
-
-
 #endif
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index b821bb7983..1be7f90319 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -179,6 +179,22 @@ struct ArchCPU {
     CPUCRISState env;
 };
 
+/**
+ * CRISCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ * @vr: Version Register value.
+ *
+ * A CRIS CPU model.
+ */
+struct CRISCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+
+    uint32_t vr;
+};
 
 #ifndef CONFIG_USER_ONLY
 extern const VMStateDescription vmstate_cris_cpu;
diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h
index f02df7ee6f..da92fe7468 100644
--- a/target/hexagon/cpu-qom.h
+++ b/target/hexagon/cpu-qom.h
@@ -10,7 +10,6 @@
 #define QEMU_HEXAGON_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_HEXAGON_CPU "hexagon-cpu"
 
diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h
index 4b1d48f7ca..7270e93e6b 100644
--- a/target/hppa/cpu-qom.h
+++ b/target/hppa/cpu-qom.h
@@ -21,25 +21,9 @@
 #define QEMU_HPPA_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_HPPA_CPU "hppa-cpu"
 
 OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU)
 
-/**
- * HPPACPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
- *
- * An HPPA CPU model.
- */
-struct HPPACPUClass {
-    CPUClass parent_class;
-
-    DeviceRealize parent_realize;
-    DeviceReset parent_reset;
-};
-
-
 #endif
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 518ea94f4f..0a0c7366c2 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -239,6 +239,20 @@ struct ArchCPU {
     QEMUTimer *alarm_timer;
 };
 
+/**
+ * HPPACPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_reset: The parent class' reset handler.
+ *
+ * An HPPA CPU model.
+ */
+struct HPPACPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    DeviceReset parent_reset;
+};
+
 #include "exec/cpu-all.h"
 
 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index dffc74c1ce..d4e216d000 100644
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -21,8 +21,6 @@
 #define QEMU_I386_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qemu/notify.h"
-#include "qom/object.h"
 
 #ifdef TARGET_X86_64
 #define TYPE_X86_CPU "x86_64-cpu"
@@ -35,41 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
 
-typedef struct X86CPUModel X86CPUModel;
-
-/**
- * X86CPUClass:
- * @cpu_def: CPU model definition
- * @host_cpuid_required: Whether CPU model requires cpuid from host.
- * @ordering: Ordering on the "-cpu help" CPU model list.
- * @migration_safe: See CpuDefinitionInfo::migration_safe
- * @static_model: See CpuDefinitionInfo::static
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * An x86 CPU model or family.
- */
-struct X86CPUClass {
-    CPUClass parent_class;
-
-    /* CPU definition, automatically loaded by instance_init if not NULL.
-     * Should be eventually replaced by subclass-specific property defaults.
-     */
-    X86CPUModel *model;
-
-    bool host_cpuid_required;
-    int ordering;
-    bool migration_safe;
-    bool static_model;
-
-    /* Optional description of CPU model.
-     * If unavailable, cpu_def->model_id is used */
-    const char *model_description;
-
-    DeviceRealize parent_realize;
-    DeviceUnrealize parent_unrealize;
-    ResettablePhases parent_phases;
-};
-
-
 #endif
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2dea4df086..e21d293daa 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2037,6 +2037,41 @@ struct ArchCPU {
     bool xen_vapic;
 };
 
+typedef struct X86CPUModel X86CPUModel;
+
+/**
+ * X86CPUClass:
+ * @cpu_def: CPU model definition
+ * @host_cpuid_required: Whether CPU model requires cpuid from host.
+ * @ordering: Ordering on the "-cpu help" CPU model list.
+ * @migration_safe: See CpuDefinitionInfo::migration_safe
+ * @static_model: See CpuDefinitionInfo::static
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * An x86 CPU model or family.
+ */
+struct X86CPUClass {
+    CPUClass parent_class;
+
+    /* CPU definition, automatically loaded by instance_init if not NULL.
+     * Should be eventually replaced by subclass-specific property defaults.
+     */
+    X86CPUModel *model;
+
+    bool host_cpuid_required;
+    int ordering;
+    bool migration_safe;
+    bool static_model;
+
+    /* Optional description of CPU model.
+     * If unavailable, cpu_def->model_id is used */
+    const char *model_description;
+
+    DeviceRealize parent_realize;
+    DeviceUnrealize parent_unrealize;
+    ResettablePhases parent_phases;
+};
 
 #ifndef CONFIG_USER_ONLY
 extern const VMStateDescription vmstate_x86_cpu;
diff --git a/target/loongarch/cpu-qom.h b/target/loongarch/cpu-qom.h
index 82c86d146d..fa3fcf7186 100644
--- a/target/loongarch/cpu-qom.h
+++ b/target/loongarch/cpu-qom.h
@@ -9,7 +9,6 @@
 #define LOONGARCH_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_LOONGARCH_CPU "loongarch-cpu"
 #define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
index df0cc8b7a3..273e8eae41 100644
--- a/target/m68k/cpu-qom.h
+++ b/target/m68k/cpu-qom.h
@@ -21,7 +21,6 @@
 #define QEMU_M68K_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_M68K_CPU "m68k-cpu"
 
@@ -30,19 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
 #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
 #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
 
-/*
- * M68kCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A Motorola 68k CPU model.
- */
-struct M68kCPUClass {
-    CPUClass parent_class;
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-};
-
-
 #endif
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 7f34686a6f..6cfc696d2b 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -169,6 +169,19 @@ struct ArchCPU {
     CPUM68KState env;
 };
 
+/*
+ * M68kCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A Motorola 68k CPU model.
+ */
+struct M68kCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
 
 #ifndef CONFIG_USER_ONLY
 void m68k_cpu_do_interrupt(CPUState *cpu);
diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
index 78f549b57d..92e539fb2f 100644
--- a/target/microblaze/cpu-qom.h
+++ b/target/microblaze/cpu-qom.h
@@ -21,25 +21,9 @@
 #define QEMU_MICROBLAZE_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_MICROBLAZE_CPU "microblaze-cpu"
 
 OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
 
-/**
- * MicroBlazeCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A MicroBlaze CPU model.
- */
-struct MicroBlazeCPUClass {
-    CPUClass parent_class;
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-};
-
-
 #endif
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e8000237d8..b5374365f5 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -355,6 +355,19 @@ struct ArchCPU {
     MicroBlazeCPUConfig cfg;
 };
 
+/**
+ * MicroBlazeCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A MicroBlaze CPU model.
+ */
+struct MicroBlazeCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
 
 #ifndef CONFIG_USER_ONLY
 void mb_cpu_do_interrupt(CPUState *cs);
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 5822dfb1d2..0eea2a2598 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -21,7 +21,6 @@
 #define QEMU_MIPS_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #ifdef TARGET_MIPS64
 #define TYPE_MIPS_CPU "mips64-cpu"
@@ -34,23 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
 
-/**
- * MIPSCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A MIPS CPU model.
- */
-struct MIPSCPUClass {
-    CPUClass parent_class;
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-    const struct mips_def_t *cpu_def;
-
-    /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
-    bool no_data_aborts;
-};
-
-
 #endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 12cc1bfafd..52f13f0363 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1217,6 +1217,23 @@ struct ArchCPU {
     Clock *count_div; /* Divider for CP0_Count clock */
 };
 
+/**
+ * MIPSCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A MIPS CPU model.
+ */
+struct MIPSCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+    const struct mips_def_t *cpu_def;
+
+    /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
+    bool no_data_aborts;
+};
 
 void mips_cpu_list(void);
 
diff --git a/target/nios2/cpu-qom.h b/target/nios2/cpu-qom.h
index 931bc69b10..2fd9121540 100644
--- a/target/nios2/cpu-qom.h
+++ b/target/nios2/cpu-qom.h
@@ -10,7 +10,6 @@
 #define QEMU_NIOS2_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_NIOS2_CPU "nios2-cpu"
 
diff --git a/target/openrisc/cpu-qom.h b/target/openrisc/cpu-qom.h
index 1ba9fb0a4c..14bac33312 100644
--- a/target/openrisc/cpu-qom.h
+++ b/target/openrisc/cpu-qom.h
@@ -10,7 +10,6 @@
 #define QEMU_OPENRISC_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_OPENRISC_CPU "or1k-cpu"
 
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 76efb614a6..35ca5c4600 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -20,7 +20,6 @@
 #define RISCV_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_RISCV_CPU "riscv-cpu"
 #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
@@ -44,21 +43,8 @@
 #define TYPE_RISCV_CPU_VEYRON_V1        RISCV_CPU_TYPE_NAME("veyron-v1")
 #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
 
-typedef struct CPUArchState CPURISCVState;
+typedef struct CPUArchState CPURISCVState; // XXX
 
 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
 
-/**
- * RISCVCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A RISCV CPU model.
- */
-struct RISCVCPUClass {
-    CPUClass parent_class;
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-};
 #endif /* RISCV_CPU_QOM_H */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d832696418..a7edf95213 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -414,6 +414,20 @@ struct ArchCPU {
     GHashTable *pmu_event_ctr_map;
 };
 
+/**
+ * RISCVCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A RISCV CPU model.
+ */
+struct RISCVCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
+
 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 {
     return (env->misa_ext & ext) != 0;
diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
index 6213d877f7..ac2e5785ef 100644
--- a/target/rx/cpu-qom.h
+++ b/target/rx/cpu-qom.h
@@ -20,7 +20,6 @@
 #define RX_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_RX_CPU "rx-cpu"
 
@@ -31,18 +30,4 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
 #define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
 #define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
 
-/*
- * RXCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A RX CPU model.
- */
-struct RXCPUClass {
-    CPUClass parent_class;
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-};
-
 #endif
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index c81613770c..e931e77e85 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -112,6 +112,20 @@ struct ArchCPU {
     CPURXState env;
 };
 
+/*
+ * RXCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A RX CPU model.
+ */
+struct RXCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
+
 #define CPU_RESOLVING_TYPE TYPE_RX_CPU
 
 const char *rx_crname(uint8_t cr);
diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
index fcd70daddf..4037e31f79 100644
--- a/target/s390x/cpu-qom.h
+++ b/target/s390x/cpu-qom.h
@@ -21,7 +21,6 @@
 #define QEMU_S390_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_S390_CPU "s390x-cpu"
 
@@ -30,40 +29,6 @@ OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU)
 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
 
-typedef struct S390CPUModel S390CPUModel;
-typedef struct S390CPUDef S390CPUDef;
-
-typedef struct CPUArchState CPUS390XState;
-
-typedef enum cpu_reset_type {
-    S390_CPU_RESET_NORMAL,
-    S390_CPU_RESET_INITIAL,
-    S390_CPU_RESET_CLEAR,
-} cpu_reset_type;
-
-/**
- * S390CPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
- * @load_normal: Performs a load normal.
- * @cpu_reset: Performs a CPU reset.
- * @initial_cpu_reset: Performs an initial CPU reset.
- *
- * An S/390 CPU model.
- */
-struct S390CPUClass {
-    CPUClass parent_class;
-
-    const S390CPUDef *cpu_def;
-    bool kvm_required;
-    bool is_static;
-    bool is_migration_safe;
-    const char *desc;
-
-    DeviceRealize parent_realize;
-    DeviceReset parent_reset;
-    void (*load_normal)(CPUState *cpu);
-    void (*reset)(CPUState *cpu, cpu_reset_type type);
-};
+typedef struct CPUArchState CPUS390XState; // XXX
 
 #endif
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 988e2954a4..7e2cccec65 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -175,6 +175,36 @@ struct ArchCPU {
     uint32_t irqstate_saved_size;
 };
 
+typedef enum cpu_reset_type {
+    S390_CPU_RESET_NORMAL,
+    S390_CPU_RESET_INITIAL,
+    S390_CPU_RESET_CLEAR,
+} cpu_reset_type;
+
+/**
+ * S390CPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_reset: The parent class' reset handler.
+ * @load_normal: Performs a load normal.
+ * @cpu_reset: Performs a CPU reset.
+ * @initial_cpu_reset: Performs an initial CPU reset.
+ *
+ * An S/390 CPU model.
+ */
+struct S390CPUClass {
+    CPUClass parent_class;
+
+    const S390CPUDef *cpu_def;
+    bool kvm_required;
+    bool is_static;
+    bool is_migration_safe;
+    const char *desc;
+
+    DeviceRealize parent_realize;
+    DeviceReset parent_reset;
+    void (*load_normal)(CPUState *cpu);
+    void (*reset)(CPUState *cpu, cpu_reset_type type);
+};
 
 #ifndef CONFIG_USER_ONLY
 extern const VMStateDescription vmstate_s390_cpu;
diff --git a/target/s390x/cpu_models.h b/target/s390x/cpu_models.h
index cc7305ec21..d7b8912989 100644
--- a/target/s390x/cpu_models.h
+++ b/target/s390x/cpu_models.h
@@ -18,7 +18,7 @@
 #include "hw/core/cpu.h"
 
 /* static CPU definition */
-struct S390CPUDef {
+typedef struct S390CPUDef {
     const char *name;       /* name exposed to the user */
     const char *desc;       /* description exposed to the user */
     uint8_t gen;            /* hw generation identification */
@@ -38,10 +38,10 @@ struct S390CPUDef {
     S390FeatBitmap full_feat;
     /* used to init full_feat from generated data */
     S390FeatInit full_init;
-};
+} S390CPUDef;
 
 /* CPU model based on a CPU definition */
-struct S390CPUModel {
+typedef struct S390CPUModel {
     const S390CPUDef *def;
     S390FeatBitmap features;
     /* values copied from the "host" model, can change during migration */
@@ -49,7 +49,7 @@ struct S390CPUModel {
     uint32_t cpu_id;        /* CPU id */
     uint8_t cpu_id_format;  /* CPU id format bit */
     uint8_t cpu_ver;        /* CPU version, usually "ff" for kvm */
-};
+} S390CPUModel;
 
 /*
  * CPU ID
diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
index bd0ef49fa1..6cf5fbb074 100644
--- a/target/sh4/cpu-qom.h
+++ b/target/sh4/cpu-qom.h
@@ -21,7 +21,6 @@
 #define QEMU_SUPERH_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_SUPERH_CPU "superh-cpu"
 
@@ -34,26 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
 #define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
 #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
 
-/**
- * SuperHCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- * @pvr: Processor Version Register
- * @prr: Processor Revision Register
- * @cvr: Cache Version Register
- *
- * A SuperH CPU model.
- */
-struct SuperHCPUClass {
-    CPUClass parent_class;
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-
-    uint32_t pvr;
-    uint32_t prr;
-    uint32_t cvr;
-};
-
-
 #endif
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index dbe00e29c2..360eac1fbe 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -209,6 +209,26 @@ struct ArchCPU {
     CPUSH4State env;
 };
 
+/**
+ * SuperHCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ * @pvr: Processor Version Register
+ * @prr: Processor Revision Register
+ * @cvr: Cache Version Register
+ *
+ * A SuperH CPU model.
+ */
+struct SuperHCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+
+    uint32_t pvr;
+    uint32_t prr;
+    uint32_t cvr;
+};
 
 void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
index aca29415b4..a86331bd58 100644
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@@ -21,7 +21,6 @@
 #define QEMU_SPARC_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #ifdef TARGET_SPARC64
 #define TYPE_SPARC_CPU "sparc64-cpu"
@@ -34,21 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
 #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
 #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
 
-typedef struct sparc_def_t sparc_def_t;
-/**
- * SPARCCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A SPARC CPU model.
- */
-struct SPARCCPUClass {
-    CPUClass parent_class;
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-    sparc_def_t *cpu_def;
-};
-
-
 #endif
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 31772c9b73..9cee99d687 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -252,7 +252,7 @@ typedef struct trap_state {
 #endif
 #define TARGET_INSN_START_EXTRA_WORDS 1
 
-struct sparc_def_t {
+typedef struct sparc_def_t {
     const char *name;
     target_ulong iu_version;
     uint32_t fpu_version;
@@ -266,7 +266,7 @@ struct sparc_def_t {
     uint32_t features;
     uint32_t nwindows;
     uint32_t maxtl;
-};
+} sparc_def_t;
 
 #define CPU_FEATURE_FLOAT        (1 << 0)
 #define CPU_FEATURE_FLOAT128     (1 << 1)
@@ -562,6 +562,20 @@ struct ArchCPU {
     CPUSPARCState env;
 };
 
+/**
+ * SPARCCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ *
+ * A SPARC CPU model.
+ */
+struct SPARCCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+    sparc_def_t *cpu_def;
+};
 
 #ifndef CONFIG_USER_ONLY
 extern const VMStateDescription vmstate_sparc_cpu;
diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h
index 2598651008..e35dc1ad2d 100644
--- a/target/tricore/cpu-qom.h
+++ b/target/tricore/cpu-qom.h
@@ -21,8 +21,6 @@
 #define QEMU_TRICORE_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
-
 
 #define TYPE_TRICORE_CPU "tricore-cpu"
 
@@ -31,12 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)
 #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
 #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
 
-struct TriCoreCPUClass {
-    CPUClass parent_class;
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-};
-
-
 #endif /* QEMU_TRICORE_CPU_QOM_H */
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index c537a33ee8..de3ab53a83 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -68,6 +68,12 @@ struct ArchCPU {
     CPUTriCoreState env;
 };
 
+struct TriCoreCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
 
 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h
index 03873ea50b..d932346b5f 100644
--- a/target/xtensa/cpu-qom.h
+++ b/target/xtensa/cpu-qom.h
@@ -30,7 +30,6 @@
 #define QEMU_XTENSA_CPU_QOM_H
 
 #include "hw/core/cpu.h"
-#include "qom/object.h"
 
 #define TYPE_XTENSA_CPU "xtensa-cpu"
 
@@ -39,24 +38,4 @@ OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU)
 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
 #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
 
-typedef struct XtensaConfig XtensaConfig;
-
-/**
- * XtensaCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- * @config: The CPU core configuration.
- *
- * An Xtensa CPU model.
- */
-struct XtensaCPUClass {
-    CPUClass parent_class;
-
-    DeviceRealize parent_realize;
-    ResettablePhases parent_phases;
-
-    const XtensaConfig *config;
-};
-
-
 #endif
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index d6d2fb1f4e..dd81729306 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -426,7 +426,7 @@ extern const XtensaOpcodeTranslators xtensa_core_opcodes;
 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes;
 extern const XtensaOpcodeTranslators xtensa_fpu_opcodes;
 
-struct XtensaConfig {
+typedef struct XtensaConfig {
     const char *name;
     uint64_t options;
     XtensaGdbRegmap gdb_regmap;
@@ -489,7 +489,7 @@ struct XtensaConfig {
     const xtensa_mpu_entry *mpu_bg;
 
     bool use_first_nan;
-};
+} XtensaConfig;
 
 typedef struct XtensaConfigList {
     const XtensaConfig *config;
@@ -562,6 +562,22 @@ struct ArchCPU {
     Clock *clock;
 };
 
+/**
+ * XtensaCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
+ * @config: The CPU core configuration.
+ *
+ * An Xtensa CPU model.
+ */
+struct XtensaCPUClass {
+    CPUClass parent_class;
+
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+
+    const XtensaConfig *config;
+};
 
 #ifndef CONFIG_USER_ONLY
 bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-- 
2.41.0

[PATCH v2 13/16] target/i386: Declare CPU QOM types using DEFINE_TYPES() macro

[Philippe Mathieu-Daudé]

When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.

In few commits we are going to add more types, so replace
the type_register_static() to ease further reviews.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/i386/cpu.c | 50 ++++++++++++++++++++++-------------------------
 1 file changed, 23 insertions(+), 27 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3aab05ddad..81b05d421c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4990,13 +4990,6 @@ static void max_x86_cpu_initfn(Object *obj)
                             &error_abort);
 }
 
-static const TypeInfo max_x86_cpu_type_info = {
-    .name = X86_CPU_TYPE_NAME("max"),
-    .parent = TYPE_X86_CPU,
-    .instance_init = max_x86_cpu_initfn,
-    .class_init = max_x86_cpu_class_init,
-};
-
 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
 {
     assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
@@ -8018,19 +8011,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
     }
 }
 
-static const TypeInfo x86_cpu_type_info = {
-    .name = TYPE_X86_CPU,
-    .parent = TYPE_CPU,
-    .instance_size = sizeof(X86CPU),
-    .instance_align = __alignof(X86CPU),
-    .instance_init = x86_cpu_initfn,
-    .instance_post_init = x86_cpu_post_initfn,
-
-    .abstract = true,
-    .class_size = sizeof(X86CPUClass),
-    .class_init = x86_cpu_common_class_init,
-};
-
 /* "base" CPU model, used by query-cpu-model-expansion */
 static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
 {
@@ -8042,22 +8022,38 @@ static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
     xcc->ordering = 8;
 }
 
-static const TypeInfo x86_base_cpu_type_info = {
-        .name = X86_CPU_TYPE_NAME("base"),
-        .parent = TYPE_X86_CPU,
-        .class_init = x86_cpu_base_class_init,
+static const TypeInfo x86_cpu_types[] = {
+    {
+        .name           = TYPE_X86_CPU,
+        .parent         = TYPE_CPU,
+        .abstract       = true,
+        .instance_size  = sizeof(X86CPU),
+        .instance_align = __alignof(X86CPU),
+        .instance_init  = x86_cpu_initfn,
+        .instance_post_init = x86_cpu_post_initfn,
+        .class_size     = sizeof(X86CPUClass),
+        .class_init     = x86_cpu_common_class_init,
+    }, {
+        .name           = X86_CPU_TYPE_NAME("base"),
+        .parent         = TYPE_X86_CPU,
+        .class_init     = x86_cpu_base_class_init,
+    }, {
+        .name           = X86_CPU_TYPE_NAME("max"),
+        .parent         = TYPE_X86_CPU,
+        .instance_init  = max_x86_cpu_initfn,
+        .class_init     = max_x86_cpu_class_init,
+    }
 };
 
+DEFINE_TYPES(x86_cpu_types)
+
 static void x86_cpu_register_types(void)
 {
     int i;
 
-    type_register_static(&x86_cpu_type_info);
     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
         x86_register_cpudef_types(&builtin_x86_defs[i]);
     }
-    type_register_static(&max_x86_cpu_type_info);
-    type_register_static(&x86_base_cpu_type_info);
 }
 
 type_init(x86_cpu_register_types)
-- 
2.41.0

[PATCH v2 14/16] target/mips: Declare CPU QOM types using DEFINE_TYPES() macro

[Philippe Mathieu-Daudé]

When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.

In few commits we are going to add more types, so replace
the type_register_static() to ease further reviews.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/mips/cpu.c | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index a0023edd43..83ee54f766 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -595,17 +595,21 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
 #endif /* CONFIG_TCG */
 }
 
-static const TypeInfo mips_cpu_type_info = {
-    .name = TYPE_MIPS_CPU,
-    .parent = TYPE_CPU,
-    .instance_size = sizeof(MIPSCPU),
-    .instance_align = __alignof(MIPSCPU),
-    .instance_init = mips_cpu_initfn,
-    .abstract = true,
-    .class_size = sizeof(MIPSCPUClass),
-    .class_init = mips_cpu_class_init,
+static const TypeInfo mips_cpu_types[] = {
+    {
+        .name           = TYPE_MIPS_CPU,
+        .parent         = TYPE_CPU,
+        .instance_size  = sizeof(MIPSCPU),
+        .instance_align = __alignof(MIPSCPU),
+        .instance_init  = mips_cpu_initfn,
+        .abstract       = true,
+        .class_size     = sizeof(MIPSCPUClass),
+        .class_init     = mips_cpu_class_init,
+    }
 };
 
+DEFINE_TYPES(mips_cpu_types)
+
 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
 {
     MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
@@ -630,7 +634,6 @@ static void mips_cpu_register_types(void)
 {
     int i;
 
-    type_register_static(&mips_cpu_type_info);
     for (i = 0; i < mips_defs_number; i++) {
         mips_register_cpudef_type(&mips_defs[i]);
     }
-- 
2.41.0

[PATCH v2 15/16] target/ppc: Declare CPU QOM types using DEFINE_TYPES() macro

[Philippe Mathieu-Daudé]

When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.

In few commits we are going to add more types, so replace
the type_register_static() to ease further reviews.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/ppc/cpu_init.c | 52 +++++++++++++++++++------------------------
 1 file changed, 23 insertions(+), 29 deletions(-)

diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 40fe14a6c2..055436c141 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7408,39 +7408,34 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
 #endif /* CONFIG_TCG */
 }
 
-static const TypeInfo ppc_cpu_type_info = {
-    .name = TYPE_POWERPC_CPU,
-    .parent = TYPE_CPU,
-    .instance_size = sizeof(PowerPCCPU),
-    .instance_align = __alignof__(PowerPCCPU),
-    .instance_init = ppc_cpu_instance_init,
-    .instance_finalize = ppc_cpu_instance_finalize,
-    .abstract = true,
-    .class_size = sizeof(PowerPCCPUClass),
-    .class_init = ppc_cpu_class_init,
+static const TypeInfo ppc_cpu_types[] = {
+    {
+        .name           = TYPE_POWERPC_CPU,
+        .parent         = TYPE_CPU,
+        .abstract       = true,
+        .instance_size  = sizeof(PowerPCCPU),
+        .instance_align = __alignof__(PowerPCCPU),
+        .instance_init  = ppc_cpu_instance_init,
+        .instance_finalize = ppc_cpu_instance_finalize,
+        .class_size     = sizeof(PowerPCCPUClass),
+        .class_init     = ppc_cpu_class_init,
 #ifndef CONFIG_USER_ONLY
-    .interfaces = (InterfaceInfo[]) {
-          { TYPE_INTERRUPT_STATS_PROVIDER },
-          { }
+        .interfaces     = (InterfaceInfo[]) {
+              { TYPE_INTERRUPT_STATS_PROVIDER },
+              { }
+        },
+#endif
+    },
+#ifndef CONFIG_USER_ONLY
+    {
+        .name           = TYPE_PPC_VIRTUAL_HYPERVISOR,
+        .parent         = TYPE_INTERFACE,
+        .class_size     = sizeof(PPCVirtualHypervisorClass),
     },
 #endif
 };
 
-#ifndef CONFIG_USER_ONLY
-static const TypeInfo ppc_vhyp_type_info = {
-    .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
-    .parent = TYPE_INTERFACE,
-    .class_size = sizeof(PPCVirtualHypervisorClass),
-};
-#endif
-
-static void ppc_cpu_register_types(void)
-{
-    type_register_static(&ppc_cpu_type_info);
-#ifndef CONFIG_USER_ONLY
-    type_register_static(&ppc_vhyp_type_info);
-#endif
-}
+DEFINE_TYPES(ppc_cpu_types)
 
 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 {
@@ -7635,4 +7630,3 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 #undef RGPL
 #undef RFPL
 }
-type_init(ppc_cpu_register_types)
-- 
2.41.0

[PATCH v2 16/16] target/sparc: Declare CPU QOM types using DEFINE_TYPES() macro

[Philippe Mathieu-Daudé]

When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.

In few commits we are going to add more types, so replace
the type_register_static() to ease further reviews.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/cpu.c | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 8ba96ae225..1e66413e94 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -924,17 +924,21 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
     cc->tcg_ops = &sparc_tcg_ops;
 }
 
-static const TypeInfo sparc_cpu_type_info = {
-    .name = TYPE_SPARC_CPU,
-    .parent = TYPE_CPU,
-    .instance_size = sizeof(SPARCCPU),
-    .instance_align = __alignof(SPARCCPU),
-    .instance_init = sparc_cpu_initfn,
-    .abstract = true,
-    .class_size = sizeof(SPARCCPUClass),
-    .class_init = sparc_cpu_class_init,
+static const TypeInfo sparc_cpu_types[] = {
+    {
+        .name           = TYPE_SPARC_CPU,
+        .parent         = TYPE_CPU,
+        .instance_size  = sizeof(SPARCCPU),
+        .instance_align = __alignof(SPARCCPU),
+        .instance_init  = sparc_cpu_initfn,
+        .abstract       = true,
+        .class_size     = sizeof(SPARCCPUClass),
+        .class_init     = sparc_cpu_class_init,
+    }
 };
 
+DEFINE_TYPES(sparc_cpu_types)
+
 static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data)
 {
     SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
@@ -959,7 +963,6 @@ static void sparc_cpu_register_types(void)
 {
     int i;
 
-    type_register_static(&sparc_cpu_type_info);
     for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
         sparc_register_cpudef_type(&sparc_defs[i]);
     }
-- 
2.41.0

Re: [PATCH v2 01/16] target: Unify QOM style

[Richard Henderson]

On 10/13/23 07:01, Philippe Mathieu-Daudé wrote:
> Enforce the style described by commit 067109a11c ("docs/devel:
> mention the spacing requirement for QOM"):
> 
>    The first declaration of a storage or class structure should
>    always be the parent and leave a visual space between that
>    declaration and the new code. It is also useful to separate
>    backing for properties (options driven by the user) and internal
>    state to make navigation easier.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 03/16] target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h'

[Richard Henderson]

On 10/13/23 07:01, Philippe Mathieu-Daudé wrote:
> These definitions and declarations are only used by
> target/arm/, no need to expose them to generic hw/.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/arm/cpu-qom.h | 28 ----------------------------
>   target/arm/cpu.h     | 28 ++++++++++++++++++++++++++++
>   2 files changed, 28 insertions(+), 28 deletions(-)
> 
> diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
> index dfb9d5b827..35c3b0924e 100644
> --- a/target/arm/cpu-qom.h
> +++ b/target/arm/cpu-qom.h
> @@ -35,9 +35,6 @@ typedef struct ARMCPUInfo {
>       void (*class_init)(ObjectClass *oc, void *data);
>   } ARMCPUInfo;
>   
> -void arm_cpu_register(const ARMCPUInfo *info);
> -void aarch64_cpu_register(const ARMCPUInfo *info);
> -
>   /**
>    * ARMCPUClass:
>    * @parent_realize: The parent class' realize handler.
> @@ -63,29 +60,4 @@ struct AArch64CPUClass {
>       ARMCPUClass parent_class;
>   };
>   
> -void register_cp_regs_for_features(ARMCPU *cpu);
> -void init_cpreg_list(ARMCPU *cpu);
> -
> -/* Callback functions for the generic timer's timers. */
> -void arm_gt_ptimer_cb(void *opaque);
> -void arm_gt_vtimer_cb(void *opaque);
> -void arm_gt_htimer_cb(void *opaque);
> -void arm_gt_stimer_cb(void *opaque);
> -void arm_gt_hvtimer_cb(void *opaque);
> -
> -#define ARM_AFF0_SHIFT 0
> -#define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
> -#define ARM_AFF1_SHIFT 8
> -#define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
> -#define ARM_AFF2_SHIFT 16
> -#define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
> -#define ARM_AFF3_SHIFT 32
> -#define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
> -#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
> -
> -#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
> -#define ARM64_AFFINITY_MASK \
> -    (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
> -#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
> -
>   #endif
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index fb1b08371c..06f92dacb9 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1116,11 +1116,39 @@ struct ArchCPU {
>       uint64_t gt_cntfrq_hz;
>   };
>   
> +/* Callback functions for the generic timer's timers. */
> +void arm_gt_ptimer_cb(void *opaque);
> +void arm_gt_vtimer_cb(void *opaque);
> +void arm_gt_htimer_cb(void *opaque);
> +void arm_gt_stimer_cb(void *opaque);
> +void arm_gt_hvtimer_cb(void *opaque);
> +
>   unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
>   void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
>   
>   void arm_cpu_post_init(Object *obj);
>   
> +void arm_cpu_register(const ARMCPUInfo *info);
> +void aarch64_cpu_register(const ARMCPUInfo *info);
> +
> +void register_cp_regs_for_features(ARMCPU *cpu);
> +void init_cpreg_list(ARMCPU *cpu);

These can go to internals.h.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

> +
> +#define ARM_AFF0_SHIFT 0
> +#define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
> +#define ARM_AFF1_SHIFT 8
> +#define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
> +#define ARM_AFF2_SHIFT 16
> +#define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
> +#define ARM_AFF3_SHIFT 32
> +#define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
> +#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
> +
> +#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
> +#define ARM64_AFFINITY_MASK \
> +    (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
> +#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
> +
>   uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
>   
>   #ifndef CONFIG_USER_ONLY

Re: [PATCH v2 07/16] target/hexagon: Declare QOM definitions in 'cpu-qom.h'

[Richard Henderson]

On 10/13/23 07:01, Philippe Mathieu-Daudé wrote:
> "target/foo/cpu.h" contains the target specific declarations.
> 
> A heterogeneous setup need to access target agnostic declarations
> (at least the QOM ones, to instantiate the objects).
> 
> Our convention is to add such target agnostic QOM declarations in
> the "target/foo/cpu-qom.h" header.
> 
> Extract QOM definitions from "cpu.h" to "cpu-qom.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/hexagon/cpu-qom.h | 28 ++++++++++++++++++++++++++++
>   target/hexagon/cpu.h     | 15 +--------------
>   2 files changed, 29 insertions(+), 14 deletions(-)
>   create mode 100644 target/hexagon/cpu-qom.h

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH v2 08/16] target/loongarch: Declare QOM definitions in 'cpu-qom.h'

[Richard Henderson]

On 10/13/23 07:01, Philippe Mathieu-Daudé wrote:
> "target/foo/cpu.h" contains the target specific declarations.
> 
> A heterogeneous setup need to access target agnostic declarations
> (at least the QOM ones, to instantiate the objects).
> 
> Our convention is to add such target agnostic QOM declarations in
> the "target/foo/cpu-qom.h" header.
> 
> Extract QOM definitions from "cpu.h" to "cpu-qom.h".
> 
> Reviewed-by: Song Gao <gaosong@loongson.cn>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/loongarch/cpu-qom.h | 24 ++++++++++++++++++++++++
>   target/loongarch/cpu.h     | 10 +---------
>   2 files changed, 25 insertions(+), 9 deletions(-)
>   create mode 100644 target/loongarch/cpu-qom.h

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH v2 09/16] target/nios2: Declare QOM definitions in 'cpu-qom.h'

[Richard Henderson]

On 10/13/23 07:01, Philippe Mathieu-Daudé wrote:
> "target/foo/cpu.h" contains the target specific declarations.
> 
> A heterogeneous setup need to access target agnostic declarations
> (at least the QOM ones, to instantiate the objects).
> 
> Our convention is to add such target agnostic QOM declarations in
> the "target/foo/cpu-qom.h" header.
> 
> Extract QOM definitions from "cpu.h" to "cpu-qom.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/nios2/cpu-qom.h | 19 +++++++++++++++++++
>   target/nios2/cpu.h     |  7 +------
>   2 files changed, 20 insertions(+), 6 deletions(-)
>   create mode 100644 target/nios2/cpu-qom.h

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH v2 10/16] target/openrisc: Declare QOM definitions in 'cpu-qom.h'

[Richard Henderson]

On 10/13/23 07:01, Philippe Mathieu-Daudé wrote:
> "target/foo/cpu.h" contains the target specific declarations.
> 
> A heterogeneous setup need to access target agnostic declarations
> (at least the QOM ones, to instantiate the objects).
> 
> Our convention is to add such target agnostic QOM declarations in
> the "target/foo/cpu-qom.h" header.
> 
> Extract QOM definitions from "cpu.h" to "cpu-qom.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/openrisc/cpu-qom.h | 22 ++++++++++++++++++++++
>   target/openrisc/cpu.h     | 10 +---------
>   2 files changed, 23 insertions(+), 9 deletions(-)
>   create mode 100644 target/openrisc/cpu-qom.h

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH v2 11/16] target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h'

[Richard Henderson]

On 10/13/23 07:01, Philippe Mathieu-Daudé wrote:
> TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64
> definitions which are target specific. Such target specific
> definition taints "cpu-qom.h".
> 
> Since "cpu-qom.h" must be target agnostic, remove its target
> specific definition uses by moving TYPE_RISCV_CPU_BASE to
> "target/riscv/cpu.h".
> 
> "target/riscv/cpu-qom.h" is now fully target agnostic.
> 
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/riscv/cpu-qom.h | 8 +-------
>   target/riscv/cpu.h     | 6 ++++++
>   2 files changed, 7 insertions(+), 7 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 12/16] target: Move ArchCPUClass definition to 'cpu.h'

[Richard Henderson]

On 10/13/23 07:01, Philippe Mathieu-Daudé wrote:
> The OBJECT_DECLARE_CPU_TYPE() macro forward-declares each
> ArchCPUClass type. These forward declarations are sufficient
> for code in hw/ to use the QOM definitions. No need to expose
> these structure definitions. Keep each local to their target/
> by moving them to the corresponding "cpu.h" header.
> 
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/alpha/cpu-qom.h      | 16 ---------------
>   target/alpha/cpu.h          | 13 +++++++++++++
>   target/arm/cpu-qom.h        | 27 -------------------------
>   target/arm/cpu.h            | 25 ++++++++++++++++++++++++
>   target/avr/cpu-qom.h        | 16 ---------------
>   target/avr/cpu.h            | 14 +++++++++++++
>   target/cris/cpu-qom.h       | 19 ------------------
>   target/cris/cpu.h           | 16 +++++++++++++++
>   target/hexagon/cpu-qom.h    |  1 -
>   target/hppa/cpu-qom.h       | 16 ---------------
>   target/hppa/cpu.h           | 14 +++++++++++++
>   target/i386/cpu-qom.h       | 39 -------------------------------------
>   target/i386/cpu.h           | 35 +++++++++++++++++++++++++++++++++
>   target/loongarch/cpu-qom.h  |  1 -
>   target/m68k/cpu-qom.h       | 16 ---------------
>   target/m68k/cpu.h           | 13 +++++++++++++
>   target/microblaze/cpu-qom.h | 16 ---------------
>   target/microblaze/cpu.h     | 13 +++++++++++++
>   target/mips/cpu-qom.h       | 20 -------------------
>   target/mips/cpu.h           | 17 ++++++++++++++++
>   target/nios2/cpu-qom.h      |  1 -
>   target/openrisc/cpu-qom.h   |  1 -
>   target/riscv/cpu-qom.h      | 16 +--------------
>   target/riscv/cpu.h          | 14 +++++++++++++
>   target/rx/cpu-qom.h         | 15 --------------
>   target/rx/cpu.h             | 14 +++++++++++++
>   target/s390x/cpu-qom.h      | 37 +----------------------------------
>   target/s390x/cpu.h          | 30 ++++++++++++++++++++++++++++
>   target/s390x/cpu_models.h   |  8 ++++----
>   target/sh4/cpu-qom.h        | 23 ----------------------
>   target/sh4/cpu.h            | 20 +++++++++++++++++++
>   target/sparc/cpu-qom.h      | 18 -----------------
>   target/sparc/cpu.h          | 18 +++++++++++++++--
>   target/tricore/cpu-qom.h    | 10 ----------
>   target/tricore/cpu.h        |  6 ++++++
>   target/xtensa/cpu-qom.h     | 21 --------------------
>   target/xtensa/cpu.h         | 20 +++++++++++++++++--
>   37 files changed, 284 insertions(+), 335 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH v2 03/16] target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h'

[Philippe Mathieu-Daudé]

On 13/10/23 16:27, Richard Henderson wrote:
> On 10/13/23 07:01, Philippe Mathieu-Daudé wrote:
>> These definitions and declarations are only used by
>> target/arm/, no need to expose them to generic hw/.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   target/arm/cpu-qom.h | 28 ----------------------------
>>   target/arm/cpu.h     | 28 ++++++++++++++++++++++++++++
>>   2 files changed, 28 insertions(+), 28 deletions(-)


>> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
>> index fb1b08371c..06f92dacb9 100644
>> --- a/target/arm/cpu.h
>> +++ b/target/arm/cpu.h
>> @@ -1116,11 +1116,39 @@ struct ArchCPU {
>>       uint64_t gt_cntfrq_hz;
>>   };
>> +/* Callback functions for the generic timer's timers. */
>> +void arm_gt_ptimer_cb(void *opaque);
>> +void arm_gt_vtimer_cb(void *opaque);
>> +void arm_gt_htimer_cb(void *opaque);
>> +void arm_gt_stimer_cb(void *opaque);
>> +void arm_gt_hvtimer_cb(void *opaque);
>> +
>>   unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
>>   void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
>>   void arm_cpu_post_init(Object *obj);
>> +void arm_cpu_register(const ARMCPUInfo *info);
>> +void aarch64_cpu_register(const ARMCPUInfo *info);
>> +
>> +void register_cp_regs_for_features(ARMCPU *cpu);
>> +void init_cpreg_list(ARMCPU *cpu);
> 
> These can go to internals.h.

OK, I'm squashing:

-- >8 --
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ad2f32efd5..2bd8aaff3d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1153,12 +1153,6 @@ void gt_rme_post_el_change(ARMCPU *cpu, void 
*opaque);

  void arm_cpu_post_init(Object *obj);

-void arm_cpu_register(const ARMCPUInfo *info);
-void aarch64_cpu_register(const ARMCPUInfo *info);
-
-void register_cp_regs_for_features(ARMCPU *cpu);
-void init_cpreg_list(ARMCPU *cpu);
-
  #define ARM_AFF0_SHIFT 0
  #define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
  #define ARM_AFF1_SHIFT 8
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 1dd9182a54..cfd64145ea 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -182,6 +182,12 @@ static inline int r14_bank_number(int mode)
      return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode);
  }

+void arm_cpu_register(const ARMCPUInfo *info);
+void aarch64_cpu_register(const ARMCPUInfo *info);
+
+void register_cp_regs_for_features(ARMCPU *cpu);
+void init_cpreg_list(ARMCPU *cpu);
+
  void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
  void arm_translate_init(void);

---

> 
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Thanks!

Re: [PATCH v2 00/16] target: Make 'cpu-qom.h' really target agnostic

[Zhao Liu]

Hi Philippe,

On Fri, Oct 13, 2023 at 04:00:59PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 13 Oct 2023 16:00:59 +0200
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH v2 00/16] target: Make 'cpu-qom.h' really target agnostic
> X-Mailer: git-send-email 2.41.0
> 
> Since v1:
> - Added R-b tags
> - Addressed Richard comments
> - Postponed OBJECT_DECLARE_CPU_TYPE() changes
> 
> A heterogeneous machine must be able to instantiate CPUs
> from different architectures.

Does this mean the different ISA cores in heterogeneous machine?
And is this case for TCG?

> In order to do that, the
> common hw/ code has to access to the QOM CPU definitions
> from various architecture.

About this kind of heterogeneous machine with multiple CPUs, is there
any initial configuration command line example?

I'm not sure how to configure this case...The main unsure thing is
whether the configuration is based on the granularity of the CPU
(by "-cpu") or the granularity of the core device (by "-device
xxx-core").

-Zhao

> 
> Those QOM definitions are published in "target/foo/cpu-qom.h".
> All 'cpu-qom.h' must be target agnostic, so hw/ can include
> multiple of them in order to create a heterogeneous machine.
> 
> This series strengthen all (except PPC...) target 'cpu-qom.h',
> making them target agnostic.
> 
> For various targets it is just a matter of moving definitions
> where they belong (either 'cpu.h' or 'cpu-qom.h').
> 
> For few (mips/riscv/sparc/x86) we have to remove the target
> specific definitions (which 'taint' the header as target specific).
> 
> For mips/sparc/x86 this implies splitting the base target
> definition by making it explicit to the build type (32 or 64-bit).
> 
> PPC is missing because CPU types are currently registered
> indistinctly, and whether a CPU is 32/64 bit can not be detected
> at build time (it is done in each cpu_class_init() handler,
> *after* the type is registered).
> 
> Based-on: <20231010074952.79165-1-philmd@linaro.org>
>   Introduce qtest_get_base_arch() / qtest_get_arch_bits()
> 
> Philippe Mathieu-Daudé (16):
>   target: Unify QOM style
>   target: Mention 'cpu-qom.h' is target agnostic
>   target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h'
>   target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'
>   target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'
>   target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'
>   target/hexagon: Declare QOM definitions in 'cpu-qom.h'
>   target/loongarch: Declare QOM definitions in 'cpu-qom.h'
>   target/nios2: Declare QOM definitions in 'cpu-qom.h'
>   target/openrisc: Declare QOM definitions in 'cpu-qom.h'
>   target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h'
>   target: Move ArchCPUClass definition to 'cpu.h'
>   target/i386: Declare CPU QOM types using DEFINE_TYPES() macro
>   target/mips: Declare CPU QOM types using DEFINE_TYPES() macro
>   target/ppc: Declare CPU QOM types using DEFINE_TYPES() macro
>   target/sparc: Declare CPU QOM types using DEFINE_TYPES() macro
> 
>  target/alpha/cpu-qom.h      | 21 ++-----------
>  target/alpha/cpu.h          | 17 ++++++++---
>  target/arm/cpu-qom.h        | 61 +------------------------------------
>  target/arm/cpu.h            | 55 +++++++++++++++++++++++++++++++--
>  target/avr/cpu-qom.h        | 20 ++----------
>  target/avr/cpu.h            | 18 ++++++++---
>  target/cris/cpu-qom.h       | 24 ++-------------
>  target/cris/cpu.h           | 20 +++++++++---
>  target/hexagon/cpu-qom.h    | 27 ++++++++++++++++
>  target/hexagon/cpu.h        | 20 ++----------
>  target/hppa/cpu-qom.h       | 20 +-----------
>  target/hppa/cpu.h           | 16 ++++++++--
>  target/i386/cpu-qom.h       | 42 ++-----------------------
>  target/i386/cpu.h           | 39 +++++++++++++++++++++---
>  target/loongarch/cpu-qom.h  | 23 ++++++++++++++
>  target/loongarch/cpu.h      | 14 +--------
>  target/m68k/cpu-qom.h       | 21 ++-----------
>  target/m68k/cpu.h           | 17 ++++++++---
>  target/microblaze/cpu-qom.h | 20 +-----------
>  target/microblaze/cpu.h     | 15 +++++++--
>  target/mips/cpu-qom.h       | 23 ++------------
>  target/mips/cpu.h           | 21 ++++++++++---
>  target/nios2/cpu-qom.h      | 18 +++++++++++
>  target/nios2/cpu.h          | 11 +------
>  target/openrisc/cpu-qom.h   | 21 +++++++++++++
>  target/openrisc/cpu.h       | 14 +--------
>  target/ppc/cpu-qom.h        |  3 +-
>  target/ppc/cpu.h            |  4 +--
>  target/riscv/cpu-qom.h      | 26 ++--------------
>  target/riscv/cpu.h          | 24 +++++++++++++--
>  target/rx/cpu-qom.h         | 20 ++----------
>  target/rx/cpu.h             | 18 ++++++++---
>  target/s390x/cpu-qom.h      | 41 +++----------------------
>  target/s390x/cpu.h          | 34 ++++++++++++++++++---
>  target/s390x/cpu_models.h   |  8 ++---
>  target/sh4/cpu-qom.h        | 28 ++---------------
>  target/sh4/cpu.h            | 24 ++++++++++++---
>  target/sparc/cpu-qom.h      | 23 ++------------
>  target/sparc/cpu.h          | 22 +++++++++----
>  target/tricore/cpu-qom.h    | 15 +++------
>  target/tricore/cpu.h        | 10 +++---
>  target/xtensa/cpu-qom.h     | 26 ++--------------
>  target/xtensa/cpu.h         | 24 +++++++++++----
>  target/i386/cpu.c           | 50 ++++++++++++++----------------
>  target/mips/cpu.c           | 23 ++++++++------
>  target/ppc/cpu_init.c       | 52 ++++++++++++++-----------------
>  target/sparc/cpu.c          | 23 ++++++++------
>  47 files changed, 528 insertions(+), 588 deletions(-)
>  create mode 100644 target/hexagon/cpu-qom.h
>  create mode 100644 target/loongarch/cpu-qom.h
>  create mode 100644 target/nios2/cpu-qom.h
>  create mode 100644 target/openrisc/cpu-qom.h
> 
> -- 
> 2.41.0
> 

Re: [PATCH v2 13/16] target/i386: Declare CPU QOM types using DEFINE_TYPES() macro

[Zhao Liu]

On Fri, Oct 13, 2023 at 04:01:12PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 13 Oct 2023 16:01:12 +0200
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH v2 13/16] target/i386: Declare CPU QOM types using
>  DEFINE_TYPES() macro
> X-Mailer: git-send-email 2.41.0
> 
> When multiple QOM types are registered in the same file,
> it is simpler to use the the DEFINE_TYPES() macro. In
> particular because type array declared with such macro
> are easier to review.
> 
> In few commits we are going to add more types, so replace
> the type_register_static() to ease further reviews.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/i386/cpu.c | 50 ++++++++++++++++++++++-------------------------
>  1 file changed, 23 insertions(+), 27 deletions(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 3aab05ddad..81b05d421c 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -4990,13 +4990,6 @@ static void max_x86_cpu_initfn(Object *obj)
>                              &error_abort);
>  }
>  
> -static const TypeInfo max_x86_cpu_type_info = {
> -    .name = X86_CPU_TYPE_NAME("max"),
> -    .parent = TYPE_X86_CPU,
> -    .instance_init = max_x86_cpu_initfn,
> -    .class_init = max_x86_cpu_class_init,
> -};
> -
>  static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
>  {
>      assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
> @@ -8018,19 +8011,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
>      }
>  }
>  
> -static const TypeInfo x86_cpu_type_info = {
> -    .name = TYPE_X86_CPU,
> -    .parent = TYPE_CPU,
> -    .instance_size = sizeof(X86CPU),
> -    .instance_align = __alignof(X86CPU),
> -    .instance_init = x86_cpu_initfn,
> -    .instance_post_init = x86_cpu_post_initfn,
> -
> -    .abstract = true,
> -    .class_size = sizeof(X86CPUClass),
> -    .class_init = x86_cpu_common_class_init,
> -};
> -
>  /* "base" CPU model, used by query-cpu-model-expansion */
>  static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
>  {
> @@ -8042,22 +8022,38 @@ static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
>      xcc->ordering = 8;
>  }
>  
> -static const TypeInfo x86_base_cpu_type_info = {
> -        .name = X86_CPU_TYPE_NAME("base"),
> -        .parent = TYPE_X86_CPU,
> -        .class_init = x86_cpu_base_class_init,
> +static const TypeInfo x86_cpu_types[] = {
> +    {
> +        .name           = TYPE_X86_CPU,
> +        .parent         = TYPE_CPU,
> +        .abstract       = true,
> +        .instance_size  = sizeof(X86CPU),
> +        .instance_align = __alignof(X86CPU),
> +        .instance_init  = x86_cpu_initfn,
> +        .instance_post_init = x86_cpu_post_initfn,
> +        .class_size     = sizeof(X86CPUClass),
> +        .class_init     = x86_cpu_common_class_init,
> +    }, {
> +        .name           = X86_CPU_TYPE_NAME("base"),
> +        .parent         = TYPE_X86_CPU,
> +        .class_init     = x86_cpu_base_class_init,
> +    }, {
> +        .name           = X86_CPU_TYPE_NAME("max"),
> +        .parent         = TYPE_X86_CPU,
> +        .instance_init  = max_x86_cpu_initfn,
> +        .class_init     = max_x86_cpu_class_init,
> +    }
>  };
>  
> +DEFINE_TYPES(x86_cpu_types)
> +
>  static void x86_cpu_register_types(void)
>  {
>      int i;
>  
> -    type_register_static(&x86_cpu_type_info);
>      for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
>          x86_register_cpudef_types(&builtin_x86_defs[i]);
>      }
> -    type_register_static(&max_x86_cpu_type_info);
> -    type_register_static(&x86_base_cpu_type_info);
>  }
>  
>  type_init(x86_cpu_register_types)
> -- 
> 2.41.0
> 
> 
> 

Re: [PATCH v2 01/16] target: Unify QOM style

[Zhao Liu]

On Fri, Oct 13, 2023 at 04:01:00PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 13 Oct 2023 16:01:00 +0200
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH v2 01/16] target: Unify QOM style
> X-Mailer: git-send-email 2.41.0
> 
> Enforce the style described by commit 067109a11c ("docs/devel:
> mention the spacing requirement for QOM"):
> 
>   The first declaration of a storage or class structure should
>   always be the parent and leave a visual space between that
>   declaration and the new code. It is also useful to separate
>   backing for properties (options driven by the user) and internal
>   state to make navigation easier.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/alpha/cpu-qom.h      | 2 --
>  target/alpha/cpu.h          | 2 --
>  target/arm/cpu-qom.h        | 4 ----
>  target/arm/cpu.h            | 2 --
>  target/avr/cpu-qom.h        | 3 +--
>  target/avr/cpu.h            | 2 --
>  target/cris/cpu-qom.h       | 2 --
>  target/cris/cpu.h           | 2 --
>  target/hexagon/cpu.h        | 5 +----
>  target/hppa/cpu-qom.h       | 2 --
>  target/hppa/cpu.h           | 2 --
>  target/i386/cpu-qom.h       | 2 --
>  target/i386/cpu.h           | 2 --
>  target/loongarch/cpu.h      | 4 ----
>  target/m68k/cpu-qom.h       | 2 --
>  target/m68k/cpu.h           | 2 --
>  target/microblaze/cpu-qom.h | 2 --
>  target/microblaze/cpu.h     | 2 --
>  target/mips/cpu-qom.h       | 2 --
>  target/mips/cpu.h           | 2 --
>  target/nios2/cpu.h          | 4 ----
>  target/openrisc/cpu.h       | 4 ----
>  target/ppc/cpu.h            | 2 --
>  target/riscv/cpu-qom.h      | 3 +--
>  target/riscv/cpu.h          | 2 --
>  target/rx/cpu-qom.h         | 2 --
>  target/rx/cpu.h             | 2 --
>  target/s390x/cpu-qom.h      | 3 +--
>  target/s390x/cpu.h          | 2 --
>  target/sh4/cpu-qom.h        | 2 --
>  target/sh4/cpu.h            | 2 --
>  target/sparc/cpu-qom.h      | 2 --
>  target/sparc/cpu.h          | 2 --
>  target/tricore/cpu-qom.h    | 2 --
>  target/tricore/cpu.h        | 2 --
>  target/xtensa/cpu-qom.h     | 2 --
>  target/xtensa/cpu.h         | 2 --
>  37 files changed, 4 insertions(+), 84 deletions(-)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

> 
> diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
> index 1f200724b6..c5fbd8f11a 100644
> --- a/target/alpha/cpu-qom.h
> +++ b/target/alpha/cpu-qom.h
> @@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
>   * An Alpha CPU model.
>   */
>  struct AlphaCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      DeviceRealize parent_realize;
>      DeviceReset parent_reset;
> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
> index e2a467ec17..c8d97ac27a 100644
> --- a/target/alpha/cpu.h
> +++ b/target/alpha/cpu.h
> @@ -259,9 +259,7 @@ typedef struct CPUArchState {
>   * An Alpha CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUAlphaState env;
>  
> diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
> index d06c08a734..153865d1bb 100644
> --- a/target/arm/cpu-qom.h
> +++ b/target/arm/cpu-qom.h
> @@ -46,9 +46,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info);
>   * An ARM CPU model.
>   */
>  struct ARMCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      const ARMCPUInfo *info;
>      DeviceRealize parent_realize;
> @@ -62,9 +60,7 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
>                         TYPE_AARCH64_CPU)
>  
>  struct AArch64CPUClass {
> -    /*< private >*/
>      ARMCPUClass parent_class;
> -    /*< public >*/
>  };
>  
>  void register_cp_regs_for_features(ARMCPU *cpu);
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index a9edfb8353..fb1b08371c 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -852,9 +852,7 @@ typedef struct {
>   * An ARM CPU core.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUARMState env;
>  
> diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
> index 01ea5f160b..d89be01e0f 100644
> --- a/target/avr/cpu-qom.h
> +++ b/target/avr/cpu-qom.h
> @@ -36,9 +36,8 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
>   *  A AVR CPU model.
>   */
>  struct AVRCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
> +
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
>  };
> diff --git a/target/avr/cpu.h b/target/avr/cpu.h
> index 4ce22d8e4f..f8b065ed79 100644
> --- a/target/avr/cpu.h
> +++ b/target/avr/cpu.h
> @@ -144,9 +144,7 @@ typedef struct CPUArchState {
>   *  A AVR CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUAVRState env;
>  };
> diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h
> index 431a1d536a..c2fee242f4 100644
> --- a/target/cris/cpu-qom.h
> +++ b/target/cris/cpu-qom.h
> @@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
>   * A CRIS CPU model.
>   */
>  struct CRISCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
> diff --git a/target/cris/cpu.h b/target/cris/cpu.h
> index 676b8e93ca..6aa445348f 100644
> --- a/target/cris/cpu.h
> +++ b/target/cris/cpu.h
> @@ -174,9 +174,7 @@ typedef struct CPUArchState {
>   * A CRIS CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUCRISState env;
>  };
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
> index 10cd1efd57..035ac4fb6d 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -130,17 +130,14 @@ typedef struct CPUArchState {
>  OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
>  
>  typedef struct HexagonCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
> +
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
>  } HexagonCPUClass;
>  
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUHexagonState env;
>  
> diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h
> index b96e0318c7..67f12422c4 100644
> --- a/target/hppa/cpu-qom.h
> +++ b/target/hppa/cpu-qom.h
> @@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU)
>   * An HPPA CPU model.
>   */
>  struct HPPACPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      DeviceRealize parent_realize;
>      DeviceReset parent_reset;
> diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
> index 798d0c26d7..518ea94f4f 100644
> --- a/target/hppa/cpu.h
> +++ b/target/hppa/cpu.h
> @@ -233,9 +233,7 @@ typedef struct CPUArchState {
>   * An HPPA CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUHPPAState env;
>      QEMUTimer *alarm_timer;
> diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
> index 2350f4ae60..58145717ef 100644
> --- a/target/i386/cpu-qom.h
> +++ b/target/i386/cpu-qom.h
> @@ -47,9 +47,7 @@ typedef struct X86CPUModel X86CPUModel;
>   * An x86 CPU model or family.
>   */
>  struct X86CPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      /* CPU definition, automatically loaded by instance_init if not NULL.
>       * Should be eventually replaced by subclass-specific property defaults.
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index e1875466b9..a600468698 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1897,9 +1897,7 @@ struct kvm_msrs;
>   * An x86 CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUX86State env;
>      VMChangeStateEntry *vmsentry;
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index 40e70a8119..2b8b828114 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -371,9 +371,7 @@ typedef struct CPUArchState {
>   * A LoongArch CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPULoongArchState env;
>      QEMUTimer timer;
> @@ -398,9 +396,7 @@ OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
>   * A LoongArch CPU model.
>   */
>  struct LoongArchCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
> diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
> index 0ec7750a92..13d94c9fe3 100644
> --- a/target/m68k/cpu-qom.h
> +++ b/target/m68k/cpu-qom.h
> @@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
>   * A Motorola 68k CPU model.
>   */
>  struct M68kCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
> index 20afb0c94d..9ea18028ad 100644
> --- a/target/m68k/cpu.h
> +++ b/target/m68k/cpu.h
> @@ -164,9 +164,7 @@ typedef struct CPUArchState {
>   * A Motorola 68k CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUM68KState env;
>  };
> diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
> index cda9220fa9..2a734e644d 100644
> --- a/target/microblaze/cpu-qom.h
> +++ b/target/microblaze/cpu-qom.h
> @@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
>   * A MicroBlaze CPU model.
>   */
>  struct MicroBlazeCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index e43c49d4af..e8000237d8 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -343,9 +343,7 @@ typedef struct {
>   * A MicroBlaze CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUMBState env;
>  
> diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
> index 0dffab453b..c70b4a34be 100644
> --- a/target/mips/cpu-qom.h
> +++ b/target/mips/cpu-qom.h
> @@ -39,9 +39,7 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
>   * A MIPS CPU model.
>   */
>  struct MIPSCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 5fddceff3a..617c373797 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1209,9 +1209,7 @@ typedef struct CPUArchState {
>   * A MIPS CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUMIPSState env;
>  
> diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
> index 70b6377a4f..ede1ba2140 100644
> --- a/target/nios2/cpu.h
> +++ b/target/nios2/cpu.h
> @@ -42,9 +42,7 @@ OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
>   * A Nios2 CPU model.
>   */
>  struct Nios2CPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
> @@ -214,9 +212,7 @@ typedef struct {
>   * A Nios2 CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUNios2State env;
>  
> diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
> index 334997e9a1..29cda7279c 100644
> --- a/target/openrisc/cpu.h
> +++ b/target/openrisc/cpu.h
> @@ -39,9 +39,7 @@ OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
>   * A OpenRISC CPU model.
>   */
>  struct OpenRISCCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
> @@ -301,9 +299,7 @@ typedef struct CPUArchState {
>   * A OpenRISC CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUOpenRISCState env;
>  };
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 4b8b5d3d3e..cf4629036d 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1407,9 +1407,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
>   * A PowerPC CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUPPCState env;
>  
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index f3fbe37a2c..b9164a8e5b 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -63,9 +63,8 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
>   * A RISCV CPU model.
>   */
>  struct RISCVCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
> +
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
>  };
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index f8ffa5ee38..f0dc257a75 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -389,9 +389,7 @@ struct CPUArchState {
>   * A RISCV CPU.
>   */
>  struct ArchCPU {
> -    /* < private > */
>      CPUState parent_obj;
> -    /* < public > */
>  
>      CPURISCVState env;
>  
> diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
> index 1c8466a187..f4cd5664e5 100644
> --- a/target/rx/cpu-qom.h
> +++ b/target/rx/cpu-qom.h
> @@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
>   * A RX CPU model.
>   */
>  struct RXCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
> diff --git a/target/rx/cpu.h b/target/rx/cpu.h
> index f66754eb8a..8379f4a150 100644
> --- a/target/rx/cpu.h
> +++ b/target/rx/cpu.h
> @@ -107,9 +107,7 @@ typedef struct CPUArchState {
>   * A RX CPU
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPURXState env;
>  };
> diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
> index 00cae2b131..1088965fd5 100644
> --- a/target/s390x/cpu-qom.h
> +++ b/target/s390x/cpu-qom.h
> @@ -49,9 +49,8 @@ typedef enum cpu_reset_type {
>   * An S/390 CPU model.
>   */
>  struct S390CPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
> +
>      const S390CPUDef *cpu_def;
>      bool kvm_required;
>      bool is_static;
> diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
> index 7bea7075e1..e56982dd69 100644
> --- a/target/s390x/cpu.h
> +++ b/target/s390x/cpu.h
> @@ -166,9 +166,7 @@ static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
>   * An S/390 CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUS390XState env;
>      S390CPUModel *model;
> diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
> index 89785a90f0..08fbebc996 100644
> --- a/target/sh4/cpu-qom.h
> +++ b/target/sh4/cpu-qom.h
> @@ -42,9 +42,7 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
>   * A SuperH CPU model.
>   */
>  struct SuperHCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
> index f75a235973..dc0561b73b 100644
> --- a/target/sh4/cpu.h
> +++ b/target/sh4/cpu.h
> @@ -204,9 +204,7 @@ typedef struct CPUArchState {
>   * A SuperH CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUSH4State env;
>  };
> diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
> index 78bf00b9a2..b4a0db84ce 100644
> --- a/target/sparc/cpu-qom.h
> +++ b/target/sparc/cpu-qom.h
> @@ -40,9 +40,7 @@ typedef struct sparc_def_t sparc_def_t;
>   * A SPARC CPU model.
>   */
>  struct SPARCCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
> diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
> index b3a98f1d74..691287f134 100644
> --- a/target/sparc/cpu.h
> +++ b/target/sparc/cpu.h
> @@ -557,9 +557,7 @@ struct CPUArchState {
>   * A SPARC CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUSPARCState env;
>  };
> diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h
> index 612731daa0..b3b6c75a3a 100644
> --- a/target/tricore/cpu-qom.h
> +++ b/target/tricore/cpu-qom.h
> @@ -27,9 +27,7 @@
>  OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)
>  
>  struct TriCoreCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
> diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
> index a357b573f2..b4a6ab141d 100644
> --- a/target/tricore/cpu.h
> +++ b/target/tricore/cpu.h
> @@ -63,9 +63,7 @@ typedef struct CPUArchState {
>   * A TriCore CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUTriCoreState env;
>  };
> diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h
> index 419c7d8e4a..424bcbd8dd 100644
> --- a/target/xtensa/cpu-qom.h
> +++ b/target/xtensa/cpu-qom.h
> @@ -47,9 +47,7 @@ typedef struct XtensaConfig XtensaConfig;
>   * An Xtensa CPU model.
>   */
>  struct XtensaCPUClass {
> -    /*< private >*/
>      CPUClass parent_class;
> -    /*< public >*/
>  
>      DeviceRealize parent_realize;
>      ResettablePhases parent_phases;
> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> index c6bbef1e5d..85aab1bdf8 100644
> --- a/target/xtensa/cpu.h
> +++ b/target/xtensa/cpu.h
> @@ -556,9 +556,7 @@ struct CPUArchState {
>   * An Xtensa CPU.
>   */
>  struct ArchCPU {
> -    /*< private >*/
>      CPUState parent_obj;
> -    /*< public >*/
>  
>      CPUXtensaState env;
>      Clock *clock;
> -- 
> 2.41.0
> 
> 
> 

Re: [PATCH v2 02/16] target: Mention 'cpu-qom.h' is target agnostic

[Zhao Liu]

Hi Philippe,

On Fri, Oct 13, 2023 at 04:01:01PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 13 Oct 2023 16:01:01 +0200
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH v2 02/16] target: Mention 'cpu-qom.h' is target agnostic
> X-Mailer: git-send-email 2.41.0
> 
> "target/foo/cpu-qom.h" is supposed to be target agnostic
> (include-able by any target). Add such mention in the
> header.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu-qom.h        | 2 +-
>  target/hppa/cpu-qom.h       | 2 +-
>  target/microblaze/cpu-qom.h | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)

Why not mention this description for other qom-cpu.h in this series,
e.g., target/i386/cpu-qom.h.

Otherwise,

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

> 
> diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
> index 153865d1bb..dfb9d5b827 100644
> --- a/target/arm/cpu-qom.h
> +++ b/target/arm/cpu-qom.h
> @@ -1,5 +1,5 @@
>  /*
> - * QEMU ARM CPU
> + * QEMU ARM CPU QOM header (target agnostic)
>   *
>   * Copyright (c) 2012 SUSE LINUX Products GmbH
>   *
> diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h
> index 67f12422c4..4b1d48f7ca 100644
> --- a/target/hppa/cpu-qom.h
> +++ b/target/hppa/cpu-qom.h
> @@ -1,5 +1,5 @@
>  /*
> - * QEMU HPPA CPU
> + * QEMU HPPA CPU QOM header (target agnostic)
>   *
>   * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
>   *
> diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
> index 2a734e644d..78f549b57d 100644
> --- a/target/microblaze/cpu-qom.h
> +++ b/target/microblaze/cpu-qom.h
> @@ -1,5 +1,5 @@
>  /*
> - * QEMU MicroBlaze CPU
> + * QEMU MicroBlaze CPU QOM header (target agnostic)
>   *
>   * Copyright (c) 2012 SUSE LINUX Products GmbH
>   *
> -- 
> 2.41.0
> 
> 
> 

Re: [PATCH v2 12/16] target: Move ArchCPUClass definition to 'cpu.h'

[Zhao Liu]

Hi Philippe,

On Fri, Oct 13, 2023 at 04:01:11PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 13 Oct 2023 16:01:11 +0200
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH v2 12/16] target: Move ArchCPUClass definition to 'cpu.h'
> X-Mailer: git-send-email 2.41.0
> 
> The OBJECT_DECLARE_CPU_TYPE() macro forward-declares each
> ArchCPUClass type. These forward declarations are sufficient
> for code in hw/ to use the QOM definitions. No need to expose
> these structure definitions. Keep each local to their target/
> by moving them to the corresponding "cpu.h" header.
> 
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/alpha/cpu-qom.h      | 16 ---------------
>  target/alpha/cpu.h          | 13 +++++++++++++
>  target/arm/cpu-qom.h        | 27 -------------------------
>  target/arm/cpu.h            | 25 ++++++++++++++++++++++++
>  target/avr/cpu-qom.h        | 16 ---------------
>  target/avr/cpu.h            | 14 +++++++++++++
>  target/cris/cpu-qom.h       | 19 ------------------
>  target/cris/cpu.h           | 16 +++++++++++++++
>  target/hexagon/cpu-qom.h    |  1 -
>  target/hppa/cpu-qom.h       | 16 ---------------
>  target/hppa/cpu.h           | 14 +++++++++++++
>  target/i386/cpu-qom.h       | 39 -------------------------------------
>  target/i386/cpu.h           | 35 +++++++++++++++++++++++++++++++++
>  target/loongarch/cpu-qom.h  |  1 -
>  target/m68k/cpu-qom.h       | 16 ---------------
>  target/m68k/cpu.h           | 13 +++++++++++++
>  target/microblaze/cpu-qom.h | 16 ---------------
>  target/microblaze/cpu.h     | 13 +++++++++++++
>  target/mips/cpu-qom.h       | 20 -------------------
>  target/mips/cpu.h           | 17 ++++++++++++++++
>  target/nios2/cpu-qom.h      |  1 -
>  target/openrisc/cpu-qom.h   |  1 -
>  target/riscv/cpu-qom.h      | 16 +--------------
>  target/riscv/cpu.h          | 14 +++++++++++++
>  target/rx/cpu-qom.h         | 15 --------------
>  target/rx/cpu.h             | 14 +++++++++++++
>  target/s390x/cpu-qom.h      | 37 +----------------------------------
>  target/s390x/cpu.h          | 30 ++++++++++++++++++++++++++++
>  target/s390x/cpu_models.h   |  8 ++++----
>  target/sh4/cpu-qom.h        | 23 ----------------------
>  target/sh4/cpu.h            | 20 +++++++++++++++++++
>  target/sparc/cpu-qom.h      | 18 -----------------
>  target/sparc/cpu.h          | 18 +++++++++++++++--
>  target/tricore/cpu-qom.h    | 10 ----------
>  target/tricore/cpu.h        |  6 ++++++
>  target/xtensa/cpu-qom.h     | 21 --------------------
>  target/xtensa/cpu.h         | 20 +++++++++++++++++--
>  37 files changed, 284 insertions(+), 335 deletions(-)
> 
> diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
> index c4a4523993..1b32b18d34 100644
> --- a/target/alpha/cpu-qom.h
> +++ b/target/alpha/cpu-qom.h
> @@ -21,7 +21,6 @@
>  #define QEMU_ALPHA_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_ALPHA_CPU "alpha-cpu"
>  
> @@ -30,19 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
>  #define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU
>  #define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX
>  
> -/**
> - * AlphaCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_reset: The parent class' reset handler.
> - *
> - * An Alpha CPU model.
> - */
> -struct AlphaCPUClass {
> -    CPUClass parent_class;
> -
> -    DeviceRealize parent_realize;
> -    DeviceReset parent_reset;
> -};
> -
> -
>  #endif
> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
> index 3bff56c565..d672e911dd 100644
> --- a/target/alpha/cpu.h
> +++ b/target/alpha/cpu.h
> @@ -267,6 +267,19 @@ struct ArchCPU {
>      QEMUTimer *alarm_timer;
>  };
>  
> +/**
> + * AlphaCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_reset: The parent class' reset handler.
> + *
> + * An Alpha CPU model.
> + */
> +struct AlphaCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    DeviceReset parent_reset;
> +};
>  
>  #ifndef CONFIG_USER_ONLY
>  extern const VMStateDescription vmstate_alpha_cpu;
> diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
> index 35c3b0924e..02b914c876 100644
> --- a/target/arm/cpu-qom.h
> +++ b/target/arm/cpu-qom.h
> @@ -21,7 +21,6 @@
>  #define QEMU_ARM_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_ARM_CPU "arm-cpu"
>  
> @@ -29,35 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
>  
>  #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
>  
> -typedef struct ARMCPUInfo {
> -    const char *name;
> -    void (*initfn)(Object *obj);
> -    void (*class_init)(ObjectClass *oc, void *data);
> -} ARMCPUInfo;
> -
> -/**
> - * ARMCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - *
> - * An ARM CPU model.
> - */
> -struct ARMCPUClass {
> -    CPUClass parent_class;
> -
> -    const ARMCPUInfo *info;
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -};
> -
> -
>  #define TYPE_AARCH64_CPU "aarch64-cpu"
>  typedef struct AArch64CPUClass AArch64CPUClass;
>  DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
>                         TYPE_AARCH64_CPU)
>  
> -struct AArch64CPUClass {
> -    ARMCPUClass parent_class;
> -};
> -
>  #endif
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 06f92dacb9..ad2f32efd5 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1116,6 +1116,31 @@ struct ArchCPU {
>      uint64_t gt_cntfrq_hz;
>  };
>  
> +typedef struct ARMCPUInfo {
> +    const char *name;
> +    void (*initfn)(Object *obj);
> +    void (*class_init)(ObjectClass *oc, void *data);
> +} ARMCPUInfo;
> +
> +/**
> + * ARMCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + *
> + * An ARM CPU model.
> + */
> +struct ARMCPUClass {
> +    CPUClass parent_class;
> +
> +    const ARMCPUInfo *info;
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +};
> +
> +struct AArch64CPUClass {
> +    ARMCPUClass parent_class;
> +};
> +
>  /* Callback functions for the generic timer's timers. */
>  void arm_gt_ptimer_cb(void *opaque);
>  void arm_gt_vtimer_cb(void *opaque);
> diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
> index 75590cdd97..38dbcc0535 100644
> --- a/target/avr/cpu-qom.h
> +++ b/target/avr/cpu-qom.h
> @@ -22,7 +22,6 @@
>  #define TARGET_AVR_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_AVR_CPU "avr-cpu"
>  
> @@ -31,19 +30,4 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
>  #define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU
>  #define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX)
>  
> -/**
> - *  AVRCPUClass:
> - *  @parent_realize: The parent class' realize handler.
> - *  @parent_phases: The parent class' reset phase handlers.
> - *
> - *  A AVR CPU model.
> - */
> -struct AVRCPUClass {
> -    CPUClass parent_class;
> -
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -};
> -
> -
>  #endif /* TARGET_AVR_CPU_QOM_H */
> diff --git a/target/avr/cpu.h b/target/avr/cpu.h
> index 0487399cb2..8a17862737 100644
> --- a/target/avr/cpu.h
> +++ b/target/avr/cpu.h
> @@ -147,6 +147,20 @@ struct ArchCPU {
>      CPUAVRState env;
>  };
>  
> +/**
> + *  AVRCPUClass:
> + *  @parent_realize: The parent class' realize handler.
> + *  @parent_phases: The parent class' reset phase handlers.
> + *
> + *  A AVR CPU model.
> + */
> +struct AVRCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +};
> +
>  extern const struct VMStateDescription vms_avr_cpu;
>  
>  void avr_cpu_do_interrupt(CPUState *cpu);
> diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h
> index d7e5f33e62..741ca97a1b 100644
> --- a/target/cris/cpu-qom.h
> +++ b/target/cris/cpu-qom.h
> @@ -21,7 +21,6 @@
>  #define QEMU_CRIS_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_CRIS_CPU "cris-cpu"
>  
> @@ -30,22 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
>  #define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
>  #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
>  
> -/**
> - * CRISCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - * @vr: Version Register value.
> - *
> - * A CRIS CPU model.
> - */
> -struct CRISCPUClass {
> -    CPUClass parent_class;
> -
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -
> -    uint32_t vr;
> -};
> -
> -
>  #endif
> diff --git a/target/cris/cpu.h b/target/cris/cpu.h
> index b821bb7983..1be7f90319 100644
> --- a/target/cris/cpu.h
> +++ b/target/cris/cpu.h
> @@ -179,6 +179,22 @@ struct ArchCPU {
>      CPUCRISState env;
>  };
>  
> +/**
> + * CRISCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + * @vr: Version Register value.
> + *
> + * A CRIS CPU model.
> + */
> +struct CRISCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +
> +    uint32_t vr;
> +};
>  
>  #ifndef CONFIG_USER_ONLY
>  extern const VMStateDescription vmstate_cris_cpu;
> diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h
> index f02df7ee6f..da92fe7468 100644
> --- a/target/hexagon/cpu-qom.h
> +++ b/target/hexagon/cpu-qom.h
> @@ -10,7 +10,6 @@
>  #define QEMU_HEXAGON_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_HEXAGON_CPU "hexagon-cpu"
>  
> diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h
> index 4b1d48f7ca..7270e93e6b 100644
> --- a/target/hppa/cpu-qom.h
> +++ b/target/hppa/cpu-qom.h
> @@ -21,25 +21,9 @@
>  #define QEMU_HPPA_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_HPPA_CPU "hppa-cpu"
>  
>  OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU)
>  
> -/**
> - * HPPACPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_reset: The parent class' reset handler.
> - *
> - * An HPPA CPU model.
> - */
> -struct HPPACPUClass {
> -    CPUClass parent_class;
> -
> -    DeviceRealize parent_realize;
> -    DeviceReset parent_reset;
> -};
> -
> -
>  #endif
> diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
> index 518ea94f4f..0a0c7366c2 100644
> --- a/target/hppa/cpu.h
> +++ b/target/hppa/cpu.h
> @@ -239,6 +239,20 @@ struct ArchCPU {
>      QEMUTimer *alarm_timer;
>  };
>  
> +/**
> + * HPPACPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_reset: The parent class' reset handler.
> + *
> + * An HPPA CPU model.
> + */
> +struct HPPACPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    DeviceReset parent_reset;
> +};
> +
>  #include "exec/cpu-all.h"
>  
>  static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
> diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
> index dffc74c1ce..d4e216d000 100644
> --- a/target/i386/cpu-qom.h
> +++ b/target/i386/cpu-qom.h
> @@ -21,8 +21,6 @@
>  #define QEMU_I386_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qemu/notify.h"
> -#include "qom/object.h"
>  
>  #ifdef TARGET_X86_64
>  #define TYPE_X86_CPU "x86_64-cpu"
> @@ -35,41 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
>  #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
>  #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
>  
> -typedef struct X86CPUModel X86CPUModel;
> -
> -/**
> - * X86CPUClass:
> - * @cpu_def: CPU model definition
> - * @host_cpuid_required: Whether CPU model requires cpuid from host.
> - * @ordering: Ordering on the "-cpu help" CPU model list.
> - * @migration_safe: See CpuDefinitionInfo::migration_safe
> - * @static_model: See CpuDefinitionInfo::static
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - *
> - * An x86 CPU model or family.
> - */
> -struct X86CPUClass {
> -    CPUClass parent_class;
> -
> -    /* CPU definition, automatically loaded by instance_init if not NULL.
> -     * Should be eventually replaced by subclass-specific property defaults.
> -     */
> -    X86CPUModel *model;
> -
> -    bool host_cpuid_required;
> -    int ordering;
> -    bool migration_safe;
> -    bool static_model;
> -
> -    /* Optional description of CPU model.
> -     * If unavailable, cpu_def->model_id is used */
> -    const char *model_description;
> -
> -    DeviceRealize parent_realize;
> -    DeviceUnrealize parent_unrealize;
> -    ResettablePhases parent_phases;
> -};
> -
> -
>  #endif
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 2dea4df086..e21d293daa 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -2037,6 +2037,41 @@ struct ArchCPU {
>      bool xen_vapic;
>  };
>  
> +typedef struct X86CPUModel X86CPUModel;

Could we "typedef" this structure at its definition?

Then this explicit "typedef" can also be omitted, just like you did
elsewhere.

> +
> +/**
> + * X86CPUClass:
> + * @cpu_def: CPU model definition
> + * @host_cpuid_required: Whether CPU model requires cpuid from host.
> + * @ordering: Ordering on the "-cpu help" CPU model list.
> + * @migration_safe: See CpuDefinitionInfo::migration_safe
> + * @static_model: See CpuDefinitionInfo::static
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + *
> + * An x86 CPU model or family.
> + */
> +struct X86CPUClass {
> +    CPUClass parent_class;
> +
> +    /* CPU definition, automatically loaded by instance_init if not NULL.
> +     * Should be eventually replaced by subclass-specific property defaults.
> +     */
> +    X86CPUModel *model;
> +
> +    bool host_cpuid_required;
> +    int ordering;
> +    bool migration_safe;
> +    bool static_model;
> +
> +    /* Optional description of CPU model.
> +     * If unavailable, cpu_def->model_id is used */
> +    const char *model_description;
> +
> +    DeviceRealize parent_realize;
> +    DeviceUnrealize parent_unrealize;
> +    ResettablePhases parent_phases;
> +};
>  
>  #ifndef CONFIG_USER_ONLY
>  extern const VMStateDescription vmstate_x86_cpu;
> diff --git a/target/loongarch/cpu-qom.h b/target/loongarch/cpu-qom.h
> index 82c86d146d..fa3fcf7186 100644
> --- a/target/loongarch/cpu-qom.h
> +++ b/target/loongarch/cpu-qom.h
> @@ -9,7 +9,6 @@
>  #define LOONGARCH_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_LOONGARCH_CPU "loongarch-cpu"
>  #define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
> diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
> index df0cc8b7a3..273e8eae41 100644
> --- a/target/m68k/cpu-qom.h
> +++ b/target/m68k/cpu-qom.h
> @@ -21,7 +21,6 @@
>  #define QEMU_M68K_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_M68K_CPU "m68k-cpu"
>  
> @@ -30,19 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
>  #define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
>  #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
>  
> -/*
> - * M68kCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - *
> - * A Motorola 68k CPU model.
> - */
> -struct M68kCPUClass {
> -    CPUClass parent_class;
> -
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -};
> -
> -
>  #endif
> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
> index 7f34686a6f..6cfc696d2b 100644
> --- a/target/m68k/cpu.h
> +++ b/target/m68k/cpu.h
> @@ -169,6 +169,19 @@ struct ArchCPU {
>      CPUM68KState env;
>  };
>  
> +/*
> + * M68kCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + *
> + * A Motorola 68k CPU model.
> + */
> +struct M68kCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +};
>  
>  #ifndef CONFIG_USER_ONLY
>  void m68k_cpu_do_interrupt(CPUState *cpu);
> diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
> index 78f549b57d..92e539fb2f 100644
> --- a/target/microblaze/cpu-qom.h
> +++ b/target/microblaze/cpu-qom.h
> @@ -21,25 +21,9 @@
>  #define QEMU_MICROBLAZE_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_MICROBLAZE_CPU "microblaze-cpu"
>  
>  OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
>  
> -/**
> - * MicroBlazeCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - *
> - * A MicroBlaze CPU model.
> - */
> -struct MicroBlazeCPUClass {
> -    CPUClass parent_class;
> -
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -};
> -
> -
>  #endif
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index e8000237d8..b5374365f5 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -355,6 +355,19 @@ struct ArchCPU {
>      MicroBlazeCPUConfig cfg;
>  };
>  
> +/**
> + * MicroBlazeCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + *
> + * A MicroBlaze CPU model.
> + */
> +struct MicroBlazeCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +};
>  
>  #ifndef CONFIG_USER_ONLY
>  void mb_cpu_do_interrupt(CPUState *cs);
> diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
> index 5822dfb1d2..0eea2a2598 100644
> --- a/target/mips/cpu-qom.h
> +++ b/target/mips/cpu-qom.h
> @@ -21,7 +21,6 @@
>  #define QEMU_MIPS_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #ifdef TARGET_MIPS64
>  #define TYPE_MIPS_CPU "mips64-cpu"
> @@ -34,23 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
>  #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
>  #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
>  
> -/**
> - * MIPSCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - *
> - * A MIPS CPU model.
> - */
> -struct MIPSCPUClass {
> -    CPUClass parent_class;
> -
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -    const struct mips_def_t *cpu_def;
> -
> -    /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
> -    bool no_data_aborts;
> -};
> -
> -
>  #endif
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 12cc1bfafd..52f13f0363 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1217,6 +1217,23 @@ struct ArchCPU {
>      Clock *count_div; /* Divider for CP0_Count clock */
>  };
>  
> +/**
> + * MIPSCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + *
> + * A MIPS CPU model.
> + */
> +struct MIPSCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +    const struct mips_def_t *cpu_def;
> +
> +    /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
> +    bool no_data_aborts;
> +};
>  
>  void mips_cpu_list(void);
>  
> diff --git a/target/nios2/cpu-qom.h b/target/nios2/cpu-qom.h
> index 931bc69b10..2fd9121540 100644
> --- a/target/nios2/cpu-qom.h
> +++ b/target/nios2/cpu-qom.h
> @@ -10,7 +10,6 @@
>  #define QEMU_NIOS2_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_NIOS2_CPU "nios2-cpu"
>  
> diff --git a/target/openrisc/cpu-qom.h b/target/openrisc/cpu-qom.h
> index 1ba9fb0a4c..14bac33312 100644
> --- a/target/openrisc/cpu-qom.h
> +++ b/target/openrisc/cpu-qom.h
> @@ -10,7 +10,6 @@
>  #define QEMU_OPENRISC_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_OPENRISC_CPU "or1k-cpu"
>  
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 76efb614a6..35ca5c4600 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -20,7 +20,6 @@
>  #define RISCV_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_RISCV_CPU "riscv-cpu"
>  #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
> @@ -44,21 +43,8 @@
>  #define TYPE_RISCV_CPU_VEYRON_V1        RISCV_CPU_TYPE_NAME("veyron-v1")
>  #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
>  
> -typedef struct CPUArchState CPURISCVState;
> +typedef struct CPUArchState CPURISCVState; // XXX

Is "// XXX" redundant?

>  
>  OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
>  
> -/**
> - * RISCVCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - *
> - * A RISCV CPU model.
> - */
> -struct RISCVCPUClass {
> -    CPUClass parent_class;
> -
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -};
>  #endif /* RISCV_CPU_QOM_H */
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d832696418..a7edf95213 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -414,6 +414,20 @@ struct ArchCPU {
>      GHashTable *pmu_event_ctr_map;
>  };
>  
> +/**
> + * RISCVCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + *
> + * A RISCV CPU model.
> + */
> +struct RISCVCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +};
> +
>  static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
>  {
>      return (env->misa_ext & ext) != 0;
> diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
> index 6213d877f7..ac2e5785ef 100644
> --- a/target/rx/cpu-qom.h
> +++ b/target/rx/cpu-qom.h
> @@ -20,7 +20,6 @@
>  #define RX_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_RX_CPU "rx-cpu"
>  
> @@ -31,18 +30,4 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
>  #define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU
>  #define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX
>  
> -/*
> - * RXCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - *
> - * A RX CPU model.
> - */
> -struct RXCPUClass {
> -    CPUClass parent_class;
> -
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -};
> -
>  #endif
> diff --git a/target/rx/cpu.h b/target/rx/cpu.h
> index c81613770c..e931e77e85 100644
> --- a/target/rx/cpu.h
> +++ b/target/rx/cpu.h
> @@ -112,6 +112,20 @@ struct ArchCPU {
>      CPURXState env;
>  };
>  
> +/*
> + * RXCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + *
> + * A RX CPU model.
> + */
> +struct RXCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +};
> +
>  #define CPU_RESOLVING_TYPE TYPE_RX_CPU
>  
>  const char *rx_crname(uint8_t cr);
> diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
> index fcd70daddf..4037e31f79 100644
> --- a/target/s390x/cpu-qom.h
> +++ b/target/s390x/cpu-qom.h
> @@ -21,7 +21,6 @@
>  #define QEMU_S390_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_S390_CPU "s390x-cpu"
>  
> @@ -30,40 +29,6 @@ OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU)
>  #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
>  #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
>  
> -typedef struct S390CPUModel S390CPUModel;
> -typedef struct S390CPUDef S390CPUDef;
> -
> -typedef struct CPUArchState CPUS390XState;
> -
> -typedef enum cpu_reset_type {
> -    S390_CPU_RESET_NORMAL,
> -    S390_CPU_RESET_INITIAL,
> -    S390_CPU_RESET_CLEAR,
> -} cpu_reset_type;
> -
> -/**
> - * S390CPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_reset: The parent class' reset handler.
> - * @load_normal: Performs a load normal.
> - * @cpu_reset: Performs a CPU reset.
> - * @initial_cpu_reset: Performs an initial CPU reset.
> - *
> - * An S/390 CPU model.
> - */
> -struct S390CPUClass {
> -    CPUClass parent_class;
> -
> -    const S390CPUDef *cpu_def;
> -    bool kvm_required;
> -    bool is_static;
> -    bool is_migration_safe;
> -    const char *desc;
> -
> -    DeviceRealize parent_realize;
> -    DeviceReset parent_reset;
> -    void (*load_normal)(CPUState *cpu);
> -    void (*reset)(CPUState *cpu, cpu_reset_type type);
> -};
> +typedef struct CPUArchState CPUS390XState; // XXX

same here.

Just the above nits. Otherwise,

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

-Zhao

>  
>  #endif
> diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
> index 988e2954a4..7e2cccec65 100644
> --- a/target/s390x/cpu.h
> +++ b/target/s390x/cpu.h
> @@ -175,6 +175,36 @@ struct ArchCPU {
>      uint32_t irqstate_saved_size;
>  };
>  
> +typedef enum cpu_reset_type {
> +    S390_CPU_RESET_NORMAL,
> +    S390_CPU_RESET_INITIAL,
> +    S390_CPU_RESET_CLEAR,
> +} cpu_reset_type;
> +
> +/**
> + * S390CPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_reset: The parent class' reset handler.
> + * @load_normal: Performs a load normal.
> + * @cpu_reset: Performs a CPU reset.
> + * @initial_cpu_reset: Performs an initial CPU reset.
> + *
> + * An S/390 CPU model.
> + */
> +struct S390CPUClass {
> +    CPUClass parent_class;
> +
> +    const S390CPUDef *cpu_def;
> +    bool kvm_required;
> +    bool is_static;
> +    bool is_migration_safe;
> +    const char *desc;
> +
> +    DeviceRealize parent_realize;
> +    DeviceReset parent_reset;
> +    void (*load_normal)(CPUState *cpu);
> +    void (*reset)(CPUState *cpu, cpu_reset_type type);
> +};
>  
>  #ifndef CONFIG_USER_ONLY
>  extern const VMStateDescription vmstate_s390_cpu;
> diff --git a/target/s390x/cpu_models.h b/target/s390x/cpu_models.h
> index cc7305ec21..d7b8912989 100644
> --- a/target/s390x/cpu_models.h
> +++ b/target/s390x/cpu_models.h
> @@ -18,7 +18,7 @@
>  #include "hw/core/cpu.h"
>  
>  /* static CPU definition */
> -struct S390CPUDef {
> +typedef struct S390CPUDef {
>      const char *name;       /* name exposed to the user */
>      const char *desc;       /* description exposed to the user */
>      uint8_t gen;            /* hw generation identification */
> @@ -38,10 +38,10 @@ struct S390CPUDef {
>      S390FeatBitmap full_feat;
>      /* used to init full_feat from generated data */
>      S390FeatInit full_init;
> -};
> +} S390CPUDef;
>  
>  /* CPU model based on a CPU definition */
> -struct S390CPUModel {
> +typedef struct S390CPUModel {
>      const S390CPUDef *def;
>      S390FeatBitmap features;
>      /* values copied from the "host" model, can change during migration */
> @@ -49,7 +49,7 @@ struct S390CPUModel {
>      uint32_t cpu_id;        /* CPU id */
>      uint8_t cpu_id_format;  /* CPU id format bit */
>      uint8_t cpu_ver;        /* CPU version, usually "ff" for kvm */
> -};
> +} S390CPUModel;
>  
>  /*
>   * CPU ID
> diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
> index bd0ef49fa1..6cf5fbb074 100644
> --- a/target/sh4/cpu-qom.h
> +++ b/target/sh4/cpu-qom.h
> @@ -21,7 +21,6 @@
>  #define QEMU_SUPERH_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_SUPERH_CPU "superh-cpu"
>  
> @@ -34,26 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
>  #define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
>  #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
>  
> -/**
> - * SuperHCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - * @pvr: Processor Version Register
> - * @prr: Processor Revision Register
> - * @cvr: Cache Version Register
> - *
> - * A SuperH CPU model.
> - */
> -struct SuperHCPUClass {
> -    CPUClass parent_class;
> -
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -
> -    uint32_t pvr;
> -    uint32_t prr;
> -    uint32_t cvr;
> -};
> -
> -
>  #endif
> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
> index dbe00e29c2..360eac1fbe 100644
> --- a/target/sh4/cpu.h
> +++ b/target/sh4/cpu.h
> @@ -209,6 +209,26 @@ struct ArchCPU {
>      CPUSH4State env;
>  };
>  
> +/**
> + * SuperHCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + * @pvr: Processor Version Register
> + * @prr: Processor Revision Register
> + * @cvr: Cache Version Register
> + *
> + * A SuperH CPU model.
> + */
> +struct SuperHCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +
> +    uint32_t pvr;
> +    uint32_t prr;
> +    uint32_t cvr;
> +};
>  
>  void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
>  int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
> diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
> index aca29415b4..a86331bd58 100644
> --- a/target/sparc/cpu-qom.h
> +++ b/target/sparc/cpu-qom.h
> @@ -21,7 +21,6 @@
>  #define QEMU_SPARC_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #ifdef TARGET_SPARC64
>  #define TYPE_SPARC_CPU "sparc64-cpu"
> @@ -34,21 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
>  #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU
>  #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX
>  
> -typedef struct sparc_def_t sparc_def_t;
> -/**
> - * SPARCCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - *
> - * A SPARC CPU model.
> - */
> -struct SPARCCPUClass {
> -    CPUClass parent_class;
> -
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -    sparc_def_t *cpu_def;
> -};
> -
> -
>  #endif
> diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
> index 31772c9b73..9cee99d687 100644
> --- a/target/sparc/cpu.h
> +++ b/target/sparc/cpu.h
> @@ -252,7 +252,7 @@ typedef struct trap_state {
>  #endif
>  #define TARGET_INSN_START_EXTRA_WORDS 1
>  
> -struct sparc_def_t {
> +typedef struct sparc_def_t {
>      const char *name;
>      target_ulong iu_version;
>      uint32_t fpu_version;
> @@ -266,7 +266,7 @@ struct sparc_def_t {
>      uint32_t features;
>      uint32_t nwindows;
>      uint32_t maxtl;
> -};
> +} sparc_def_t;
>  
>  #define CPU_FEATURE_FLOAT        (1 << 0)
>  #define CPU_FEATURE_FLOAT128     (1 << 1)
> @@ -562,6 +562,20 @@ struct ArchCPU {
>      CPUSPARCState env;
>  };
>  
> +/**
> + * SPARCCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + *
> + * A SPARC CPU model.
> + */
> +struct SPARCCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +    sparc_def_t *cpu_def;
> +};
>  
>  #ifndef CONFIG_USER_ONLY
>  extern const VMStateDescription vmstate_sparc_cpu;
> diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h
> index 2598651008..e35dc1ad2d 100644
> --- a/target/tricore/cpu-qom.h
> +++ b/target/tricore/cpu-qom.h
> @@ -21,8 +21,6 @@
>  #define QEMU_TRICORE_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
> -
>  
>  #define TYPE_TRICORE_CPU "tricore-cpu"
>  
> @@ -31,12 +29,4 @@ OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)
>  #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
>  #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
>  
> -struct TriCoreCPUClass {
> -    CPUClass parent_class;
> -
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -};
> -
> -
>  #endif /* QEMU_TRICORE_CPU_QOM_H */
> diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
> index c537a33ee8..de3ab53a83 100644
> --- a/target/tricore/cpu.h
> +++ b/target/tricore/cpu.h
> @@ -68,6 +68,12 @@ struct ArchCPU {
>      CPUTriCoreState env;
>  };
>  
> +struct TriCoreCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +};
>  
>  hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
>  void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
> diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h
> index 03873ea50b..d932346b5f 100644
> --- a/target/xtensa/cpu-qom.h
> +++ b/target/xtensa/cpu-qom.h
> @@ -30,7 +30,6 @@
>  #define QEMU_XTENSA_CPU_QOM_H
>  
>  #include "hw/core/cpu.h"
> -#include "qom/object.h"
>  
>  #define TYPE_XTENSA_CPU "xtensa-cpu"
>  
> @@ -39,24 +38,4 @@ OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU)
>  #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
>  #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
>  
> -typedef struct XtensaConfig XtensaConfig;
> -
> -/**
> - * XtensaCPUClass:
> - * @parent_realize: The parent class' realize handler.
> - * @parent_phases: The parent class' reset phase handlers.
> - * @config: The CPU core configuration.
> - *
> - * An Xtensa CPU model.
> - */
> -struct XtensaCPUClass {
> -    CPUClass parent_class;
> -
> -    DeviceRealize parent_realize;
> -    ResettablePhases parent_phases;
> -
> -    const XtensaConfig *config;
> -};
> -
> -
>  #endif
> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> index d6d2fb1f4e..dd81729306 100644
> --- a/target/xtensa/cpu.h
> +++ b/target/xtensa/cpu.h
> @@ -426,7 +426,7 @@ extern const XtensaOpcodeTranslators xtensa_core_opcodes;
>  extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes;
>  extern const XtensaOpcodeTranslators xtensa_fpu_opcodes;
>  
> -struct XtensaConfig {
> +typedef struct XtensaConfig {
>      const char *name;
>      uint64_t options;
>      XtensaGdbRegmap gdb_regmap;
> @@ -489,7 +489,7 @@ struct XtensaConfig {
>      const xtensa_mpu_entry *mpu_bg;
>  
>      bool use_first_nan;
> -};
> +} XtensaConfig;
>  
>  typedef struct XtensaConfigList {
>      const XtensaConfig *config;
> @@ -562,6 +562,22 @@ struct ArchCPU {
>      Clock *clock;
>  };
>  
> +/**
> + * XtensaCPUClass:
> + * @parent_realize: The parent class' realize handler.
> + * @parent_phases: The parent class' reset phase handlers.
> + * @config: The CPU core configuration.
> + *
> + * An Xtensa CPU model.
> + */
> +struct XtensaCPUClass {
> +    CPUClass parent_class;
> +
> +    DeviceRealize parent_realize;
> +    ResettablePhases parent_phases;
> +
> +    const XtensaConfig *config;
> +};
>  
>  #ifndef CONFIG_USER_ONLY
>  bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> -- 
> 2.41.0
> 
> 
> 

Re: [PATCH v2 00/16] target: Make 'cpu-qom.h' really target agnostic

[Philippe Mathieu-Daudé]

Hi Zhao,

On 20/10/23 07:50, Zhao Liu wrote:
> Hi Philippe,
> 
> On Fri, Oct 13, 2023 at 04:00:59PM +0200, Philippe Mathieu-Daudé wrote:
>> Date: Fri, 13 Oct 2023 16:00:59 +0200
>> From: Philippe Mathieu-Daudé <philmd@linaro.org>
>> Subject: [PATCH v2 00/16] target: Make 'cpu-qom.h' really target agnostic
>> X-Mailer: git-send-email 2.41.0
>>
>> Since v1:
>> - Added R-b tags
>> - Addressed Richard comments
>> - Postponed OBJECT_DECLARE_CPU_TYPE() changes
>>
>> A heterogeneous machine must be able to instantiate CPUs
>> from different architectures.
> 
> Does this mean the different ISA cores in heterogeneous machine?

Yes. Currently the ARM target already allows you to do that
(multiple ISA cores within the same architecture), see the
xlnx-zcu102 and fby35 machines.

> And is this case for TCG?

This is *only* for TCG. I expect hardware accel + TCG to be
theoretically possible, but no interest has been shown for
it. Anyhow this requires heterogeneous TCG as a first step.

>> In order to do that, the
>> common hw/ code has to access to the QOM CPU definitions
>> from various architecture.
> 
> About this kind of heterogeneous machine with multiple CPUs, is there
> any initial configuration command line example?

I'm prototyping in plain C but our plan is to start with a
QMP prototype. Command line configuration is not an option,
we decided to ignore it. I'll describe that better in a RFC
document I should post soon.

Regards,

Phil.

> I'm not sure how to configure this case...The main unsure thing is
> whether the configuration is based on the granularity of the CPU
> (by "-cpu") or the granularity of the core device (by "-device
> xxx-core").
> 
> -Zhao

Re: [PATCH v2 00/16] target: Make 'cpu-qom.h' really target agnostic

[Zhao Liu]

Hi Philippe,

On Fri, Oct 20, 2023 at 01:30:50PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 20 Oct 2023 13:30:50 +0200
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: Re: [PATCH v2 00/16] target: Make 'cpu-qom.h' really target
>  agnostic
> 
> Hi Zhao,
> 
> On 20/10/23 07:50, Zhao Liu wrote:
> > Hi Philippe,
> > 
> > On Fri, Oct 13, 2023 at 04:00:59PM +0200, Philippe Mathieu-Daudé wrote:
> > > Date: Fri, 13 Oct 2023 16:00:59 +0200
> > > From: Philippe Mathieu-Daudé <philmd@linaro.org>
> > > Subject: [PATCH v2 00/16] target: Make 'cpu-qom.h' really target agnostic
> > > X-Mailer: git-send-email 2.41.0
> > > 
> > > Since v1:
> > > - Added R-b tags
> > > - Addressed Richard comments
> > > - Postponed OBJECT_DECLARE_CPU_TYPE() changes
> > > 
> > > A heterogeneous machine must be able to instantiate CPUs
> > > from different architectures.
> > 
> > Does this mean the different ISA cores in heterogeneous machine?
> 
> Yes. Currently the ARM target already allows you to do that
> (multiple ISA cores within the same architecture), see the
> xlnx-zcu102 and fby35 machines.

Okay, I'll have a look at it.

> 
> > And is this case for TCG?
> 
> This is *only* for TCG. I expect hardware accel + TCG to be
> theoretically possible, but no interest has been shown for
> it. Anyhow this requires heterogeneous TCG as a first step.

Thanks, got it.

> 
> > > In order to do that, the
> > > common hw/ code has to access to the QOM CPU definitions
> > > from various architecture.
> > 
> > About this kind of heterogeneous machine with multiple CPUs, is there
> > any initial configuration command line example?
> 
> I'm prototyping in plain C but our plan is to start with a
> QMP prototype. Command line configuration is not an option,
> we decided to ignore it. I'll describe that better in a RFC
> document I should post soon.

Looking forward to your RFC!

For accel, I am currently working in this direction (to convert all CPU
topology levels to devices and to create heterogeneous topology via
"-device") as the following:

-device cpu-socket,id=sock0 \
-device cpu-die,id=die0,parent=sock0 \
-device cpu-die,id=die1,parent=sock0 \
-device cpu-cluster,id=cluster0,parent=die0 \
-device cpu-cluster,id=cluster1,parent=die0 \
-device x86-intel-core,id=core0,parent=cluster0,threads=3 \
-device x86-intel-atom,id=core1,parent=cluster1,threads=2 \
-device x86-intel-core,id=core2,parent=cluster0,threads=3

At present, I have a prototype and am sorting out the RFC.

From your description, I understand that we have no conflict.
Also welcome your thoughts and hope that I can go in the same
direction with you. ;-)

Regards,
Zhao

RE: [PATCH v2 07/16] target/hexagon: Declare QOM definitions in 'cpu-qom.h'

[Brian Cain]

> -----Original Message-----
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Sent: Friday, October 13, 2023 9:01 AM
> To: qemu-devel@nongnu.org
> Cc: Eduardo Habkost <eduardo@habkost.net>; Xiaojuan Yang
> <yangxiaojuan@loongson.cn>; Michael S. Tsirkin <mst@redhat.com>; qemu-
> ppc@nongnu.org; Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>; David
> Hildenbrand <david@redhat.com>; qemu-s390x@nongnu.org; Edgar E. Iglesias
> <edgar.iglesias@gmail.com>; Jiaxun Yang <jiaxun.yang@flygoat.com>; Song
> Gao <gaosong@loongson.cn>; Philippe Mathieu-Daudé <philmd@linaro.org>;
> Paolo Bonzini <pbonzini@redhat.com>; Stafford Horne <shorne@gmail.com>;
> Alistair Francis <alistair.francis@wdc.com>; Yanan Wang
> <wangyanan55@huawei.com>; Max Filippov <jcmvbkbc@gmail.com>; Artyom
> Tarasenko <atar4qemu@gmail.com>; Marcel Apfelbaum
> <marcel.apfelbaum@gmail.com>; Cédric Le Goater <clg@kaod.org>; Laurent
> Vivier <lvivier@redhat.com>; Aurelien Jarno <aurelien@aurel32.net>; qemu-
> riscv@nongnu.org; Palmer Dabbelt <palmer@dabbelt.com>; Yoshinori Sato
> <ysato@users.sourceforge.jp>; Bastian Koppelmann <kbastian@mail.uni-
> paderborn.de>; Bin Meng <bin.meng@windriver.com>; Daniel Henrique
> Barboza <danielhb413@gmail.com>; Mark Cave-Ayland <mark.cave-
> ayland@ilande.co.uk>; Weiwei Li <liweiwei@iscas.ac.cn>; Daniel Henrique
> Barboza <dbarboza@ventanamicro.com>; Nicholas Piggin
> <npiggin@gmail.com>; qemu-arm@nongnu.org; Liu Zhiwei
> <zhiwei_liu@linux.alibaba.com>; Marek Vasut <marex@denx.de>; Laurent
> Vivier <laurent@vivier.eu>; Peter Maydell <peter.maydell@linaro.org>; Brian
> Cain <bcain@quicinc.com>; Thomas Huth <thuth@redhat.com>; Chris Wulff
> <crwulff@gmail.com>; Sergio Lopez <slp@redhat.com>; Richard Henderson
> <richard.henderson@linaro.org>; Ilya Leoshkevich <iii@linux.ibm.com>;
> Michael Rolnik <mrolnik@gmail.com>
> Subject: [PATCH v2 07/16] target/hexagon: Declare QOM definitions in 'cpu-
> qom.h'
> 
> WARNING: This email originated from outside of Qualcomm. Please be wary of
> any links or attachments, and do not enable macros.
> 
> "target/foo/cpu.h" contains the target specific declarations.
> 
> A heterogeneous setup need to access target agnostic declarations
> (at least the QOM ones, to instantiate the objects).
> 
> Our convention is to add such target agnostic QOM declarations in
> the "target/foo/cpu-qom.h" header.
> 
> Extract QOM definitions from "cpu.h" to "cpu-qom.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/hexagon/cpu-qom.h | 28 ++++++++++++++++++++++++++++
>  target/hexagon/cpu.h     | 15 +--------------
>  2 files changed, 29 insertions(+), 14 deletions(-)
>  create mode 100644 target/hexagon/cpu-qom.h
> 
> diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h
> new file mode 100644
> index 0000000000..f02df7ee6f
> --- /dev/null
> +++ b/target/hexagon/cpu-qom.h
> @@ -0,0 +1,28 @@
> +/*
> + * QEMU Hexagon CPU QOM header (target agnostic)
> + *
> + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
> Reserved.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef QEMU_HEXAGON_CPU_QOM_H
> +#define QEMU_HEXAGON_CPU_QOM_H
> +
> +#include "hw/core/cpu.h"
> +#include "qom/object.h"
> +
> +#define TYPE_HEXAGON_CPU "hexagon-cpu"
> +
> +#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
> +#define HEXAGON_CPU_TYPE_NAME(name) (name
> HEXAGON_CPU_TYPE_SUFFIX)
> +
> +#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
> +#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
> +#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
> +#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
> +#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
> +
> +OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass,
> HEXAGON_CPU)
> +
> +#endif
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
> index 035ac4fb6d..7d16083c6a 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -20,11 +20,10 @@
> 
>  #include "fpu/softfloat-types.h"
> 
> +#include "cpu-qom.h"
>  #include "exec/cpu-defs.h"
>  #include "hex_regs.h"
>  #include "mmvec/mmvec.h"
> -#include "qom/object.h"
> -#include "hw/core/cpu.h"
>  #include "hw/registerfields.h"
> 
>  #define NUM_PREGS 4
> @@ -36,18 +35,8 @@
>  #define PRED_WRITES_MAX 5                   /* 4 insns + endloop */
>  #define VSTORES_MAX 2
> 
> -#define TYPE_HEXAGON_CPU "hexagon-cpu"
> -
> -#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
> -#define HEXAGON_CPU_TYPE_NAME(name) (name
> HEXAGON_CPU_TYPE_SUFFIX)
>  #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU
> 
> -#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
> -#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
> -#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")
> -#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71")
> -#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73")
> -
>  void hexagon_cpu_list(void);
>  #define cpu_list hexagon_cpu_list
> 
> @@ -127,8 +116,6 @@ typedef struct CPUArchState {
>      VTCMStoreLog vtcm_log;
>  } CPUHexagonState;
> 
> -OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass,
> HEXAGON_CPU)
> -
>  typedef struct HexagonCPUClass {
>      CPUClass parent_class;
> 
> --
> 2.41.0

Reviewed-by: Brian Cain <bcain@quicinc.com>

Re: [PATCH v2 02/16] target: Mention 'cpu-qom.h' is target agnostic

[Philippe Mathieu-Daudé]

On 20/10/23 09:14, Zhao Liu wrote:
> Hi Philippe,
> 
> On Fri, Oct 13, 2023 at 04:01:01PM +0200, Philippe Mathieu-Daudé wrote:
>> Date: Fri, 13 Oct 2023 16:01:01 +0200
>> From: Philippe Mathieu-Daudé <philmd@linaro.org>
>> Subject: [PATCH v2 02/16] target: Mention 'cpu-qom.h' is target agnostic
>> X-Mailer: git-send-email 2.41.0
>>
>> "target/foo/cpu-qom.h" is supposed to be target agnostic
>> (include-able by any target). Add such mention in the
>> header.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>   target/arm/cpu-qom.h        | 2 +-
>>   target/hppa/cpu-qom.h       | 2 +-
>>   target/microblaze/cpu-qom.h | 2 +-
>>   3 files changed, 3 insertions(+), 3 deletions(-)
> 
> Why not mention this description for other qom-cpu.h in this series,
> e.g., target/i386/cpu-qom.h.

OK, will add a comment in each patch.

> Otherwise,
> 
> Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Thanks!

Re: [PATCH v2 12/16] target: Move ArchCPUClass definition to 'cpu.h'

[Philippe Mathieu-Daudé]

On 20/10/23 10:03, Zhao Liu wrote:
> Hi Philippe,
> 
> On Fri, Oct 13, 2023 at 04:01:11PM +0200, Philippe Mathieu-Daudé wrote:
>> Date: Fri, 13 Oct 2023 16:01:11 +0200
>> From: Philippe Mathieu-Daudé <philmd@linaro.org>
>> Subject: [PATCH v2 12/16] target: Move ArchCPUClass definition to 'cpu.h'
>> X-Mailer: git-send-email 2.41.0
>>
>> The OBJECT_DECLARE_CPU_TYPE() macro forward-declares each
>> ArchCPUClass type. These forward declarations are sufficient
>> for code in hw/ to use the QOM definitions. No need to expose
>> these structure definitions. Keep each local to their target/
>> by moving them to the corresponding "cpu.h" header.
>>
>> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   target/alpha/cpu-qom.h      | 16 ---------------
>>   target/alpha/cpu.h          | 13 +++++++++++++
>>   target/arm/cpu-qom.h        | 27 -------------------------
>>   target/arm/cpu.h            | 25 ++++++++++++++++++++++++
>>   target/avr/cpu-qom.h        | 16 ---------------
>>   target/avr/cpu.h            | 14 +++++++++++++
>>   target/cris/cpu-qom.h       | 19 ------------------
>>   target/cris/cpu.h           | 16 +++++++++++++++
>>   target/hexagon/cpu-qom.h    |  1 -
>>   target/hppa/cpu-qom.h       | 16 ---------------
>>   target/hppa/cpu.h           | 14 +++++++++++++
>>   target/i386/cpu-qom.h       | 39 -------------------------------------
>>   target/i386/cpu.h           | 35 +++++++++++++++++++++++++++++++++
>>   target/loongarch/cpu-qom.h  |  1 -
>>   target/m68k/cpu-qom.h       | 16 ---------------
>>   target/m68k/cpu.h           | 13 +++++++++++++
>>   target/microblaze/cpu-qom.h | 16 ---------------
>>   target/microblaze/cpu.h     | 13 +++++++++++++
>>   target/mips/cpu-qom.h       | 20 -------------------
>>   target/mips/cpu.h           | 17 ++++++++++++++++
>>   target/nios2/cpu-qom.h      |  1 -
>>   target/openrisc/cpu-qom.h   |  1 -
>>   target/riscv/cpu-qom.h      | 16 +--------------
>>   target/riscv/cpu.h          | 14 +++++++++++++
>>   target/rx/cpu-qom.h         | 15 --------------
>>   target/rx/cpu.h             | 14 +++++++++++++
>>   target/s390x/cpu-qom.h      | 37 +----------------------------------
>>   target/s390x/cpu.h          | 30 ++++++++++++++++++++++++++++
>>   target/s390x/cpu_models.h   |  8 ++++----
>>   target/sh4/cpu-qom.h        | 23 ----------------------
>>   target/sh4/cpu.h            | 20 +++++++++++++++++++
>>   target/sparc/cpu-qom.h      | 18 -----------------
>>   target/sparc/cpu.h          | 18 +++++++++++++++--
>>   target/tricore/cpu-qom.h    | 10 ----------
>>   target/tricore/cpu.h        |  6 ++++++
>>   target/xtensa/cpu-qom.h     | 21 --------------------
>>   target/xtensa/cpu.h         | 20 +++++++++++++++++--
>>   37 files changed, 284 insertions(+), 335 deletions(-)


>> diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
>> index dffc74c1ce..d4e216d000 100644
>> --- a/target/i386/cpu-qom.h
>> +++ b/target/i386/cpu-qom.h
>> @@ -21,8 +21,6 @@
>>   #define QEMU_I386_CPU_QOM_H
>>   
>>   #include "hw/core/cpu.h"
>> -#include "qemu/notify.h"
>> -#include "qom/object.h"
>>   
>>   #ifdef TARGET_X86_64
>>   #define TYPE_X86_CPU "x86_64-cpu"
>> @@ -35,41 +33,4 @@ OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
>>   #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
>>   #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
>>   
>> -typedef struct X86CPUModel X86CPUModel;
>> -
>> -/**
>> - * X86CPUClass:
>> - * @cpu_def: CPU model definition
>> - * @host_cpuid_required: Whether CPU model requires cpuid from host.
>> - * @ordering: Ordering on the "-cpu help" CPU model list.
>> - * @migration_safe: See CpuDefinitionInfo::migration_safe
>> - * @static_model: See CpuDefinitionInfo::static
>> - * @parent_realize: The parent class' realize handler.
>> - * @parent_phases: The parent class' reset phase handlers.
>> - *
>> - * An x86 CPU model or family.
>> - */
>> -struct X86CPUClass {
>> -    CPUClass parent_class;
>> -
>> -    /* CPU definition, automatically loaded by instance_init if not NULL.
>> -     * Should be eventually replaced by subclass-specific property defaults.
>> -     */
>> -    X86CPUModel *model;
>> -
>> -    bool host_cpuid_required;
>> -    int ordering;
>> -    bool migration_safe;
>> -    bool static_model;
>> -
>> -    /* Optional description of CPU model.
>> -     * If unavailable, cpu_def->model_id is used */
>> -    const char *model_description;
>> -
>> -    DeviceRealize parent_realize;
>> -    DeviceUnrealize parent_unrealize;
>> -    ResettablePhases parent_phases;
>> -};
>> -
>> -
>>   #endif
>> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
>> index 2dea4df086..e21d293daa 100644
>> --- a/target/i386/cpu.h
>> +++ b/target/i386/cpu.h
>> @@ -2037,6 +2037,41 @@ struct ArchCPU {
>>       bool xen_vapic;
>>   };
>>   
>> +typedef struct X86CPUModel X86CPUModel;
> 
> Could we "typedef" this structure at its definition?

No, because X86CPUClass uses the declaration in its 'model' field
in [*], so we have to forward-declare it first.

> Then this explicit "typedef" can also be omitted, just like you did
> elsewhere.
> 
>> +
>> +/**
>> + * X86CPUClass:
>> + * @cpu_def: CPU model definition
>> + * @host_cpuid_required: Whether CPU model requires cpuid from host.
>> + * @ordering: Ordering on the "-cpu help" CPU model list.
>> + * @migration_safe: See CpuDefinitionInfo::migration_safe
>> + * @static_model: See CpuDefinitionInfo::static
>> + * @parent_realize: The parent class' realize handler.
>> + * @parent_phases: The parent class' reset phase handlers.
>> + *
>> + * An x86 CPU model or family.
>> + */
>> +struct X86CPUClass {
>> +    CPUClass parent_class;
>> +
>> +    /* CPU definition, automatically loaded by instance_init if not NULL.
>> +     * Should be eventually replaced by subclass-specific property defaults.
>> +     */
>> +    X86CPUModel *model;

[*]     ^^^^^^^^^^^

>> +    bool host_cpuid_required;
>> +    int ordering;
>> +    bool migration_safe;
>> +    bool static_model;
>> +
>> +    /* Optional description of CPU model.
>> +     * If unavailable, cpu_def->model_id is used */
>> +    const char *model_description;
>> +
>> +    DeviceRealize parent_realize;
>> +    DeviceUnrealize parent_unrealize;
>> +    ResettablePhases parent_phases;
>> +};


>> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
>> index 76efb614a6..35ca5c4600 100644
>> --- a/target/riscv/cpu-qom.h
>> +++ b/target/riscv/cpu-qom.h
>> @@ -20,7 +20,6 @@
>>   #define RISCV_CPU_QOM_H
>>   
>>   #include "hw/core/cpu.h"
>> -#include "qom/object.h"
>>   
>>   #define TYPE_RISCV_CPU "riscv-cpu"
>>   #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
>> @@ -44,21 +43,8 @@
>>   #define TYPE_RISCV_CPU_VEYRON_V1        RISCV_CPU_TYPE_NAME("veyron-v1")
>>   #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
>>   
>> -typedef struct CPUArchState CPURISCVState;
>> +typedef struct CPUArchState CPURISCVState; // XXX
> 
> Is "// XXX" redundant?

Good catch, I forgot about this comment. I now simply moved that
to "cpu.h".

> 
>>   
>>   OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
>>   
>> -/**
>> - * RISCVCPUClass:
>> - * @parent_realize: The parent class' realize handler.
>> - * @parent_phases: The parent class' reset phase handlers.
>> - *
>> - * A RISCV CPU model.
>> - */
>> -struct RISCVCPUClass {
>> -    CPUClass parent_class;
>> -
>> -    DeviceRealize parent_realize;
>> -    ResettablePhases parent_phases;
>> -};
>>   #endif /* RISCV_CPU_QOM_H */
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index d832696418..a7edf95213 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -414,6 +414,20 @@ struct ArchCPU {
>>       GHashTable *pmu_event_ctr_map;
>>   };
>>   
>> +/**
>> + * RISCVCPUClass:
>> + * @parent_realize: The parent class' realize handler.
>> + * @parent_phases: The parent class' reset phase handlers.
>> + *
>> + * A RISCV CPU model.
>> + */
>> +struct RISCVCPUClass {
>> +    CPUClass parent_class;
>> +
>> +    DeviceRealize parent_realize;
>> +    ResettablePhases parent_phases;
>> +};
>> +


>> diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
>> index fcd70daddf..4037e31f79 100644
>> --- a/target/s390x/cpu-qom.h
>> +++ b/target/s390x/cpu-qom.h
>> @@ -21,7 +21,6 @@
>>   #define QEMU_S390_CPU_QOM_H
>>   
>>   #include "hw/core/cpu.h"
>> -#include "qom/object.h"
>>   
>>   #define TYPE_S390_CPU "s390x-cpu"
>>   
>> @@ -30,40 +29,6 @@ OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU)
>>   #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
>>   #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
>>   
>> -typedef struct S390CPUModel S390CPUModel;
>> -typedef struct S390CPUDef S390CPUDef;
>> -
>> -typedef struct CPUArchState CPUS390XState;
>> -
>> -typedef enum cpu_reset_type {
>> -    S390_CPU_RESET_NORMAL,
>> -    S390_CPU_RESET_INITIAL,
>> -    S390_CPU_RESET_CLEAR,
>> -} cpu_reset_type;
>> -
>> -/**
>> - * S390CPUClass:
>> - * @parent_realize: The parent class' realize handler.
>> - * @parent_reset: The parent class' reset handler.
>> - * @load_normal: Performs a load normal.
>> - * @cpu_reset: Performs a CPU reset.
>> - * @initial_cpu_reset: Performs an initial CPU reset.
>> - *
>> - * An S/390 CPU model.
>> - */
>> -struct S390CPUClass {
>> -    CPUClass parent_class;
>> -
>> -    const S390CPUDef *cpu_def;
>> -    bool kvm_required;
>> -    bool is_static;
>> -    bool is_migration_safe;
>> -    const char *desc;
>> -
>> -    DeviceRealize parent_realize;
>> -    DeviceReset parent_reset;
>> -    void (*load_normal)(CPUState *cpu);
>> -    void (*reset)(CPUState *cpu, cpu_reset_type type);
>> -};
>> +typedef struct CPUArchState CPUS390XState; // XXX
> 
> same here.

Oops, I forgot to send the preliminary series required to
remove that comment, see:
https://lore.kernel.org/qemu-devel/20231106114500.5269-1-philmd@linaro.org/

> Just the above nits. Otherwise,
> 
> Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

Thanks for your careful review!