From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: pbonzini@redhat.com
Subject: [PATCH v2 0/2] tcg: Streamline vector load/store
Date: Fri, 13 Oct 2023 10:51:07 -0700 [thread overview]
Message-ID: <20231013175109.124308-1-richard.henderson@linaro.org> (raw)
We have tcg_gen_qemu_{ld,st}_i128, which can be used to implement
load/store of vectors to guest memory. But at present we have to
split into, or concatenated from, two i64 to reference the guest
vector register backing store within env.
Provide tcg_gen_{ld,st}_i128, which can avoid the trip through i64.
This does require that the target store i128 in host byte ordering,
which is true of i386 (and some other backends) but not arm or s390x.
There is definitely further cleanup possible.
Changes for v2:
* Set atomicity for x86 vector operations.
r~
Richard Henderson (2):
tcg: Add tcg_gen_{ld,st}_i128
target/i386: Use i128 for 128 and 256-bit loads and stores
include/tcg/tcg-op-common.h | 3 ++
target/i386/tcg/translate.c | 63 +++++++++++++++++--------------------
tcg/tcg-op.c | 22 +++++++++++++
3 files changed, 54 insertions(+), 34 deletions(-)
--
2.34.1
next reply other threads:[~2023-10-13 17:52 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-13 17:51 Richard Henderson [this message]
2023-10-13 17:51 ` [PATCH v2 1/2] tcg: Add tcg_gen_{ld,st}_i128 Richard Henderson
2023-10-17 11:48 ` Philippe Mathieu-Daudé
2023-10-18 1:19 ` gaosong
2023-10-18 5:03 ` Philippe Mathieu-Daudé
2023-10-13 17:51 ` [PATCH v2 2/2] target/i386: Use i128 for 128 and 256-bit loads and stores Richard Henderson
2023-10-17 11:52 ` [PATCH v2 0/2] tcg: Streamline vector load/store Philippe Mathieu-Daudé
2023-10-17 13:38 ` Richard Henderson
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