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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com
Subject: [PATCH 36/85] target/sparc: Move JMPL, RETT, RETURN to decodetree
Date: Fri, 13 Oct 2023 14:27:57 -0700	[thread overview]
Message-ID: <20231013212846.165724-37-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/insns.decode |   6 ++
 target/sparc/translate.c  | 121 +++++++++++++++++++++++---------------
 2 files changed, 79 insertions(+), 48 deletions(-)

diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index a124fdeaac..d8ebebce53 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -212,6 +212,12 @@ MOVcc       10 rd:5  101100 1 cond:4 imm:1 cc:1 0 rs2_or_imm:s11
 MOVfcc      10 rd:5  101100 0 cond:4 imm:1 cc:2   rs2_or_imm:s11
 MOVR        10 rd:5  101111 rs1:5    imm:1 cond:3 rs2_or_imm:s10
 
+JMPL        10 ..... 111000 ..... . .............          @r_r_ri
+{
+  RETT      10 00000 111001 ..... . .............          @n_r_ri
+  RETURN    10 00000 111001 ..... . .............          @n_r_ri
+}
+
 NCP         10 ----- 110110 ----- --------- -----          # v8 CPop1
 NCP         10 ----- 110111 ----- --------- -----          # v8 CPop2
 
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 72f3cbab47..47a281dc38 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -40,6 +40,7 @@
 #define gen_helper_rdpsr(D, E)          qemu_build_not_reached()
 #define gen_helper_wrpsr(E, S)          qemu_build_not_reached()
 #define gen_helper_power_down(E)        g_assert_not_reached()
+#define gen_helper_rett(E)              qemu_build_not_reached()
 #else
 #define gen_helper_rdccr(D, E)          qemu_build_not_reached()
 #define gen_helper_rdcwp(D, E)          qemu_build_not_reached()
@@ -4388,6 +4389,77 @@ static bool trans_MOVR(DisasContext *dc, arg_MOVR *a)
     return do_mov_cond(dc, &cmp, a->rd, src2);
 }
 
+static bool do_add_special(DisasContext *dc, arg_r_r_ri *a,
+                           bool (*func)(DisasContext *dc, int rd, TCGv src))
+{
+    TCGv src1, src;
+
+    /* For simplicity, we under-decoded the rs2 form. */
+    if (!a->imm && a->rs2_or_imm & ~0x1f) {
+        return false;
+    }
+
+    src1 = gen_load_gpr(dc, a->rs1);
+    if (a->rs2_or_imm == 0) {
+        src = src1;
+    } else {
+        src = tcg_temp_new();
+        if (a->imm) {
+            tcg_gen_addi_tl(src, src1, a->rs2_or_imm);
+        } else {
+            tcg_gen_add_tl(src, src1, cpu_regs[a->rs2_or_imm]);
+        }
+    }
+    return func(dc, a->rd, src);
+}
+
+static bool do_jmpl(DisasContext *dc, int rd, TCGv src)
+{
+    gen_check_align(src, 3);
+
+    gen_store_gpr(dc, rd, tcg_constant_tl(dc->pc));
+    gen_mov_pc_npc(dc);
+    tcg_gen_mov_tl(cpu_npc, src);
+    gen_address_mask(dc, cpu_npc);
+
+    dc->npc = DYNAMIC_PC_LOOKUP;
+    return true;
+}
+
+TRANS(JMPL, ALL, do_add_special, a, do_jmpl)
+
+static bool do_rett(DisasContext *dc, int rd, TCGv src)
+{
+    if (!supervisor(dc)) {
+        return raise_priv(dc);
+    }
+
+    gen_check_align(src, 3);
+
+    gen_mov_pc_npc(dc);
+    tcg_gen_mov_tl(cpu_npc, src);
+    dc->npc = DYNAMIC_PC;
+    gen_helper_rett(tcg_env);
+    return true;
+}
+
+TRANS(RETT, 32, do_add_special, a, do_rett)
+
+static bool do_return(DisasContext *dc, int rd, TCGv src)
+{
+    gen_check_align(src, 3);
+
+    gen_mov_pc_npc(dc);
+    tcg_gen_mov_tl(cpu_npc, src);
+    gen_address_mask(dc, cpu_npc);
+
+    gen_helper_restore(tcg_env);
+    dc->npc = DYNAMIC_PC_LOOKUP;
+    return true;
+}
+
+TRANS(RETURN, 64, do_add_special, a, do_return)
+
 #define CHECK_IU_FEATURE(dc, FEATURE)                      \
     if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE))  \
         goto illegal_insn;
@@ -5185,30 +5257,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
             } else if (xop == 0x37) {
                 /* V8 CPop2, V9 impdep2 */
                 goto illegal_insn; /* in decodetree */
-#ifdef TARGET_SPARC64
-            } else if (xop == 0x39) { /* V9 return */
-                save_state(dc);
-                cpu_src1 = get_src1(dc, insn);
-                cpu_tmp0 = tcg_temp_new();
-                if (IS_IMM) {   /* immediate */
-                    simm = GET_FIELDs(insn, 19, 31);
-                    tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
-                } else {                /* register */
-                    rs2 = GET_FIELD(insn, 27, 31);
-                    if (rs2) {
-                        cpu_src2 = gen_load_gpr(dc, rs2);
-                        tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2);
-                    } else {
-                        tcg_gen_mov_tl(cpu_tmp0, cpu_src1);
-                    }
-                }
-                gen_helper_restore(tcg_env);
-                gen_mov_pc_npc(dc);
-                gen_check_align(cpu_tmp0, 3);
-                tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
-                dc->npc = DYNAMIC_PC_LOOKUP;
-                goto jmp_insn;
-#endif
             } else {
                 cpu_src1 = get_src1(dc, insn);
                 cpu_tmp0 = tcg_temp_new();
@@ -5226,31 +5274,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
                 }
                 switch (xop) {
                 case 0x38:      /* jmpl */
-                    {
-                        TCGv t = gen_dest_gpr(dc, rd);
-                        tcg_gen_movi_tl(t, dc->pc);
-                        gen_store_gpr(dc, rd, t);
-
-                        gen_mov_pc_npc(dc);
-                        gen_check_align(cpu_tmp0, 3);
-                        gen_address_mask(dc, cpu_tmp0);
-                        tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
-                        dc->npc = DYNAMIC_PC_LOOKUP;
-                    }
-                    goto jmp_insn;
-#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
                 case 0x39:      /* rett, V9 return */
-                    {
-                        if (!supervisor(dc))
-                            goto priv_insn;
-                        gen_mov_pc_npc(dc);
-                        gen_check_align(cpu_tmp0, 3);
-                        tcg_gen_mov_tl(cpu_npc, cpu_tmp0);
-                        dc->npc = DYNAMIC_PC;
-                        gen_helper_rett(tcg_env);
-                    }
-                    goto jmp_insn;
-#endif
+                    g_assert_not_reached();  /* in decode tree */
                 case 0x3b: /* flush */
                     /* nop */
                     break;
-- 
2.34.1



  parent reply	other threads:[~2023-10-13 21:31 UTC|newest]

Thread overview: 95+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-13 21:27 [PATCH 00/85] target/sparc: Convert to decodetree Richard Henderson
2023-10-13 21:27 ` [PATCH 01/85] target/sparc: Set TCG_GUEST_DEFAULT_MO Richard Henderson
2023-10-16  6:46   ` Philippe Mathieu-Daudé
2023-10-13 21:27 ` [PATCH 02/85] configs: Enable MTTCG for sparc, sparc64 Richard Henderson
2023-10-13 21:27 ` [PATCH 03/85] target/sparc: Remove always-set cpu features Richard Henderson
2023-10-15 16:53   ` Richard Henderson
2023-10-13 21:27 ` [PATCH 04/85] target/sparc: Add decodetree infrastructure Richard Henderson
2023-10-13 21:27 ` [PATCH 05/85] target/sparc: Define AM_CHECK for sparc32 Richard Henderson
2023-10-13 21:27 ` [PATCH 06/85] target/sparc: Move CALL to decodetree Richard Henderson
2023-10-13 21:27 ` [PATCH 07/85] target/sparc: Move BPcc and Bicc " Richard Henderson
2023-10-13 21:27 ` [PATCH 08/85] target/sparc: Move BPr " Richard Henderson
2023-10-13 21:27 ` [PATCH 09/85] target/sparc: Move FBPfcc and FBfcc " Richard Henderson
2025-01-26  9:38   ` Artyom Tarasenko
2025-01-26 12:25     ` Richard Henderson
2023-10-13 21:27 ` [PATCH 10/85] target/sparc: Merge gen_cond with only caller Richard Henderson
2023-10-16  6:52   ` Philippe Mathieu-Daudé
2023-10-13 21:27 ` [PATCH 11/85] target/sparc: Merge gen_fcond " Richard Henderson
2023-10-16  6:52   ` Philippe Mathieu-Daudé
2023-10-13 21:27 ` [PATCH 12/85] target/sparc: Merge gen_branch_[an] " Richard Henderson
2023-10-13 21:27 ` [PATCH 13/85] target/sparc: Pass DisasCompare to advance_jump_cond Richard Henderson
2023-10-13 21:27 ` [PATCH 14/85] target/sparc: Move SETHI to decodetree Richard Henderson
2023-10-13 21:27 ` [PATCH 15/85] target/sparc: Move Tcc " Richard Henderson
2023-10-13 21:27 ` [PATCH 16/85] target/sparc: Move RDASR, STBAR, MEMBAR " Richard Henderson
2023-10-13 21:27 ` [PATCH 17/85] target/sparc: Move RDPSR, RDHPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 18/85] target/sparc: Move RDWIM, RDPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 19/85] target/sparc: Move RDTBR, FLUSHW " Richard Henderson
2023-10-13 21:27 ` [PATCH 20/85] target/sparc: Move WRASR " Richard Henderson
2023-10-13 21:27 ` [PATCH 21/85] target/sparc: Move WRPSR, SAVED, RESTORED " Richard Henderson
2023-10-13 21:27 ` [PATCH 22/85] target/sparc: Move WRWIM, WRPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 23/85] target/sparc: Move WRTBR, WRHPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 24/85] target/sparc: Move basic arithmetic " Richard Henderson
2023-10-13 21:27 ` [PATCH 25/85] target/sparc: Move ADDC " Richard Henderson
2023-10-13 21:27 ` [PATCH 26/85] target/sparc: Move MULX " Richard Henderson
2023-10-13 21:27 ` [PATCH 27/85] target/sparc: Move UMUL, SMUL " Richard Henderson
2023-10-13 21:27 ` [PATCH 28/85] target/sparc: Move SUBC " Richard Henderson
2023-10-13 21:27 ` [PATCH 29/85] target/sparc: Move UDIVX, SDIVX " Richard Henderson
2023-10-13 21:27 ` [PATCH 30/85] target/sparc: Move UDIV, SDIV " Richard Henderson
2023-10-13 21:27 ` [PATCH 31/85] target/sparc: Move TADD, TSUB, MULS " Richard Henderson
2023-10-13 21:27 ` [PATCH 32/85] target/sparc: Move SLL, SRL, SRA " Richard Henderson
2023-10-13 21:27 ` [PATCH 33/85] target/sparc: Move MOVcc, MOVR " Richard Henderson
2023-10-13 21:27 ` [PATCH 34/85] target/sparc: Move POPC " Richard Henderson
2023-10-13 21:27 ` [PATCH 35/85] target/sparc: Convert remaining v8 coproc insns " Richard Henderson
2023-10-13 21:27 ` Richard Henderson [this message]
2023-10-13 21:27 ` [PATCH 37/85] target/sparc: Move FLUSH, SAVE, RESTORE " Richard Henderson
2023-10-13 21:27 ` [PATCH 38/85] target/sparc: Move DONE, RETRY " Richard Henderson
2023-10-13 21:28 ` [PATCH 39/85] target/sparc: Split out resolve_asi Richard Henderson
2023-10-13 21:28 ` [PATCH 40/85] target/sparc: Drop ifdef around get_asi and friends Richard Henderson
2023-10-13 21:28 ` [PATCH 41/85] target/sparc: Split out ldst functions with asi pre-computed Richard Henderson
2023-10-13 21:28 ` [PATCH 42/85] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX Richard Henderson
2023-10-13 21:28 ` [PATCH 43/85] target/sparc: Move simple integer load/store to decodetree Richard Henderson
2023-10-13 21:28 ` [PATCH 44/85] target/sparc: Move asi " Richard Henderson
2023-10-13 21:28 ` [PATCH 45/85] target/sparc: Move LDSTUB, LDSTUBA " Richard Henderson
2023-10-13 21:28 ` [PATCH 46/85] target/sparc: Move SWAP, SWAPA " Richard Henderson
2023-10-13 21:28 ` [PATCH 47/85] target/sparc: Move CASA, CASXA " Richard Henderson
2023-10-13 21:28 ` [PATCH 48/85] target/sparc: Move PREFETCH, PREFETCHA " Richard Henderson
2023-10-13 21:28 ` [PATCH 49/85] target/sparc: Split out fp ldst functions with asi precomputed Richard Henderson
2023-10-13 21:28 ` [PATCH 50/85] target/sparc: Move simple fp load/store to decodetree Richard Henderson
2023-10-13 21:28 ` [PATCH 51/85] target/sparc: Move asi " Richard Henderson
2023-10-13 21:28 ` [PATCH 52/85] target/sparc: Move LDFSR, STFSR " Richard Henderson
2023-10-13 21:28 ` [PATCH 53/85] target/sparc: Merge LDFSR, LDXFSR implementations Richard Henderson
2023-10-13 21:28 ` [PATCH 54/85] target/sparc: Move EDGE* to decodetree Richard Henderson
2023-10-13 21:28 ` [PATCH 55/85] target/sparc: Move ARRAY* " Richard Henderson
2023-10-13 21:28 ` [PATCH 56/85] target/sparc: Move ADDRALIGN* " Richard Henderson
2023-10-13 21:28 ` [PATCH 57/85] target/sparc: Move BMASK " Richard Henderson
2023-10-13 21:28 ` [PATCH 58/85] target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S " Richard Henderson
2023-10-13 21:28 ` [PATCH 59/85] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D " Richard Henderson
2023-10-13 21:28 ` [PATCH 60/85] target/sparc: Use tcg_gen_vec_{add,sub}* Richard Henderson
2023-10-13 21:28 ` [PATCH 61/85] target/sparc: Move gen_ne_fop_FFF insns to decodetree Richard Henderson
2023-10-13 21:28 ` [PATCH 62/85] target/sparc: Move gen_ne_fop_DDD " Richard Henderson
2023-10-13 21:28 ` [PATCH 63/85] target/sparc: Move PDIST " Richard Henderson
2023-10-13 21:28 ` [PATCH 64/85] target/sparc: Move gen_gsr_fop_DDD insns " Richard Henderson
2023-10-13 21:28 ` [PATCH 65/85] target/sparc: Move gen_fop_FF " Richard Henderson
2023-10-13 21:28 ` [PATCH 66/85] target/sparc: Move gen_fop_DD " Richard Henderson
2023-10-13 21:28 ` [PATCH 67/85] target/sparc: Move FSQRTq " Richard Henderson
2023-10-13 21:28 ` [PATCH 68/85] target/sparc: Move gen_fop_FFF insns " Richard Henderson
2023-10-13 21:28 ` [PATCH 69/85] target/sparc: Move gen_fop_DDD " Richard Henderson
2023-10-13 21:28 ` [PATCH 70/85] target/sparc: Move gen_fop_QQQ " Richard Henderson
2023-10-13 21:28 ` [PATCH 71/85] target/sparc: Move FSMULD " Richard Henderson
2023-10-13 21:28 ` [PATCH 72/85] target/sparc: Move FDMULQ " Richard Henderson
2023-10-13 21:28 ` [PATCH 73/85] target/sparc: Move gen_fop_FD insns " Richard Henderson
2023-10-13 21:28 ` [PATCH 74/85] target/sparc: Move FiTOd, FsTOd, FsTOx " Richard Henderson
2023-10-13 21:28 ` [PATCH 75/85] target/sparc: Move FqTOs, FqTOi " Richard Henderson
2023-10-13 21:28 ` [PATCH 76/85] target/sparc: Move FqTOd, FqTOx " Richard Henderson
2023-10-13 21:28 ` [PATCH 77/85] target/sparc: Move FiTOq, FsTOq " Richard Henderson
2023-10-13 21:28 ` [PATCH 78/85] target/sparc: Move FdTOq, FxTOq " Richard Henderson
2023-10-13 21:28 ` [PATCH 79/85] target/sparc: Move FMOVq, FNEGq, FABSq " Richard Henderson
2023-10-13 21:28 ` [PATCH 80/85] target/sparc: Move FMOVR, FMOVcc, FMOVfcc " Richard Henderson
2023-10-13 21:28 ` [PATCH 81/85] target/sparc: Convert FCMP, FCMPE " Richard Henderson
2023-10-13 21:28 ` [PATCH 82/85] target/sparc: Move FPCMP* " Richard Henderson
2023-10-13 21:28 ` [PATCH 83/85] target/sparc: Move FPACK16, FPACKFIX " Richard Henderson
2023-10-13 21:28 ` [PATCH 84/85] target/sparc: Convert FZERO, FONE " Richard Henderson
2023-10-13 21:28 ` [PATCH 85/85] target/sparc: Remove disas_sparc_legacy Richard Henderson
2023-10-14  6:32 ` [PATCH 00/85] target/sparc: Convert to decodetree Mark Cave-Ayland
2023-10-15 20:12 ` Mark Cave-Ayland
2023-10-15 22:38   ` Richard Henderson

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