From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com
Subject: [PATCH 44/85] target/sparc: Move asi integer load/store to decodetree
Date: Fri, 13 Oct 2023 14:28:05 -0700 [thread overview]
Message-ID: <20231013212846.165724-45-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org>
Move LDDA, LDSBA, LDSHA, LDSWA, LDUBA, LDUHA, LDUWA, LDXA,
STBA, STDA, STHA, STWA, STXA.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 31 +++++++++
target/sparc/translate.c | 128 +++++---------------------------------
2 files changed, 48 insertions(+), 111 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 41fbda4eb8..fd9e268a0e 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -231,6 +231,9 @@ RETRY 10 00001 111110 00000 0 0000000000000
&r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool
@r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi=-1
+@r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm=0
+@r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \
+ &r_r_ri_asi imm=1 asi=-2
LDUW 11 ..... 000000 ..... . ............. @r_r_ri_na
LDUB 11 ..... 000001 ..... . ............. @r_r_ri_na
@@ -247,6 +250,34 @@ STH 11 ..... 000110 ..... . ............. @r_r_ri_na
STD 11 ..... 000111 ..... . ............. @r_r_ri_na
STX 11 ..... 001110 ..... . ............. @r_r_ri_na
+LDUW 11 ..... 010000 ..... . ............. @r_r_r_asi # LDUWA
+LDUW 11 ..... 010000 ..... . ............. @r_r_i_asi # LDUWA
+LDUB 11 ..... 010001 ..... . ............. @r_r_r_asi # LDUBA
+LDUB 11 ..... 010001 ..... . ............. @r_r_i_asi # LDUBA
+LDUH 11 ..... 010010 ..... . ............. @r_r_r_asi # LDUHA
+LDUH 11 ..... 010010 ..... . ............. @r_r_i_asi # LDUHA
+LDD 11 ..... 010011 ..... . ............. @r_r_r_asi # LDDA
+LDD 11 ..... 010011 ..... . ............. @r_r_i_asi # LDDA
+LDX 11 ..... 011011 ..... . ............. @r_r_r_asi # LDXA
+LDX 11 ..... 011011 ..... . ............. @r_r_i_asi # LDXA
+LDSB 11 ..... 011001 ..... . ............. @r_r_r_asi # LDSBA
+LDSB 11 ..... 011001 ..... . ............. @r_r_i_asi # LDSBA
+LDSH 11 ..... 011010 ..... . ............. @r_r_r_asi # LDSHA
+LDSH 11 ..... 011010 ..... . ............. @r_r_i_asi # LDSHA
+LDSW 11 ..... 011000 ..... . ............. @r_r_r_asi # LDSWA
+LDSW 11 ..... 011000 ..... . ............. @r_r_i_asi # LDSWA
+
+STW 11 ..... 010100 ..... . ............. @r_r_r_asi # STWA
+STW 11 ..... 010100 ..... . ............. @r_r_i_asi # STWA
+STB 11 ..... 010101 ..... . ............. @r_r_r_asi # STBA
+STB 11 ..... 010101 ..... . ............. @r_r_i_asi # STBA
+STH 11 ..... 010110 ..... . ............. @r_r_r_asi # STHA
+STH 11 ..... 010110 ..... . ............. @r_r_i_asi # STHA
+STD 11 ..... 010111 ..... . ............. @r_r_r_asi # STDA
+STD 11 ..... 010111 ..... . ............. @r_r_i_asi # STDA
+STX 11 ..... 011110 ..... . ............. @r_r_r_asi # STXA
+STX 11 ..... 011110 ..... . ............. @r_r_i_asi # STXA
+
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 7b7437dbd8..11f885822f 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2056,7 +2056,7 @@ static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop)
return resolve_asi(dc, asi, memop);
}
-static void gen_ld_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr)
+static void gen_ld_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr)
{
switch (da->type) {
case GET_ASI_EXCP:
@@ -2087,16 +2087,7 @@ static void gen_ld_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr)
}
}
-static void __attribute__((unused))
-gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop)
-{
- DisasASI da = get_asi(dc, insn, memop);
-
- gen_address_mask(dc, addr);
- gen_ld_asi0(dc, &da, dst, addr);
-}
-
-static void gen_st_asi0(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr)
+static void gen_st_asi(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr)
{
switch (da->type) {
case GET_ASI_EXCP:
@@ -2168,15 +2159,6 @@ static void gen_st_asi0(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr)
}
}
-static void __attribute__((unused))
-gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop)
-{
- DisasASI da = get_asi(dc, insn, memop);
-
- gen_address_mask(dc, addr);
- gen_st_asi0(dc, &da, src, addr);
-}
-
static void gen_swap_asi0(DisasContext *dc, DisasASI *da,
TCGv dst, TCGv src, TCGv addr)
{
@@ -2478,7 +2460,7 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
}
}
-static void gen_ldda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
+static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
{
TCGv hi = gen_dest_gpr(dc, rd);
TCGv lo = gen_dest_gpr(dc, rd + 1);
@@ -2554,16 +2536,7 @@ static void gen_ldda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
gen_store_gpr(dc, rd + 1, lo);
}
-static void __attribute__((unused))
-gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
-{
- DisasASI da = get_asi(dc, insn, MO_TEUQ);
-
- gen_address_mask(dc, addr);
- gen_ldda_asi0(dc, &da, addr, rd);
-}
-
-static void gen_stda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
+static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
{
TCGv hi = gen_load_gpr(dc, rd);
TCGv lo = gen_load_gpr(dc, rd + 1);
@@ -2655,15 +2628,6 @@ static void gen_stda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
}
}
-static void __attribute__((unused))
-gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd)
-{
- DisasASI da = get_asi(dc, insn, MO_TEUQ);
-
- gen_address_mask(dc, addr);
- gen_stda_asi0(dc, &da, addr, rd);
-}
-
static TCGv get_src1(DisasContext *dc, unsigned int insn)
{
unsigned int rs1 = GET_FIELD(insn, 13, 17);
@@ -4592,7 +4556,7 @@ static bool do_ld_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop)
da = resolve_asi(dc, a->asi, mop);
reg = gen_dest_gpr(dc, a->rd);
- gen_ld_asi0(dc, &da, reg, addr);
+ gen_ld_asi(dc, &da, reg, addr);
gen_store_gpr(dc, a->rd, reg);
return advance_pc(dc);
}
@@ -4616,7 +4580,7 @@ static bool do_st_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop)
da = resolve_asi(dc, a->asi, mop);
reg = gen_load_gpr(dc, a->rd);
- gen_st_asi0(dc, &da, reg, addr);
+ gen_st_asi(dc, &da, reg, addr);
return advance_pc(dc);
}
@@ -4638,7 +4602,7 @@ static bool trans_LDD(DisasContext *dc, arg_r_r_ri_asi *a)
return false;
}
da = resolve_asi(dc, a->asi, MO_TEUQ);
- gen_ldda_asi0(dc, &da, addr, a->rd);
+ gen_ldda_asi(dc, &da, addr, a->rd);
return advance_pc(dc);
}
@@ -4655,7 +4619,7 @@ static bool trans_STD(DisasContext *dc, arg_r_r_ri_asi *a)
return false;
}
da = resolve_asi(dc, a->asi, MO_TEUQ);
- gen_stda_asi0(dc, &da, addr, a->rd);
+ gen_stda_asi(dc, &da, addr, a->rd);
return advance_pc(dc);
}
@@ -5487,9 +5451,17 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x3: /* ldd, load double word */
case 0x9: /* ldsb, load signed byte */
case 0xa: /* ldsh, load signed halfword */
+ case 0x10: /* lda, V9 lduwa, load word alternate */
+ case 0x11: /* lduba, load unsigned byte alternate */
+ case 0x12: /* lduha, load unsigned halfword alternate */
+ case 0x13: /* ldda, load double word alternate */
+ case 0x19: /* ldsba, load signed byte alternate */
+ case 0x1a: /* ldsha, load signed halfword alternate */
g_assert_not_reached(); /* in decodetree */
case 0x08: /* V9 ldsw */
case 0x0b: /* V9 ldx */
+ case 0x18: /* V9 ldswa */
+ case 0x1b: /* V9 ldxa */
goto illegal_insn; /* in decodetree */
case 0xd: /* ldstub */
gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
@@ -5501,27 +5473,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
dc->mem_idx, MO_TEUL);
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
- case 0x10: /* lda, V9 lduwa, load word alternate */
- gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
- break;
- case 0x11: /* lduba, load unsigned byte alternate */
- gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
- break;
- case 0x12: /* lduha, load unsigned halfword alternate */
- gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
- break;
- case 0x13: /* ldda, load double word alternate */
- if (rd & 1) {
- goto illegal_insn;
- }
- gen_ldda_asi(dc, cpu_addr, insn, rd);
- goto skip_move;
- case 0x19: /* ldsba, load signed byte alternate */
- gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB);
- break;
- case 0x1a: /* ldsha, load signed halfword alternate */
- gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW);
- break;
case 0x1d: /* ldstuba -- XXX: should be atomically */
gen_ldstub_asi(dc, cpu_val, cpu_addr, insn);
break;
@@ -5532,12 +5483,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
break;
#endif
#ifdef TARGET_SPARC64
- case 0x18: /* V9 ldswa */
- gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
- break;
- case 0x1b: /* V9 ldxa */
- gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ);
- break;
case 0x2d: /* V9 prefetch, no effect */
goto skip_move;
case 0x30: /* V9 ldfa */
@@ -5569,7 +5514,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
goto illegal_insn;
}
gen_store_gpr(dc, rd, cpu_val);
-#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
+#if defined(TARGET_SPARC64)
skip_move: ;
#endif
} else if (xop >= 0x20 && xop < 0x24) {
@@ -5622,45 +5567,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
default:
goto illegal_insn;
}
- } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) ||
- xop == 0xe || xop == 0x1e) {
-#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
- TCGv cpu_val = gen_load_gpr(dc, rd);
-#endif
-
- switch (xop) {
- case 0x4: /* st, store word */
- case 0x5: /* stb, store byte */
- case 0x6: /* sth, store halfword */
- case 0x7: /* std, store double word */
- g_assert_not_reached(); /* in decodetree */
- case 0x0e: /* V9 stx */
- goto illegal_insn; /* in decodetree */
-#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
- case 0x14: /* sta, V9 stwa, store word alternate */
- gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
- break;
- case 0x15: /* stba, store byte alternate */
- gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
- break;
- case 0x16: /* stha, store halfword alternate */
- gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
- break;
- case 0x17: /* stda, store double word alternate */
- if (rd & 1) {
- goto illegal_insn;
- }
- gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd);
- break;
-#endif
-#ifdef TARGET_SPARC64
- case 0x1e: /* V9 stxa */
- gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ);
- break;
-#endif
- default:
- goto illegal_insn;
- }
} else if (xop > 0x23 && xop < 0x28) {
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
--
2.34.1
next prev parent reply other threads:[~2023-10-13 21:35 UTC|newest]
Thread overview: 95+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-13 21:27 [PATCH 00/85] target/sparc: Convert to decodetree Richard Henderson
2023-10-13 21:27 ` [PATCH 01/85] target/sparc: Set TCG_GUEST_DEFAULT_MO Richard Henderson
2023-10-16 6:46 ` Philippe Mathieu-Daudé
2023-10-13 21:27 ` [PATCH 02/85] configs: Enable MTTCG for sparc, sparc64 Richard Henderson
2023-10-13 21:27 ` [PATCH 03/85] target/sparc: Remove always-set cpu features Richard Henderson
2023-10-15 16:53 ` Richard Henderson
2023-10-13 21:27 ` [PATCH 04/85] target/sparc: Add decodetree infrastructure Richard Henderson
2023-10-13 21:27 ` [PATCH 05/85] target/sparc: Define AM_CHECK for sparc32 Richard Henderson
2023-10-13 21:27 ` [PATCH 06/85] target/sparc: Move CALL to decodetree Richard Henderson
2023-10-13 21:27 ` [PATCH 07/85] target/sparc: Move BPcc and Bicc " Richard Henderson
2023-10-13 21:27 ` [PATCH 08/85] target/sparc: Move BPr " Richard Henderson
2023-10-13 21:27 ` [PATCH 09/85] target/sparc: Move FBPfcc and FBfcc " Richard Henderson
2025-01-26 9:38 ` Artyom Tarasenko
2025-01-26 12:25 ` Richard Henderson
2023-10-13 21:27 ` [PATCH 10/85] target/sparc: Merge gen_cond with only caller Richard Henderson
2023-10-16 6:52 ` Philippe Mathieu-Daudé
2023-10-13 21:27 ` [PATCH 11/85] target/sparc: Merge gen_fcond " Richard Henderson
2023-10-16 6:52 ` Philippe Mathieu-Daudé
2023-10-13 21:27 ` [PATCH 12/85] target/sparc: Merge gen_branch_[an] " Richard Henderson
2023-10-13 21:27 ` [PATCH 13/85] target/sparc: Pass DisasCompare to advance_jump_cond Richard Henderson
2023-10-13 21:27 ` [PATCH 14/85] target/sparc: Move SETHI to decodetree Richard Henderson
2023-10-13 21:27 ` [PATCH 15/85] target/sparc: Move Tcc " Richard Henderson
2023-10-13 21:27 ` [PATCH 16/85] target/sparc: Move RDASR, STBAR, MEMBAR " Richard Henderson
2023-10-13 21:27 ` [PATCH 17/85] target/sparc: Move RDPSR, RDHPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 18/85] target/sparc: Move RDWIM, RDPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 19/85] target/sparc: Move RDTBR, FLUSHW " Richard Henderson
2023-10-13 21:27 ` [PATCH 20/85] target/sparc: Move WRASR " Richard Henderson
2023-10-13 21:27 ` [PATCH 21/85] target/sparc: Move WRPSR, SAVED, RESTORED " Richard Henderson
2023-10-13 21:27 ` [PATCH 22/85] target/sparc: Move WRWIM, WRPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 23/85] target/sparc: Move WRTBR, WRHPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 24/85] target/sparc: Move basic arithmetic " Richard Henderson
2023-10-13 21:27 ` [PATCH 25/85] target/sparc: Move ADDC " Richard Henderson
2023-10-13 21:27 ` [PATCH 26/85] target/sparc: Move MULX " Richard Henderson
2023-10-13 21:27 ` [PATCH 27/85] target/sparc: Move UMUL, SMUL " Richard Henderson
2023-10-13 21:27 ` [PATCH 28/85] target/sparc: Move SUBC " Richard Henderson
2023-10-13 21:27 ` [PATCH 29/85] target/sparc: Move UDIVX, SDIVX " Richard Henderson
2023-10-13 21:27 ` [PATCH 30/85] target/sparc: Move UDIV, SDIV " Richard Henderson
2023-10-13 21:27 ` [PATCH 31/85] target/sparc: Move TADD, TSUB, MULS " Richard Henderson
2023-10-13 21:27 ` [PATCH 32/85] target/sparc: Move SLL, SRL, SRA " Richard Henderson
2023-10-13 21:27 ` [PATCH 33/85] target/sparc: Move MOVcc, MOVR " Richard Henderson
2023-10-13 21:27 ` [PATCH 34/85] target/sparc: Move POPC " Richard Henderson
2023-10-13 21:27 ` [PATCH 35/85] target/sparc: Convert remaining v8 coproc insns " Richard Henderson
2023-10-13 21:27 ` [PATCH 36/85] target/sparc: Move JMPL, RETT, RETURN " Richard Henderson
2023-10-13 21:27 ` [PATCH 37/85] target/sparc: Move FLUSH, SAVE, RESTORE " Richard Henderson
2023-10-13 21:27 ` [PATCH 38/85] target/sparc: Move DONE, RETRY " Richard Henderson
2023-10-13 21:28 ` [PATCH 39/85] target/sparc: Split out resolve_asi Richard Henderson
2023-10-13 21:28 ` [PATCH 40/85] target/sparc: Drop ifdef around get_asi and friends Richard Henderson
2023-10-13 21:28 ` [PATCH 41/85] target/sparc: Split out ldst functions with asi pre-computed Richard Henderson
2023-10-13 21:28 ` [PATCH 42/85] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX Richard Henderson
2023-10-13 21:28 ` [PATCH 43/85] target/sparc: Move simple integer load/store to decodetree Richard Henderson
2023-10-13 21:28 ` Richard Henderson [this message]
2023-10-13 21:28 ` [PATCH 45/85] target/sparc: Move LDSTUB, LDSTUBA " Richard Henderson
2023-10-13 21:28 ` [PATCH 46/85] target/sparc: Move SWAP, SWAPA " Richard Henderson
2023-10-13 21:28 ` [PATCH 47/85] target/sparc: Move CASA, CASXA " Richard Henderson
2023-10-13 21:28 ` [PATCH 48/85] target/sparc: Move PREFETCH, PREFETCHA " Richard Henderson
2023-10-13 21:28 ` [PATCH 49/85] target/sparc: Split out fp ldst functions with asi precomputed Richard Henderson
2023-10-13 21:28 ` [PATCH 50/85] target/sparc: Move simple fp load/store to decodetree Richard Henderson
2023-10-13 21:28 ` [PATCH 51/85] target/sparc: Move asi " Richard Henderson
2023-10-13 21:28 ` [PATCH 52/85] target/sparc: Move LDFSR, STFSR " Richard Henderson
2023-10-13 21:28 ` [PATCH 53/85] target/sparc: Merge LDFSR, LDXFSR implementations Richard Henderson
2023-10-13 21:28 ` [PATCH 54/85] target/sparc: Move EDGE* to decodetree Richard Henderson
2023-10-13 21:28 ` [PATCH 55/85] target/sparc: Move ARRAY* " Richard Henderson
2023-10-13 21:28 ` [PATCH 56/85] target/sparc: Move ADDRALIGN* " Richard Henderson
2023-10-13 21:28 ` [PATCH 57/85] target/sparc: Move BMASK " Richard Henderson
2023-10-13 21:28 ` [PATCH 58/85] target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S " Richard Henderson
2023-10-13 21:28 ` [PATCH 59/85] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D " Richard Henderson
2023-10-13 21:28 ` [PATCH 60/85] target/sparc: Use tcg_gen_vec_{add,sub}* Richard Henderson
2023-10-13 21:28 ` [PATCH 61/85] target/sparc: Move gen_ne_fop_FFF insns to decodetree Richard Henderson
2023-10-13 21:28 ` [PATCH 62/85] target/sparc: Move gen_ne_fop_DDD " Richard Henderson
2023-10-13 21:28 ` [PATCH 63/85] target/sparc: Move PDIST " Richard Henderson
2023-10-13 21:28 ` [PATCH 64/85] target/sparc: Move gen_gsr_fop_DDD insns " Richard Henderson
2023-10-13 21:28 ` [PATCH 65/85] target/sparc: Move gen_fop_FF " Richard Henderson
2023-10-13 21:28 ` [PATCH 66/85] target/sparc: Move gen_fop_DD " Richard Henderson
2023-10-13 21:28 ` [PATCH 67/85] target/sparc: Move FSQRTq " Richard Henderson
2023-10-13 21:28 ` [PATCH 68/85] target/sparc: Move gen_fop_FFF insns " Richard Henderson
2023-10-13 21:28 ` [PATCH 69/85] target/sparc: Move gen_fop_DDD " Richard Henderson
2023-10-13 21:28 ` [PATCH 70/85] target/sparc: Move gen_fop_QQQ " Richard Henderson
2023-10-13 21:28 ` [PATCH 71/85] target/sparc: Move FSMULD " Richard Henderson
2023-10-13 21:28 ` [PATCH 72/85] target/sparc: Move FDMULQ " Richard Henderson
2023-10-13 21:28 ` [PATCH 73/85] target/sparc: Move gen_fop_FD insns " Richard Henderson
2023-10-13 21:28 ` [PATCH 74/85] target/sparc: Move FiTOd, FsTOd, FsTOx " Richard Henderson
2023-10-13 21:28 ` [PATCH 75/85] target/sparc: Move FqTOs, FqTOi " Richard Henderson
2023-10-13 21:28 ` [PATCH 76/85] target/sparc: Move FqTOd, FqTOx " Richard Henderson
2023-10-13 21:28 ` [PATCH 77/85] target/sparc: Move FiTOq, FsTOq " Richard Henderson
2023-10-13 21:28 ` [PATCH 78/85] target/sparc: Move FdTOq, FxTOq " Richard Henderson
2023-10-13 21:28 ` [PATCH 79/85] target/sparc: Move FMOVq, FNEGq, FABSq " Richard Henderson
2023-10-13 21:28 ` [PATCH 80/85] target/sparc: Move FMOVR, FMOVcc, FMOVfcc " Richard Henderson
2023-10-13 21:28 ` [PATCH 81/85] target/sparc: Convert FCMP, FCMPE " Richard Henderson
2023-10-13 21:28 ` [PATCH 82/85] target/sparc: Move FPCMP* " Richard Henderson
2023-10-13 21:28 ` [PATCH 83/85] target/sparc: Move FPACK16, FPACKFIX " Richard Henderson
2023-10-13 21:28 ` [PATCH 84/85] target/sparc: Convert FZERO, FONE " Richard Henderson
2023-10-13 21:28 ` [PATCH 85/85] target/sparc: Remove disas_sparc_legacy Richard Henderson
2023-10-14 6:32 ` [PATCH 00/85] target/sparc: Convert to decodetree Mark Cave-Ayland
2023-10-15 20:12 ` Mark Cave-Ayland
2023-10-15 22:38 ` Richard Henderson
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