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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com
Subject: [PATCH 60/85] target/sparc: Use tcg_gen_vec_{add,sub}*
Date: Fri, 13 Oct 2023 14:28:21 -0700	[thread overview]
Message-ID: <20231013212846.165724-61-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org>

Replace the local helpers for the same integer operations.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/helper.h     | 12 --------
 target/sparc/translate.c  | 15 +++++-----
 target/sparc/vis_helper.c | 59 ---------------------------------------
 3 files changed, 7 insertions(+), 79 deletions(-)

diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index a9ee8e6b9f..8d20258d08 100644
--- a/target/sparc/helper.h
+++ b/target/sparc/helper.h
@@ -138,18 +138,6 @@ DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i64, i64)
 DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
 DEF_HELPER_FLAGS_2(fpackfix, TCG_CALL_NO_RWG_SE, i32, i64, i64)
 DEF_HELPER_FLAGS_3(bshuffle, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
-#define VIS_HELPER(name)                                                 \
-    DEF_HELPER_FLAGS_2(f ## name ## 16, TCG_CALL_NO_RWG_SE,  \
-                       i64, i64, i64)                                    \
-    DEF_HELPER_FLAGS_2(f ## name ## 16s, TCG_CALL_NO_RWG_SE, \
-                       i32, i32, i32)                                    \
-    DEF_HELPER_FLAGS_2(f ## name ## 32, TCG_CALL_NO_RWG_SE,  \
-                       i64, i64, i64)                                    \
-    DEF_HELPER_FLAGS_2(f ## name ## 32s, TCG_CALL_NO_RWG_SE, \
-                       i32, i32, i32)
-
-VIS_HELPER(padd)
-VIS_HELPER(psub)
 #define VIS_CMPHELPER(name)                                              \
     DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE,      \
                        i64, i64, i64)                                    \
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 0a1ebb62e3..3b6f4bef95 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -25,9 +25,8 @@
 #include "exec/helper-proto.h"
 #include "exec/exec-all.h"
 #include "tcg/tcg-op.h"
-
+#include "tcg/tcg-op-gvec.h"
 #include "exec/helper-gen.h"
-
 #include "exec/translator.h"
 #include "exec/log.h"
 #include "asi.h"
@@ -5337,15 +5336,15 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
                     break;
                 case 0x050: /* VIS I fpadd16 */
                     CHECK_FPU_FEATURE(dc, VIS1);
-                    gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16);
+                    gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add16_i64);
                     break;
                 case 0x051: /* VIS I fpadd16s */
                     CHECK_FPU_FEATURE(dc, VIS1);
-                    gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s);
+                    gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_vec_add16_i32);
                     break;
                 case 0x052: /* VIS I fpadd32 */
                     CHECK_FPU_FEATURE(dc, VIS1);
-                    gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32);
+                    gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64);
                     break;
                 case 0x053: /* VIS I fpadd32s */
                     CHECK_FPU_FEATURE(dc, VIS1);
@@ -5353,15 +5352,15 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
                     break;
                 case 0x054: /* VIS I fpsub16 */
                     CHECK_FPU_FEATURE(dc, VIS1);
-                    gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16);
+                    gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i64);
                     break;
                 case 0x055: /* VIS I fpsub16s */
                     CHECK_FPU_FEATURE(dc, VIS1);
-                    gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s);
+                    gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i32);
                     break;
                 case 0x056: /* VIS I fpsub32 */
                     CHECK_FPU_FEATURE(dc, VIS1);
-                    gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32);
+                    gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64);
                     break;
                 case 0x057: /* VIS I fpsub32s */
                     CHECK_FPU_FEATURE(dc, VIS1);
diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c
index 3afdc6975c..7763b16c24 100644
--- a/target/sparc/vis_helper.c
+++ b/target/sparc/vis_helper.c
@@ -275,65 +275,6 @@ uint64_t helper_fexpand(uint64_t src1, uint64_t src2)
     return d.ll;
 }
 
-#define VIS_HELPER(name, F)                             \
-    uint64_t name##16(uint64_t src1, uint64_t src2)     \
-    {                                                   \
-        VIS64 s, d;                                     \
-                                                        \
-        s.ll = src1;                                    \
-        d.ll = src2;                                    \
-                                                        \
-        d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0));   \
-        d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1));   \
-        d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2));   \
-        d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3));   \
-                                                        \
-        return d.ll;                                    \
-    }                                                   \
-                                                        \
-    uint32_t name##16s(uint32_t src1, uint32_t src2)    \
-    {                                                   \
-        VIS32 s, d;                                     \
-                                                        \
-        s.l = src1;                                     \
-        d.l = src2;                                     \
-                                                        \
-        d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0));   \
-        d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1));   \
-                                                        \
-        return d.l;                                     \
-    }                                                   \
-                                                        \
-    uint64_t name##32(uint64_t src1, uint64_t src2)     \
-    {                                                   \
-        VIS64 s, d;                                     \
-                                                        \
-        s.ll = src1;                                    \
-        d.ll = src2;                                    \
-                                                        \
-        d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0));   \
-        d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1));   \
-                                                        \
-        return d.ll;                                    \
-    }                                                   \
-                                                        \
-    uint32_t name##32s(uint32_t src1, uint32_t src2)    \
-    {                                                   \
-        VIS32 s, d;                                     \
-                                                        \
-        s.l = src1;                                     \
-        d.l = src2;                                     \
-                                                        \
-        d.l = F(d.l, s.l);                              \
-                                                        \
-        return d.l;                                     \
-    }
-
-#define FADD(a, b) ((a) + (b))
-#define FSUB(a, b) ((a) - (b))
-VIS_HELPER(helper_fpadd, FADD)
-VIS_HELPER(helper_fpsub, FSUB)
-
 #define VIS_CMPHELPER(name, F)                                    \
     uint64_t name##16(uint64_t src1, uint64_t src2)               \
     {                                                             \
-- 
2.34.1



  parent reply	other threads:[~2023-10-13 21:38 UTC|newest]

Thread overview: 95+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-13 21:27 [PATCH 00/85] target/sparc: Convert to decodetree Richard Henderson
2023-10-13 21:27 ` [PATCH 01/85] target/sparc: Set TCG_GUEST_DEFAULT_MO Richard Henderson
2023-10-16  6:46   ` Philippe Mathieu-Daudé
2023-10-13 21:27 ` [PATCH 02/85] configs: Enable MTTCG for sparc, sparc64 Richard Henderson
2023-10-13 21:27 ` [PATCH 03/85] target/sparc: Remove always-set cpu features Richard Henderson
2023-10-15 16:53   ` Richard Henderson
2023-10-13 21:27 ` [PATCH 04/85] target/sparc: Add decodetree infrastructure Richard Henderson
2023-10-13 21:27 ` [PATCH 05/85] target/sparc: Define AM_CHECK for sparc32 Richard Henderson
2023-10-13 21:27 ` [PATCH 06/85] target/sparc: Move CALL to decodetree Richard Henderson
2023-10-13 21:27 ` [PATCH 07/85] target/sparc: Move BPcc and Bicc " Richard Henderson
2023-10-13 21:27 ` [PATCH 08/85] target/sparc: Move BPr " Richard Henderson
2023-10-13 21:27 ` [PATCH 09/85] target/sparc: Move FBPfcc and FBfcc " Richard Henderson
2025-01-26  9:38   ` Artyom Tarasenko
2025-01-26 12:25     ` Richard Henderson
2023-10-13 21:27 ` [PATCH 10/85] target/sparc: Merge gen_cond with only caller Richard Henderson
2023-10-16  6:52   ` Philippe Mathieu-Daudé
2023-10-13 21:27 ` [PATCH 11/85] target/sparc: Merge gen_fcond " Richard Henderson
2023-10-16  6:52   ` Philippe Mathieu-Daudé
2023-10-13 21:27 ` [PATCH 12/85] target/sparc: Merge gen_branch_[an] " Richard Henderson
2023-10-13 21:27 ` [PATCH 13/85] target/sparc: Pass DisasCompare to advance_jump_cond Richard Henderson
2023-10-13 21:27 ` [PATCH 14/85] target/sparc: Move SETHI to decodetree Richard Henderson
2023-10-13 21:27 ` [PATCH 15/85] target/sparc: Move Tcc " Richard Henderson
2023-10-13 21:27 ` [PATCH 16/85] target/sparc: Move RDASR, STBAR, MEMBAR " Richard Henderson
2023-10-13 21:27 ` [PATCH 17/85] target/sparc: Move RDPSR, RDHPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 18/85] target/sparc: Move RDWIM, RDPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 19/85] target/sparc: Move RDTBR, FLUSHW " Richard Henderson
2023-10-13 21:27 ` [PATCH 20/85] target/sparc: Move WRASR " Richard Henderson
2023-10-13 21:27 ` [PATCH 21/85] target/sparc: Move WRPSR, SAVED, RESTORED " Richard Henderson
2023-10-13 21:27 ` [PATCH 22/85] target/sparc: Move WRWIM, WRPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 23/85] target/sparc: Move WRTBR, WRHPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 24/85] target/sparc: Move basic arithmetic " Richard Henderson
2023-10-13 21:27 ` [PATCH 25/85] target/sparc: Move ADDC " Richard Henderson
2023-10-13 21:27 ` [PATCH 26/85] target/sparc: Move MULX " Richard Henderson
2023-10-13 21:27 ` [PATCH 27/85] target/sparc: Move UMUL, SMUL " Richard Henderson
2023-10-13 21:27 ` [PATCH 28/85] target/sparc: Move SUBC " Richard Henderson
2023-10-13 21:27 ` [PATCH 29/85] target/sparc: Move UDIVX, SDIVX " Richard Henderson
2023-10-13 21:27 ` [PATCH 30/85] target/sparc: Move UDIV, SDIV " Richard Henderson
2023-10-13 21:27 ` [PATCH 31/85] target/sparc: Move TADD, TSUB, MULS " Richard Henderson
2023-10-13 21:27 ` [PATCH 32/85] target/sparc: Move SLL, SRL, SRA " Richard Henderson
2023-10-13 21:27 ` [PATCH 33/85] target/sparc: Move MOVcc, MOVR " Richard Henderson
2023-10-13 21:27 ` [PATCH 34/85] target/sparc: Move POPC " Richard Henderson
2023-10-13 21:27 ` [PATCH 35/85] target/sparc: Convert remaining v8 coproc insns " Richard Henderson
2023-10-13 21:27 ` [PATCH 36/85] target/sparc: Move JMPL, RETT, RETURN " Richard Henderson
2023-10-13 21:27 ` [PATCH 37/85] target/sparc: Move FLUSH, SAVE, RESTORE " Richard Henderson
2023-10-13 21:27 ` [PATCH 38/85] target/sparc: Move DONE, RETRY " Richard Henderson
2023-10-13 21:28 ` [PATCH 39/85] target/sparc: Split out resolve_asi Richard Henderson
2023-10-13 21:28 ` [PATCH 40/85] target/sparc: Drop ifdef around get_asi and friends Richard Henderson
2023-10-13 21:28 ` [PATCH 41/85] target/sparc: Split out ldst functions with asi pre-computed Richard Henderson
2023-10-13 21:28 ` [PATCH 42/85] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX Richard Henderson
2023-10-13 21:28 ` [PATCH 43/85] target/sparc: Move simple integer load/store to decodetree Richard Henderson
2023-10-13 21:28 ` [PATCH 44/85] target/sparc: Move asi " Richard Henderson
2023-10-13 21:28 ` [PATCH 45/85] target/sparc: Move LDSTUB, LDSTUBA " Richard Henderson
2023-10-13 21:28 ` [PATCH 46/85] target/sparc: Move SWAP, SWAPA " Richard Henderson
2023-10-13 21:28 ` [PATCH 47/85] target/sparc: Move CASA, CASXA " Richard Henderson
2023-10-13 21:28 ` [PATCH 48/85] target/sparc: Move PREFETCH, PREFETCHA " Richard Henderson
2023-10-13 21:28 ` [PATCH 49/85] target/sparc: Split out fp ldst functions with asi precomputed Richard Henderson
2023-10-13 21:28 ` [PATCH 50/85] target/sparc: Move simple fp load/store to decodetree Richard Henderson
2023-10-13 21:28 ` [PATCH 51/85] target/sparc: Move asi " Richard Henderson
2023-10-13 21:28 ` [PATCH 52/85] target/sparc: Move LDFSR, STFSR " Richard Henderson
2023-10-13 21:28 ` [PATCH 53/85] target/sparc: Merge LDFSR, LDXFSR implementations Richard Henderson
2023-10-13 21:28 ` [PATCH 54/85] target/sparc: Move EDGE* to decodetree Richard Henderson
2023-10-13 21:28 ` [PATCH 55/85] target/sparc: Move ARRAY* " Richard Henderson
2023-10-13 21:28 ` [PATCH 56/85] target/sparc: Move ADDRALIGN* " Richard Henderson
2023-10-13 21:28 ` [PATCH 57/85] target/sparc: Move BMASK " Richard Henderson
2023-10-13 21:28 ` [PATCH 58/85] target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S " Richard Henderson
2023-10-13 21:28 ` [PATCH 59/85] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D " Richard Henderson
2023-10-13 21:28 ` Richard Henderson [this message]
2023-10-13 21:28 ` [PATCH 61/85] target/sparc: Move gen_ne_fop_FFF insns " Richard Henderson
2023-10-13 21:28 ` [PATCH 62/85] target/sparc: Move gen_ne_fop_DDD " Richard Henderson
2023-10-13 21:28 ` [PATCH 63/85] target/sparc: Move PDIST " Richard Henderson
2023-10-13 21:28 ` [PATCH 64/85] target/sparc: Move gen_gsr_fop_DDD insns " Richard Henderson
2023-10-13 21:28 ` [PATCH 65/85] target/sparc: Move gen_fop_FF " Richard Henderson
2023-10-13 21:28 ` [PATCH 66/85] target/sparc: Move gen_fop_DD " Richard Henderson
2023-10-13 21:28 ` [PATCH 67/85] target/sparc: Move FSQRTq " Richard Henderson
2023-10-13 21:28 ` [PATCH 68/85] target/sparc: Move gen_fop_FFF insns " Richard Henderson
2023-10-13 21:28 ` [PATCH 69/85] target/sparc: Move gen_fop_DDD " Richard Henderson
2023-10-13 21:28 ` [PATCH 70/85] target/sparc: Move gen_fop_QQQ " Richard Henderson
2023-10-13 21:28 ` [PATCH 71/85] target/sparc: Move FSMULD " Richard Henderson
2023-10-13 21:28 ` [PATCH 72/85] target/sparc: Move FDMULQ " Richard Henderson
2023-10-13 21:28 ` [PATCH 73/85] target/sparc: Move gen_fop_FD insns " Richard Henderson
2023-10-13 21:28 ` [PATCH 74/85] target/sparc: Move FiTOd, FsTOd, FsTOx " Richard Henderson
2023-10-13 21:28 ` [PATCH 75/85] target/sparc: Move FqTOs, FqTOi " Richard Henderson
2023-10-13 21:28 ` [PATCH 76/85] target/sparc: Move FqTOd, FqTOx " Richard Henderson
2023-10-13 21:28 ` [PATCH 77/85] target/sparc: Move FiTOq, FsTOq " Richard Henderson
2023-10-13 21:28 ` [PATCH 78/85] target/sparc: Move FdTOq, FxTOq " Richard Henderson
2023-10-13 21:28 ` [PATCH 79/85] target/sparc: Move FMOVq, FNEGq, FABSq " Richard Henderson
2023-10-13 21:28 ` [PATCH 80/85] target/sparc: Move FMOVR, FMOVcc, FMOVfcc " Richard Henderson
2023-10-13 21:28 ` [PATCH 81/85] target/sparc: Convert FCMP, FCMPE " Richard Henderson
2023-10-13 21:28 ` [PATCH 82/85] target/sparc: Move FPCMP* " Richard Henderson
2023-10-13 21:28 ` [PATCH 83/85] target/sparc: Move FPACK16, FPACKFIX " Richard Henderson
2023-10-13 21:28 ` [PATCH 84/85] target/sparc: Convert FZERO, FONE " Richard Henderson
2023-10-13 21:28 ` [PATCH 85/85] target/sparc: Remove disas_sparc_legacy Richard Henderson
2023-10-14  6:32 ` [PATCH 00/85] target/sparc: Convert to decodetree Mark Cave-Ayland
2023-10-15 20:12 ` Mark Cave-Ayland
2023-10-15 22:38   ` Richard Henderson

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