From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com
Subject: [PATCH 81/85] target/sparc: Convert FCMP, FCMPE to decodetree
Date: Fri, 13 Oct 2023 14:28:42 -0700 [thread overview]
Message-ID: <20231013212846.165724-82-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 7 ++
target/sparc/translate.c | 145 +++++++++++++++++++++++---------------
2 files changed, 96 insertions(+), 56 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 5e8d456ab2..c5d6f46737 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -290,6 +290,13 @@ FMOVRs 10 rd:5 110101 rs1:5 0 cond:3 00101 rs2:5
FMOVRd 10 rd:5 110101 rs1:5 0 cond:3 00110 rs2:5
FMOVRq 10 rd:5 110101 rs1:5 0 cond:3 00111 rs2:5
+FCMPs 10 000 cc:2 110101 rs1:5 0 0101 0001 rs2:5
+FCMPd 10 000 cc:2 110101 rs1:5 0 0101 0010 rs2:5
+FCMPq 10 000 cc:2 110101 rs1:5 0 0101 0011 rs2:5
+FCMPEs 10 000 cc:2 110101 rs1:5 0 0101 0101 rs2:5
+FCMPEd 10 000 cc:2 110101 rs1:5 0 0101 0110 rs2:5
+FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5
+
{
[
EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 2ecaa82de5..81d274448a 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5105,6 +5105,82 @@ TRANS(FMOVsfcc, 64, do_fmovfcc, a, false, gen_fmovs)
TRANS(FMOVdfcc, 64, do_fmovfcc, a, false, gen_fmovd)
TRANS(FMOVqfcc, 64, do_fmovfcc, a, true, gen_fmovq)
+static bool do_fcmps(DisasContext *dc, arg_FCMPs *a, bool e)
+{
+ TCGv_i32 src1, src2;
+
+ if (avail_32(dc) && a->cc != 0) {
+ return false;
+ }
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+
+ gen_op_clear_ieee_excp_and_FTT();
+ src1 = gen_load_fpr_F(dc, a->rs1);
+ src2 = gen_load_fpr_F(dc, a->rs2);
+ if (e) {
+ gen_op_fcmpes(a->cc, src1, src2);
+ } else {
+ gen_op_fcmps(a->cc, src1, src2);
+ }
+ return advance_pc(dc);
+}
+
+TRANS(FCMPs, ALL, do_fcmps, a, false)
+TRANS(FCMPEs, ALL, do_fcmps, a, true)
+
+static bool do_fcmpd(DisasContext *dc, arg_FCMPq *a, bool e)
+{
+ TCGv_i64 src1, src2;
+
+ if (avail_32(dc) && a->cc != 0) {
+ return false;
+ }
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+
+ gen_op_clear_ieee_excp_and_FTT();
+ src1 = gen_load_fpr_D(dc, a->rs1);
+ src2 = gen_load_fpr_D(dc, a->rs2);
+ if (e) {
+ gen_op_fcmped(a->cc, src1, src2);
+ } else {
+ gen_op_fcmpd(a->cc, src1, src2);
+ }
+ return advance_pc(dc);
+}
+
+TRANS(FCMPd, ALL, do_fcmpd, a, false)
+TRANS(FCMPEd, ALL, do_fcmpd, a, true)
+
+static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, bool e)
+{
+ if (avail_32(dc) && a->cc != 0) {
+ return false;
+ }
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+ if (gen_trap_float128(dc)) {
+ return true;
+ }
+
+ gen_op_clear_ieee_excp_and_FTT();
+ gen_op_load_fpr_QT0(QFPREG(a->rs1));
+ gen_op_load_fpr_QT1(QFPREG(a->rs2));
+ if (e) {
+ gen_op_fcmpeq(a->cc);
+ } else {
+ gen_op_fcmpq(a->cc);
+ }
+ return advance_pc(dc);
+}
+
+TRANS(FCMPq, ALL, do_fcmpq, a, false)
+TRANS(FCMPEq, ALL, do_fcmpq, a, true)
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -5115,15 +5191,7 @@ TRANS(FMOVqfcc, 64, do_fmovfcc, a, true, gen_fmovq)
/* before an instruction, dc->pc must be static */
static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
{
- unsigned int opc, rs1, rs2, rd;
- TCGv cpu_src1 __attribute__((unused));
- TCGv_i32 cpu_src1_32, cpu_src2_32;
- TCGv_i64 cpu_src1_64, cpu_src2_64;
- TCGv_i32 cpu_dst_32 __attribute__((unused));
- TCGv_i64 cpu_dst_64 __attribute__((unused));
-
- opc = GET_FIELD(insn, 0, 1);
- rd = GET_FIELD(insn, 2, 6);
+ unsigned int opc = GET_FIELD(insn, 0, 1);
switch (opc) {
case 0:
@@ -5133,61 +5201,22 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 2: /* FPU & Logical Operations */
{
unsigned int xop = GET_FIELD(insn, 7, 12);
- TCGv cpu_dst __attribute__((unused)) = tcg_temp_new();
if (xop == 0x34) { /* FPU Operations */
goto illegal_insn; /* in decodetree */
} else if (xop == 0x35) { /* FPU Operations */
- if (gen_trap_ifnofpu(dc)) {
- goto jmp_insn;
- }
- gen_op_clear_ieee_excp_and_FTT();
- rs1 = GET_FIELD(insn, 13, 17);
- rs2 = GET_FIELD(insn, 27, 31);
- xop = GET_FIELD(insn, 18, 26);
-
- switch (xop) {
- case 0x51: /* fcmps, V9 %fcc */
- cpu_src1_32 = gen_load_fpr_F(dc, rs1);
- cpu_src2_32 = gen_load_fpr_F(dc, rs2);
- gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32);
- break;
- case 0x52: /* fcmpd, V9 %fcc */
- cpu_src1_64 = gen_load_fpr_D(dc, rs1);
- cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64);
- break;
- case 0x53: /* fcmpq, V9 %fcc */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_QT0(QFPREG(rs1));
- gen_op_load_fpr_QT1(QFPREG(rs2));
- gen_op_fcmpq(rd & 3);
- break;
- case 0x55: /* fcmpes, V9 %fcc */
- cpu_src1_32 = gen_load_fpr_F(dc, rs1);
- cpu_src2_32 = gen_load_fpr_F(dc, rs2);
- gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32);
- break;
- case 0x56: /* fcmped, V9 %fcc */
- cpu_src1_64 = gen_load_fpr_D(dc, rs1);
- cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64);
- break;
- case 0x57: /* fcmpeq, V9 %fcc */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_op_load_fpr_QT0(QFPREG(rs1));
- gen_op_load_fpr_QT1(QFPREG(rs2));
- gen_op_fcmpeq(rd & 3);
- break;
- default:
- goto illegal_insn;
- }
+ goto illegal_insn; /* in decodetree */
} else if (xop == 0x36) {
#ifdef TARGET_SPARC64
/* VIS */
+ TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
+ TCGv_i32 cpu_dst_32;
+ TCGv cpu_dst = tcg_temp_new();
int opf = GET_FIELD_SP(insn, 5, 13);
- rs1 = GET_FIELD(insn, 13, 17);
- rs2 = GET_FIELD(insn, 27, 31);
+ int rs1 = GET_FIELD(insn, 13, 17);
+ int rs2 = GET_FIELD(insn, 27, 31);
+ int rd = GET_FIELD(insn, 2, 6);
+
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
@@ -5372,14 +5401,18 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
goto illegal_insn; /* in decodetree */
}
advance_pc(dc);
+#ifdef TARGET_SPARC64
jmp_insn:
+#endif
return;
illegal_insn:
gen_exception(dc, TT_ILL_INSN);
return;
+#ifdef TARGET_SPARC64
nfpu_insn:
gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP);
return;
+#endif
}
static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
--
2.34.1
next prev parent reply other threads:[~2023-10-13 21:36 UTC|newest]
Thread overview: 95+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-13 21:27 [PATCH 00/85] target/sparc: Convert to decodetree Richard Henderson
2023-10-13 21:27 ` [PATCH 01/85] target/sparc: Set TCG_GUEST_DEFAULT_MO Richard Henderson
2023-10-16 6:46 ` Philippe Mathieu-Daudé
2023-10-13 21:27 ` [PATCH 02/85] configs: Enable MTTCG for sparc, sparc64 Richard Henderson
2023-10-13 21:27 ` [PATCH 03/85] target/sparc: Remove always-set cpu features Richard Henderson
2023-10-15 16:53 ` Richard Henderson
2023-10-13 21:27 ` [PATCH 04/85] target/sparc: Add decodetree infrastructure Richard Henderson
2023-10-13 21:27 ` [PATCH 05/85] target/sparc: Define AM_CHECK for sparc32 Richard Henderson
2023-10-13 21:27 ` [PATCH 06/85] target/sparc: Move CALL to decodetree Richard Henderson
2023-10-13 21:27 ` [PATCH 07/85] target/sparc: Move BPcc and Bicc " Richard Henderson
2023-10-13 21:27 ` [PATCH 08/85] target/sparc: Move BPr " Richard Henderson
2023-10-13 21:27 ` [PATCH 09/85] target/sparc: Move FBPfcc and FBfcc " Richard Henderson
2025-01-26 9:38 ` Artyom Tarasenko
2025-01-26 12:25 ` Richard Henderson
2023-10-13 21:27 ` [PATCH 10/85] target/sparc: Merge gen_cond with only caller Richard Henderson
2023-10-16 6:52 ` Philippe Mathieu-Daudé
2023-10-13 21:27 ` [PATCH 11/85] target/sparc: Merge gen_fcond " Richard Henderson
2023-10-16 6:52 ` Philippe Mathieu-Daudé
2023-10-13 21:27 ` [PATCH 12/85] target/sparc: Merge gen_branch_[an] " Richard Henderson
2023-10-13 21:27 ` [PATCH 13/85] target/sparc: Pass DisasCompare to advance_jump_cond Richard Henderson
2023-10-13 21:27 ` [PATCH 14/85] target/sparc: Move SETHI to decodetree Richard Henderson
2023-10-13 21:27 ` [PATCH 15/85] target/sparc: Move Tcc " Richard Henderson
2023-10-13 21:27 ` [PATCH 16/85] target/sparc: Move RDASR, STBAR, MEMBAR " Richard Henderson
2023-10-13 21:27 ` [PATCH 17/85] target/sparc: Move RDPSR, RDHPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 18/85] target/sparc: Move RDWIM, RDPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 19/85] target/sparc: Move RDTBR, FLUSHW " Richard Henderson
2023-10-13 21:27 ` [PATCH 20/85] target/sparc: Move WRASR " Richard Henderson
2023-10-13 21:27 ` [PATCH 21/85] target/sparc: Move WRPSR, SAVED, RESTORED " Richard Henderson
2023-10-13 21:27 ` [PATCH 22/85] target/sparc: Move WRWIM, WRPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 23/85] target/sparc: Move WRTBR, WRHPR " Richard Henderson
2023-10-13 21:27 ` [PATCH 24/85] target/sparc: Move basic arithmetic " Richard Henderson
2023-10-13 21:27 ` [PATCH 25/85] target/sparc: Move ADDC " Richard Henderson
2023-10-13 21:27 ` [PATCH 26/85] target/sparc: Move MULX " Richard Henderson
2023-10-13 21:27 ` [PATCH 27/85] target/sparc: Move UMUL, SMUL " Richard Henderson
2023-10-13 21:27 ` [PATCH 28/85] target/sparc: Move SUBC " Richard Henderson
2023-10-13 21:27 ` [PATCH 29/85] target/sparc: Move UDIVX, SDIVX " Richard Henderson
2023-10-13 21:27 ` [PATCH 30/85] target/sparc: Move UDIV, SDIV " Richard Henderson
2023-10-13 21:27 ` [PATCH 31/85] target/sparc: Move TADD, TSUB, MULS " Richard Henderson
2023-10-13 21:27 ` [PATCH 32/85] target/sparc: Move SLL, SRL, SRA " Richard Henderson
2023-10-13 21:27 ` [PATCH 33/85] target/sparc: Move MOVcc, MOVR " Richard Henderson
2023-10-13 21:27 ` [PATCH 34/85] target/sparc: Move POPC " Richard Henderson
2023-10-13 21:27 ` [PATCH 35/85] target/sparc: Convert remaining v8 coproc insns " Richard Henderson
2023-10-13 21:27 ` [PATCH 36/85] target/sparc: Move JMPL, RETT, RETURN " Richard Henderson
2023-10-13 21:27 ` [PATCH 37/85] target/sparc: Move FLUSH, SAVE, RESTORE " Richard Henderson
2023-10-13 21:27 ` [PATCH 38/85] target/sparc: Move DONE, RETRY " Richard Henderson
2023-10-13 21:28 ` [PATCH 39/85] target/sparc: Split out resolve_asi Richard Henderson
2023-10-13 21:28 ` [PATCH 40/85] target/sparc: Drop ifdef around get_asi and friends Richard Henderson
2023-10-13 21:28 ` [PATCH 41/85] target/sparc: Split out ldst functions with asi pre-computed Richard Henderson
2023-10-13 21:28 ` [PATCH 42/85] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX Richard Henderson
2023-10-13 21:28 ` [PATCH 43/85] target/sparc: Move simple integer load/store to decodetree Richard Henderson
2023-10-13 21:28 ` [PATCH 44/85] target/sparc: Move asi " Richard Henderson
2023-10-13 21:28 ` [PATCH 45/85] target/sparc: Move LDSTUB, LDSTUBA " Richard Henderson
2023-10-13 21:28 ` [PATCH 46/85] target/sparc: Move SWAP, SWAPA " Richard Henderson
2023-10-13 21:28 ` [PATCH 47/85] target/sparc: Move CASA, CASXA " Richard Henderson
2023-10-13 21:28 ` [PATCH 48/85] target/sparc: Move PREFETCH, PREFETCHA " Richard Henderson
2023-10-13 21:28 ` [PATCH 49/85] target/sparc: Split out fp ldst functions with asi precomputed Richard Henderson
2023-10-13 21:28 ` [PATCH 50/85] target/sparc: Move simple fp load/store to decodetree Richard Henderson
2023-10-13 21:28 ` [PATCH 51/85] target/sparc: Move asi " Richard Henderson
2023-10-13 21:28 ` [PATCH 52/85] target/sparc: Move LDFSR, STFSR " Richard Henderson
2023-10-13 21:28 ` [PATCH 53/85] target/sparc: Merge LDFSR, LDXFSR implementations Richard Henderson
2023-10-13 21:28 ` [PATCH 54/85] target/sparc: Move EDGE* to decodetree Richard Henderson
2023-10-13 21:28 ` [PATCH 55/85] target/sparc: Move ARRAY* " Richard Henderson
2023-10-13 21:28 ` [PATCH 56/85] target/sparc: Move ADDRALIGN* " Richard Henderson
2023-10-13 21:28 ` [PATCH 57/85] target/sparc: Move BMASK " Richard Henderson
2023-10-13 21:28 ` [PATCH 58/85] target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S " Richard Henderson
2023-10-13 21:28 ` [PATCH 59/85] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D " Richard Henderson
2023-10-13 21:28 ` [PATCH 60/85] target/sparc: Use tcg_gen_vec_{add,sub}* Richard Henderson
2023-10-13 21:28 ` [PATCH 61/85] target/sparc: Move gen_ne_fop_FFF insns to decodetree Richard Henderson
2023-10-13 21:28 ` [PATCH 62/85] target/sparc: Move gen_ne_fop_DDD " Richard Henderson
2023-10-13 21:28 ` [PATCH 63/85] target/sparc: Move PDIST " Richard Henderson
2023-10-13 21:28 ` [PATCH 64/85] target/sparc: Move gen_gsr_fop_DDD insns " Richard Henderson
2023-10-13 21:28 ` [PATCH 65/85] target/sparc: Move gen_fop_FF " Richard Henderson
2023-10-13 21:28 ` [PATCH 66/85] target/sparc: Move gen_fop_DD " Richard Henderson
2023-10-13 21:28 ` [PATCH 67/85] target/sparc: Move FSQRTq " Richard Henderson
2023-10-13 21:28 ` [PATCH 68/85] target/sparc: Move gen_fop_FFF insns " Richard Henderson
2023-10-13 21:28 ` [PATCH 69/85] target/sparc: Move gen_fop_DDD " Richard Henderson
2023-10-13 21:28 ` [PATCH 70/85] target/sparc: Move gen_fop_QQQ " Richard Henderson
2023-10-13 21:28 ` [PATCH 71/85] target/sparc: Move FSMULD " Richard Henderson
2023-10-13 21:28 ` [PATCH 72/85] target/sparc: Move FDMULQ " Richard Henderson
2023-10-13 21:28 ` [PATCH 73/85] target/sparc: Move gen_fop_FD insns " Richard Henderson
2023-10-13 21:28 ` [PATCH 74/85] target/sparc: Move FiTOd, FsTOd, FsTOx " Richard Henderson
2023-10-13 21:28 ` [PATCH 75/85] target/sparc: Move FqTOs, FqTOi " Richard Henderson
2023-10-13 21:28 ` [PATCH 76/85] target/sparc: Move FqTOd, FqTOx " Richard Henderson
2023-10-13 21:28 ` [PATCH 77/85] target/sparc: Move FiTOq, FsTOq " Richard Henderson
2023-10-13 21:28 ` [PATCH 78/85] target/sparc: Move FdTOq, FxTOq " Richard Henderson
2023-10-13 21:28 ` [PATCH 79/85] target/sparc: Move FMOVq, FNEGq, FABSq " Richard Henderson
2023-10-13 21:28 ` [PATCH 80/85] target/sparc: Move FMOVR, FMOVcc, FMOVfcc " Richard Henderson
2023-10-13 21:28 ` Richard Henderson [this message]
2023-10-13 21:28 ` [PATCH 82/85] target/sparc: Move FPCMP* " Richard Henderson
2023-10-13 21:28 ` [PATCH 83/85] target/sparc: Move FPACK16, FPACKFIX " Richard Henderson
2023-10-13 21:28 ` [PATCH 84/85] target/sparc: Convert FZERO, FONE " Richard Henderson
2023-10-13 21:28 ` [PATCH 85/85] target/sparc: Remove disas_sparc_legacy Richard Henderson
2023-10-14 6:32 ` [PATCH 00/85] target/sparc: Convert to decodetree Mark Cave-Ayland
2023-10-15 20:12 ` Mark Cave-Ayland
2023-10-15 22:38 ` Richard Henderson
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