From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk
Subject: [PATCH 11/20] target/sparc: Always copy conditions into a new temporary
Date: Mon, 16 Oct 2023 23:41:00 -0700 [thread overview]
Message-ID: <20231017064109.681935-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231017064109.681935-1-richard.henderson@linaro.org>
This will allow the condition to live across changes to
the global cc variables.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 20 +++++++-------------
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 32d29f16b5..a75f75dfb9 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -977,7 +977,7 @@ static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
{
TCGv t1, t2, zero;
- cmp->c1 = NULL;
+ cmp->c1 = t1 = tcg_temp_new();
cmp->c2 = 0;
switch (cond & 7) {
@@ -989,16 +989,14 @@ static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
case 0x1: /* eq */
cmp->cond = TCG_COND_EQ;
if (TARGET_LONG_BITS == 32 || xcc) {
- cmp->c1 = cpu_cc_Z;
+ tcg_gen_mov_tl(t1, cpu_cc_Z);
} else {
- cmp->c1 = t1 = tcg_temp_new();
tcg_gen_ext32u_tl(t1, cpu_icc_Z);
}
break;
case 0x2: /* le: Z | (N ^ V) */
cmp->cond = TCG_COND_LT;
- cmp->c1 = t1 = tcg_temp_new();
zero = tcg_constant_tl(0);
if (TARGET_LONG_BITS == 32 || xcc) {
tcg_gen_negsetcond_tl(TCG_COND_EQ, t1, cpu_cc_Z, zero);
@@ -1016,7 +1014,6 @@ static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
case 0x3: /* lt: N ^ V */
cmp->cond = TCG_COND_LT;
- cmp->c1 = t1 = tcg_temp_new();
tcg_gen_xor_tl(t1, cpu_cc_N, cpu_cc_V);
if (TARGET_LONG_BITS == 64 && !xcc) {
tcg_gen_ext32s_tl(t1, t1);
@@ -1025,7 +1022,6 @@ static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
case 0x4: /* leu: C | Z -> !(!C & !Z) */
cmp->cond = TCG_COND_EQ;
- cmp->c1 = t1 = tcg_temp_new();
if (TARGET_LONG_BITS == 32 || xcc) {
tcg_gen_subi_tl(t1, cpu_cc_C, 1);
tcg_gen_and_tl(t1, t1, cpu_cc_Z);
@@ -1041,9 +1037,8 @@ static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
case 0x5: /* ltu: C */
cmp->cond = TCG_COND_NE;
if (TARGET_LONG_BITS == 32 || xcc) {
- cmp->c1 = cpu_cc_C;
+ tcg_gen_mov_tl(t1, cpu_cc_C);
} else {
- cmp->c1 = t1 = tcg_temp_new();
tcg_gen_extract_tl(t1, cpu_icc_C, 32, 1);
}
break;
@@ -1051,9 +1046,8 @@ static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
case 0x6: /* neg: N */
cmp->cond = TCG_COND_LT;
if (TARGET_LONG_BITS == 32 || xcc) {
- cmp->c1 = cpu_cc_N;
+ tcg_gen_mov_tl(t1, cpu_cc_N);
} else {
- cmp->c1 = t1 = tcg_temp_new();
tcg_gen_ext32s_tl(t1, cpu_cc_N);
}
break;
@@ -1061,9 +1055,8 @@ static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
case 0x7: /* vs: V */
cmp->cond = TCG_COND_LT;
if (TARGET_LONG_BITS == 32 || xcc) {
- cmp->c1 = cpu_cc_V;
+ tcg_gen_mov_tl(t1, cpu_cc_V);
} else {
- cmp->c1 = t1 = tcg_temp_new();
tcg_gen_ext32s_tl(t1, cpu_cc_V);
}
break;
@@ -1166,8 +1159,9 @@ static const TCGCond gen_tcg_cond_reg[8] = {
static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
{
cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
- cmp->c1 = r_src;
+ cmp->c1 = tcg_temp_new();
cmp->c2 = 0;
+ tcg_gen_mov_tl(cmp->c1, r_src);
}
static void gen_op_clear_ieee_excp_and_FTT(void)
--
2.34.1
next prev parent reply other threads:[~2023-10-17 6:43 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-17 6:40 [PATCH 00/20] target/sparc: Cleanup condition codes etc Richard Henderson
2023-10-17 6:40 ` [PATCH 01/20] target/sparc: Introduce cpu_put_psr_icc Richard Henderson
2023-10-19 14:11 ` Philippe Mathieu-Daudé
2023-10-26 1:04 ` Richard Henderson
2023-10-17 6:40 ` [PATCH 02/20] target/sparc: Split psr and xcc into components Richard Henderson
2023-10-17 6:40 ` [PATCH 03/20] target/sparc: Remove CC_OP_DIV Richard Henderson
2023-10-17 6:40 ` [PATCH 04/20] target/sparc: Remove CC_OP_LOGIC Richard Henderson
2023-10-17 6:40 ` [PATCH 05/20] target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD Richard Henderson
2023-10-17 6:40 ` [PATCH 06/20] target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB Richard Henderson
2023-10-17 6:40 ` [PATCH 07/20] target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV Richard Henderson
2023-10-17 6:40 ` [PATCH 08/20] target/sparc: Remove CC_OP leftovers Richard Henderson
2023-10-17 6:40 ` [PATCH 09/20] target/sparc: Remove DisasCompare.is_bool Richard Henderson
2023-10-17 6:40 ` [PATCH 10/20] target/sparc: Change DisasCompare.c2 to int Richard Henderson
2023-10-17 6:41 ` Richard Henderson [this message]
2023-10-17 6:41 ` [PATCH 12/20] target/sparc: Do flush_cond in advance_jump_cond Richard Henderson
2023-10-17 6:41 ` [PATCH 13/20] target/sparc: Merge gen_branch2 into advance_pc Richard Henderson
2023-10-17 6:41 ` [PATCH 14/20] target/sparc: Merge advance_jump_uncond_{never, always} into advance_jump_cond Richard Henderson
2023-10-17 6:41 ` [PATCH 15/20] target/sparc: Use DISAS_EXIT in do_wrpsr Richard Henderson
2023-10-17 6:41 ` [PATCH 16/20] target/sparc: Merge gen_op_next_insn into only caller Richard Henderson
2023-10-17 6:41 ` [PATCH 17/20] target/sparc: Record entire jump condition in DisasContext Richard Henderson
2023-10-17 6:41 ` [PATCH 18/20] target/sparc: Discard cpu_cond at the end of each insn Richard Henderson
2023-10-17 6:41 ` [PATCH 19/20] target/sparc: Implement UDIVX and SDIVX inline Richard Henderson
2023-10-17 6:41 ` [PATCH 20/20] target/sparc: Implement UDIV inline Richard Henderson
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