From: Nabih Estefan <nabihestefan@google.com>
To: peter.maydell@linaro.org
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kfting@nuvoton.com,
wuhaotsh@google.com, jasonwang@redhat.com,
avi.fishman@nuvoton.com, nabihestefan@google.com
Subject: [PATCH v4 11/11] tests/qtest: Adding PCS Module test to GMAC Qtest
Date: Wed, 18 Oct 2023 18:12:59 +0000 [thread overview]
Message-ID: <20231018181259.748819-12-nabihestefan@google.com> (raw)
In-Reply-To: <20231018181259.748819-1-nabihestefan@google.com>
From: Nabih Estefan Diaz <nabihestefan@google.com>
- Add PCS Register check to npcm_gmac-test
Signed-off-by: Nabih Estefan Diaz <nabihestefan@google.com>
---
tests/qtest/npcm_gmac-test.c | 134 ++++++++++++++++++++++++++++++++++-
1 file changed, 133 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c
index 130a1599a8..0958b13814 100644
--- a/tests/qtest/npcm_gmac-test.c
+++ b/tests/qtest/npcm_gmac-test.c
@@ -20,6 +20,10 @@
/* Name of the GMAC Device */
#define TYPE_NPCM_GMAC "npcm-gmac"
+/* Address of the PCS Module */
+#define PCS_BASE_ADDRESS 0xf0780000
+#define NPCM_PCS_IND_AC_BA 0x1fe
+
typedef struct GMACModule {
int irq;
uint64_t base_addr;
@@ -111,6 +115,62 @@ typedef enum NPCMRegister {
NPCM_GMAC_PTP_STNSUR = 0x714,
NPCM_GMAC_PTP_TAR = 0x718,
NPCM_GMAC_PTP_TTSR = 0x71c,
+
+ /* PCS Registers */
+ NPCM_PCS_SR_CTL_ID1 = 0x3c0008,
+ NPCM_PCS_SR_CTL_ID2 = 0x3c000a,
+ NPCM_PCS_SR_CTL_STS = 0x3c0010,
+
+ NPCM_PCS_SR_MII_CTRL = 0x3e0000,
+ NPCM_PCS_SR_MII_STS = 0x3e0002,
+ NPCM_PCS_SR_MII_DEV_ID1 = 0x3e0004,
+ NPCM_PCS_SR_MII_DEV_ID2 = 0x3e0006,
+ NPCM_PCS_SR_MII_AN_ADV = 0x3e0008,
+ NPCM_PCS_SR_MII_LP_BABL = 0x3e000a,
+ NPCM_PCS_SR_MII_AN_EXPN = 0x3e000c,
+ NPCM_PCS_SR_MII_EXT_STS = 0x3e001e,
+
+ NPCM_PCS_SR_TIM_SYNC_ABL = 0x3e0e10,
+ NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR = 0x3e0e12,
+ NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR = 0x3e0e14,
+ NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR = 0x3e0e16,
+ NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR = 0x3e0e18,
+ NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR = 0x3e0e1a,
+ NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR = 0x3e0e1c,
+ NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR = 0x3e0e1e,
+ NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR = 0x3e0e20,
+
+ NPCM_PCS_VR_MII_MMD_DIG_CTRL1 = 0x3f0000,
+ NPCM_PCS_VR_MII_AN_CTRL = 0x3f0002,
+ NPCM_PCS_VR_MII_AN_INTR_STS = 0x3f0004,
+ NPCM_PCS_VR_MII_TC = 0x3f0006,
+ NPCM_PCS_VR_MII_DBG_CTRL = 0x3f000a,
+ NPCM_PCS_VR_MII_EEE_MCTRL0 = 0x3f000c,
+ NPCM_PCS_VR_MII_EEE_TXTIMER = 0x3f0010,
+ NPCM_PCS_VR_MII_EEE_RXTIMER = 0x3f0012,
+ NPCM_PCS_VR_MII_LINK_TIMER_CTRL = 0x3f0014,
+ NPCM_PCS_VR_MII_EEE_MCTRL1 = 0x3f0016,
+ NPCM_PCS_VR_MII_DIG_STS = 0x3f0020,
+ NPCM_PCS_VR_MII_ICG_ERRCNT1 = 0x3f0022,
+ NPCM_PCS_VR_MII_MISC_STS = 0x3f0030,
+ NPCM_PCS_VR_MII_RX_LSTS = 0x3f0040,
+ NPCM_PCS_VR_MII_MP_TX_BSTCTRL0 = 0x3f0070,
+ NPCM_PCS_VR_MII_MP_TX_LVLCTRL0 = 0x3f0074,
+ NPCM_PCS_VR_MII_MP_TX_GENCTRL0 = 0x3f007a,
+ NPCM_PCS_VR_MII_MP_TX_GENCTRL1 = 0x3f007c,
+ NPCM_PCS_VR_MII_MP_TX_STS = 0x3f0090,
+ NPCM_PCS_VR_MII_MP_RX_GENCTRL0 = 0x3f00b0,
+ NPCM_PCS_VR_MII_MP_RX_GENCTRL1 = 0x3f00b2,
+ NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0 = 0x3f00ba,
+ NPCM_PCS_VR_MII_MP_MPLL_CTRL0 = 0x3f00f0,
+ NPCM_PCS_VR_MII_MP_MPLL_CTRL1 = 0x3f00f2,
+ NPCM_PCS_VR_MII_MP_MPLL_STS = 0x3f0110,
+ NPCM_PCS_VR_MII_MP_MISC_CTRL2 = 0x3f0126,
+ NPCM_PCS_VR_MII_MP_LVL_CTRL = 0x3f0130,
+ NPCM_PCS_VR_MII_MP_MISC_CTRL0 = 0x3f0132,
+ NPCM_PCS_VR_MII_MP_MISC_CTRL1 = 0x3f0134,
+ NPCM_PCS_VR_MII_DIG_CTRL2 = 0x3f01c2,
+ NPCM_PCS_VR_MII_DIG_ERRCNT_SEL = 0x3f01c4,
} NPCMRegister;
static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
@@ -119,6 +179,15 @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
return qtest_readl(qts, mod->base_addr + regno);
}
+static uint16_t pcs_read(QTestState *qts, const GMACModule *mod,
+ NPCMRegister regno)
+{
+ uint32_t write_value = (regno & 0x3ffe00) >> 9;
+ qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value);
+ uint32_t read_offset = regno & 0x1ff;
+ return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset);
+}
+
/* Check that GMAC registers are reset to default value */
static void test_init(gconstpointer test_data)
{
@@ -129,7 +198,12 @@ static void test_init(gconstpointer test_data)
#define CHECK_REG32(regno, value) \
do { \
g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \
- } while (0)
+ } while (0) ;
+
+#define CHECK_REG_PCS(regno, value) \
+ do { \
+ g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \
+ } while (0) ;
CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);
CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);
@@ -180,6 +254,64 @@ static void test_init(gconstpointer test_data)
CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);
CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);
+ /* TODO Add registers PCS */
+ if (mod->base_addr == 0xf0802000) {
+ CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e)
+ CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0)
+ CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000)
+
+ CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140)
+ CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109)
+ CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e)
+ CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0)
+ CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020)
+ CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0)
+ CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0)
+ CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000)
+
+ CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003)
+ CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038)
+ CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0)
+ CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038)
+ CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0)
+ CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058)
+ CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0)
+ CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048)
+ CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0)
+
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0)
+ CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0)
+ }
+
qtest_quit(qts);
}
--
2.42.0.655.g421f12c284-goog
next prev parent reply other threads:[~2023-10-18 18:14 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-18 18:12 [PATCH v4 00/11] Implementation of NPI Mailbox and GMAC Networking Module Nabih Estefan
2023-10-18 18:12 ` [PATCH v4 01/11] hw/misc: Add Nuvoton's PCI Mailbox Module Nabih Estefan
2023-10-18 18:12 ` [PATCH v4 02/11] hw/arm: Add PCI mailbox module to Nuvoton SoC Nabih Estefan
2023-10-18 18:12 ` [PATCH v4 03/11] hw/misc: Add qtest for NPCM7xx PCI Mailbox Nabih Estefan
2023-10-18 18:12 ` [PATCH v4 04/11] hw/net: Add NPCMXXX GMAC device Nabih Estefan
2023-10-18 18:12 ` [PATCH v4 05/11] hw/arm: Add GMAC devices to NPCM7XX SoC Nabih Estefan
2023-10-18 18:12 ` [PATCH v4 06/11] tests/qtest: Creating qtest for GMAC Module Nabih Estefan
2023-10-18 18:12 ` [PATCH v4 07/11] include/hw/net: Implemented Classes and Masks for GMAC Descriptors Nabih Estefan
2023-10-18 18:12 ` [PATCH v4 08/11] hw/net: General GMAC Implementation Nabih Estefan
2023-10-18 18:12 ` [PATCH v4 09/11] hw/net: GMAC Rx Implementation Nabih Estefan
2023-10-18 18:12 ` [PATCH v4 10/11] hw/net: GMAC Tx Implementation Nabih Estefan
2023-10-18 18:12 ` Nabih Estefan [this message]
2023-10-27 12:07 ` [PATCH v4 00/11] Implementation of NPI Mailbox and GMAC Networking Module Peter Maydell
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