* [PATCH 01/61] include/hw/elf: Remove truncating signed casts
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 02/61] target/hppa: Remove get_temp Richard Henderson
` (59 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
There's nothing about elf that specifically requires signed vs unsigned.
This is very much a target-specific preference.
In the meantime, casting low and high from uint64_t back to Elf_SWord
to uint64_t discards high bits that might have been set by translate_fn.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/elf_ops.h | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h
index dffb0e73d2..0a5c258fe6 100644
--- a/include/hw/elf_ops.h
+++ b/include/hw/elf_ops.h
@@ -385,10 +385,11 @@ static ssize_t glue(load_elf, SZ)(const char *name, int fd,
}
if (pflags) {
- *pflags = (elf_word)ehdr.e_flags;
+ *pflags = ehdr.e_flags;
+ }
+ if (pentry) {
+ *pentry = ehdr.e_entry;
}
- if (pentry)
- *pentry = (uint64_t)(elf_sword)ehdr.e_entry;
glue(load_symbols, SZ)(&ehdr, fd, must_swab, clear_lsb, sym_cb);
@@ -610,10 +611,12 @@ static ssize_t glue(load_elf, SZ)(const char *name, int fd,
}
}
- if (lowaddr)
- *lowaddr = (uint64_t)(elf_sword)low;
- if (highaddr)
- *highaddr = (uint64_t)(elf_sword)high;
+ if (lowaddr) {
+ *lowaddr = low;
+ }
+ if (highaddr) {
+ *highaddr = high;
+ }
ret = total_size;
fail:
if (mapped_file) {
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 02/61] target/hppa: Remove get_temp
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
2023-10-18 21:50 ` [PATCH 01/61] include/hw/elf: Remove truncating signed casts Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-19 9:41 ` Philippe Mathieu-Daudé
2023-10-18 21:50 ` [PATCH 03/61] target/hppa: Remove get_temp_tl Richard Henderson
` (58 subsequent siblings)
60 siblings, 1 reply; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Replace with tcg_temp_new without recording into ctx.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 76 +++++++++++++++++------------------------
1 file changed, 31 insertions(+), 45 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 9f3ba9f42f..3065fbf625 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -254,8 +254,7 @@ typedef struct DisasContext {
target_ureg iaoq_n;
TCGv_reg iaoq_n_var;
- int ntempr, ntempl;
- TCGv_reg tempr[8];
+ int ntempl;
TCGv_tl templ[4];
DisasCond null_cond;
@@ -492,13 +491,6 @@ static void cond_free(DisasCond *cond)
}
}
-static TCGv_reg get_temp(DisasContext *ctx)
-{
- unsigned i = ctx->ntempr++;
- g_assert(i < ARRAY_SIZE(ctx->tempr));
- return ctx->tempr[i] = tcg_temp_new();
-}
-
#ifndef CONFIG_USER_ONLY
static TCGv_tl get_temp_tl(DisasContext *ctx)
{
@@ -510,7 +502,7 @@ static TCGv_tl get_temp_tl(DisasContext *ctx)
static TCGv_reg load_const(DisasContext *ctx, target_sreg v)
{
- TCGv_reg t = get_temp(ctx);
+ TCGv_reg t = tcg_temp_new();
tcg_gen_movi_reg(t, v);
return t;
}
@@ -518,7 +510,7 @@ static TCGv_reg load_const(DisasContext *ctx, target_sreg v)
static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg)
{
if (reg == 0) {
- TCGv_reg t = get_temp(ctx);
+ TCGv_reg t = tcg_temp_new();
tcg_gen_movi_reg(t, 0);
return t;
} else {
@@ -529,7 +521,7 @@ static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg)
static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg)
{
if (reg == 0 || ctx->null_cond.c != TCG_COND_NEVER) {
- return get_temp(ctx);
+ return tcg_temp_new();
} else {
return cpu_gr[reg];
}
@@ -1071,7 +1063,7 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg res,
static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res,
TCGv_reg in1, TCGv_reg in2)
{
- TCGv_reg sv = get_temp(ctx);
+ TCGv_reg sv = tcg_temp_new();
TCGv_reg tmp = tcg_temp_new();
tcg_gen_xor_reg(sv, res, in1);
@@ -1085,7 +1077,7 @@ static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res,
static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res,
TCGv_reg in1, TCGv_reg in2)
{
- TCGv_reg sv = get_temp(ctx);
+ TCGv_reg sv = tcg_temp_new();
TCGv_reg tmp = tcg_temp_new();
tcg_gen_xor_reg(sv, res, in1);
@@ -1108,20 +1100,20 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
cb_msb = NULL;
if (shift) {
- tmp = get_temp(ctx);
+ tmp = tcg_temp_new();
tcg_gen_shli_reg(tmp, in1, shift);
in1 = tmp;
}
if (!is_l || cond_need_cb(c)) {
TCGv_reg zero = tcg_constant_reg(0);
- cb_msb = get_temp(ctx);
+ cb_msb = tcg_temp_new();
tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero);
if (is_c) {
tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, zero);
}
if (!is_l) {
- cb = get_temp(ctx);
+ cb = tcg_temp_new();
tcg_gen_xor_reg(cb, in1, in2);
tcg_gen_xor_reg(cb, cb, dest);
}
@@ -1414,11 +1406,11 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs,
/* Note that RX is mutually exclusive with DISP. */
if (rx) {
- ofs = get_temp(ctx);
+ ofs = tcg_temp_new();
tcg_gen_shli_reg(ofs, cpu_gr[rx], scale);
tcg_gen_add_reg(ofs, ofs, base);
} else if (disp || modify) {
- ofs = get_temp(ctx);
+ ofs = tcg_temp_new();
tcg_gen_addi_reg(ofs, base, disp);
} else {
ofs = base;
@@ -1538,7 +1530,7 @@ static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,
dest = dest_gpr(ctx, rt);
} else {
/* Make sure if RT == RB, we see the result of the load. */
- dest = get_temp(ctx);
+ dest = tcg_temp_new();
}
do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop);
save_gpr(ctx, rt, dest);
@@ -1854,7 +1846,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg dest,
if (link != 0) {
copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
}
- next = get_temp(ctx);
+ next = tcg_temp_new();
tcg_gen_mov_reg(next, dest);
if (is_n) {
if (use_nullify_skip(ctx)) {
@@ -1896,7 +1888,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg dest,
a1 = ctx->null_cond.a1;
tmp = tcg_temp_new();
- next = get_temp(ctx);
+ next = tcg_temp_new();
copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var);
tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest);
@@ -1938,11 +1930,11 @@ static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset)
return offset;
case 3:
/* Privilege 3 is minimum and is never allowed to increase. */
- dest = get_temp(ctx);
+ dest = tcg_temp_new();
tcg_gen_ori_reg(dest, offset, 3);
break;
default:
- dest = get_temp(ctx);
+ dest = tcg_temp_new();
tcg_gen_andi_reg(dest, offset, -4);
tcg_gen_ori_reg(dest, dest, ctx->privilege);
tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset);
@@ -2104,7 +2096,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a)
break;
}
- tmp = get_temp(ctx);
+ tmp = tcg_temp_new();
tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
save_gpr(ctx, rt, tmp);
@@ -2177,7 +2169,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
case CR_IIAOQ:
/* FIXME: Respect PSW_Q bit */
/* The write advances the queue and stores to the back element. */
- tmp = get_temp(ctx);
+ tmp = tcg_temp_new();
tcg_gen_ld_reg(tmp, tcg_env,
offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ]));
tcg_gen_st_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
@@ -2243,7 +2235,7 @@ static bool trans_rsm(DisasContext *ctx, arg_rsm *a)
nullify_over(ctx);
- tmp = get_temp(ctx);
+ tmp = tcg_temp_new();
tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw));
tcg_gen_andi_reg(tmp, tmp, ~a->i);
gen_helper_swap_system_mask(tmp, tcg_env, tmp);
@@ -2263,7 +2255,7 @@ static bool trans_ssm(DisasContext *ctx, arg_ssm *a)
nullify_over(ctx);
- tmp = get_temp(ctx);
+ tmp = tcg_temp_new();
tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw));
tcg_gen_ori_reg(tmp, tmp, a->i);
gen_helper_swap_system_mask(tmp, tcg_env, tmp);
@@ -2283,7 +2275,7 @@ static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a)
nullify_over(ctx);
reg = load_gpr(ctx, a->r);
- tmp = get_temp(ctx);
+ tmp = tcg_temp_new();
gen_helper_swap_system_mask(tmp, tcg_env, reg);
/* Exit the TB to recognize new interrupts. */
@@ -2692,7 +2684,7 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc)
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
- tmp = get_temp(ctx);
+ tmp = tcg_temp_new();
tcg_gen_not_reg(tmp, tcg_r2);
do_unit(ctx, a->t, tcg_r1, tmp, a->cf, is_tc, tcg_gen_add_reg);
return nullify_end(ctx);
@@ -2714,7 +2706,7 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, bool is_i)
nullify_over(ctx);
- tmp = get_temp(ctx);
+ tmp = tcg_temp_new();
tcg_gen_shri_reg(tmp, cpu_psw_cb, 3);
if (!is_i) {
tcg_gen_not_reg(tmp, tmp);
@@ -2866,7 +2858,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
if (a->m) {
/* Base register modification. Make sure if RT == RB,
we see the result of the load. */
- dest = get_temp(ctx);
+ dest = tcg_temp_new();
} else {
dest = dest_gpr(ctx, a->t);
}
@@ -2992,7 +2984,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1,
DisasCond cond;
in2 = load_gpr(ctx, r);
- dest = get_temp(ctx);
+ dest = tcg_temp_new();
tcg_gen_sub_reg(dest, in1, in2);
@@ -3029,7 +3021,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1,
cb_msb = NULL;
if (cond_need_cb(c)) {
- cb_msb = get_temp(ctx);
+ cb_msb = tcg_temp_new();
tcg_gen_movi_reg(cb_msb, 0);
tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb);
} else {
@@ -3388,7 +3380,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a)
nullify_over(ctx);
#endif
- tmp = get_temp(ctx);
+ tmp = tcg_temp_new();
tcg_gen_addi_reg(tmp, load_gpr(ctx, a->b), a->disp);
tmp = do_ibranch_priv(ctx, tmp);
@@ -3485,7 +3477,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a)
static bool trans_blr(DisasContext *ctx, arg_blr *a)
{
if (a->x) {
- TCGv_reg tmp = get_temp(ctx);
+ TCGv_reg tmp = tcg_temp_new();
tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3);
tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8);
/* The computation here never changes privilege level. */
@@ -3503,7 +3495,7 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a)
if (a->x == 0) {
dest = load_gpr(ctx, a->b);
} else {
- dest = get_temp(ctx);
+ dest = tcg_temp_new();
tcg_gen_shli_reg(dest, load_gpr(ctx, a->x), 3);
tcg_gen_add_reg(dest, dest, load_gpr(ctx, a->b));
}
@@ -3834,7 +3826,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
nullify_over(ctx);
- t = get_temp(ctx);
+ t = tcg_temp_new();
tcg_gen_ld32u_reg(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow));
if (a->y == 1) {
@@ -4089,9 +4081,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
- ctx->ntempr = 0;
ctx->ntempl = 0;
- memset(ctx->tempr, 0, sizeof(ctx->tempr));
memset(ctx->templ, 0, sizeof(ctx->templ));
}
@@ -4140,7 +4130,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
This will be overwritten by a branch. */
if (ctx->iaoq_b == -1) {
ctx->iaoq_n = -1;
- ctx->iaoq_n_var = get_temp(ctx);
+ ctx->iaoq_n_var = tcg_temp_new();
tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4);
} else {
ctx->iaoq_n = ctx->iaoq_b + 4;
@@ -4161,13 +4151,9 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
}
/* Forget any temporaries allocated. */
- for (i = 0, n = ctx->ntempr; i < n; ++i) {
- ctx->tempr[i] = NULL;
- }
for (i = 0, n = ctx->ntempl; i < n; ++i) {
ctx->templ[i] = NULL;
}
- ctx->ntempr = 0;
ctx->ntempl = 0;
/* Advance the insn queue. Note that this check also detects
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 03/61] target/hppa: Remove get_temp_tl
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
2023-10-18 21:50 ` [PATCH 01/61] include/hw/elf: Remove truncating signed casts Richard Henderson
2023-10-18 21:50 ` [PATCH 02/61] target/hppa: Remove get_temp Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-19 9:42 ` Philippe Mathieu-Daudé
2023-10-18 21:50 ` [PATCH 04/61] target/hppa: Remove load_const Richard Henderson
` (57 subsequent siblings)
60 siblings, 1 reply; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Replace with tcg_temp_new_tl without recording into ctx.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 28 +++-------------------------
1 file changed, 3 insertions(+), 25 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 3065fbf625..5302381a56 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -254,9 +254,6 @@ typedef struct DisasContext {
target_ureg iaoq_n;
TCGv_reg iaoq_n_var;
- int ntempl;
- TCGv_tl templ[4];
-
DisasCond null_cond;
TCGLabel *null_lab;
@@ -491,15 +488,6 @@ static void cond_free(DisasCond *cond)
}
}
-#ifndef CONFIG_USER_ONLY
-static TCGv_tl get_temp_tl(DisasContext *ctx)
-{
- unsigned i = ctx->ntempl++;
- g_assert(i < ARRAY_SIZE(ctx->templ));
- return ctx->templ[i] = tcg_temp_new_tl();
-}
-#endif
-
static TCGv_reg load_const(DisasContext *ctx, target_sreg v)
{
TCGv_reg t = tcg_temp_new();
@@ -1374,7 +1362,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base)
if (sp < 0) {
sp = ~sp;
}
- spc = get_temp_tl(ctx);
+ spc = tcg_temp_new_tl();
load_spr(ctx, spc, sp);
return spc;
}
@@ -1384,7 +1372,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base)
ptr = tcg_temp_new_ptr();
tmp = tcg_temp_new();
- spc = get_temp_tl(ctx);
+ spc = tcg_temp_new_tl();
tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5);
tcg_gen_andi_reg(tmp, tmp, 030);
@@ -1420,7 +1408,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs,
#ifdef CONFIG_USER_ONLY
*pgva = (modify <= 0 ? ofs : base);
#else
- TCGv_tl addr = get_temp_tl(ctx);
+ TCGv_tl addr = tcg_temp_new_tl();
tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base);
if (ctx->tb_flags & PSW_W) {
tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull);
@@ -4080,9 +4068,6 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
/* Bound the number of instructions by those left on the page. */
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
-
- ctx->ntempl = 0;
- memset(ctx->templ, 0, sizeof(ctx->templ));
}
static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
@@ -4111,7 +4096,6 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUHPPAState *env = cpu_env(cs);
DisasJumpType ret;
- int i, n;
/* Execute one insn. */
#ifdef CONFIG_USER_ONLY
@@ -4150,12 +4134,6 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
}
}
- /* Forget any temporaries allocated. */
- for (i = 0, n = ctx->ntempl; i < n; ++i) {
- ctx->templ[i] = NULL;
- }
- ctx->ntempl = 0;
-
/* Advance the insn queue. Note that this check also detects
a priority change within the instruction queue. */
if (ret == DISAS_NEXT && ctx->iaoq_b != ctx->iaoq_f + 4) {
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 04/61] target/hppa: Remove load_const
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (2 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 03/61] target/hppa: Remove get_temp_tl Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 05/61] target/hppa: Fix hppa64 case in machine.c Richard Henderson
` (56 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Replace with tcg_constant_reg.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 21 +++++++--------------
1 file changed, 7 insertions(+), 14 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 5302381a56..21f97f63a9 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -488,13 +488,6 @@ static void cond_free(DisasCond *cond)
}
}
-static TCGv_reg load_const(DisasContext *ctx, target_sreg v)
-{
- TCGv_reg t = tcg_temp_new();
- tcg_gen_movi_reg(t, v);
- return t;
-}
-
static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg)
{
if (reg == 0) {
@@ -1164,7 +1157,7 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a,
if (a->cf) {
nullify_over(ctx);
}
- tcg_im = load_const(ctx, a->i);
+ tcg_im = tcg_constant_reg(a->i);
tcg_r2 = load_gpr(ctx, a->r);
do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf);
return nullify_end(ctx);
@@ -1253,7 +1246,7 @@ static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv)
if (a->cf) {
nullify_over(ctx);
}
- tcg_im = load_const(ctx, a->i);
+ tcg_im = tcg_constant_reg(a->i);
tcg_r2 = load_gpr(ctx, a->r);
do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf);
return nullify_end(ctx);
@@ -2808,7 +2801,7 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a)
nullify_over(ctx);
}
- tcg_im = load_const(ctx, a->i);
+ tcg_im = tcg_constant_reg(a->i);
tcg_r2 = load_gpr(ctx, a->r);
do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf);
@@ -2994,7 +2987,7 @@ static bool trans_cmpb(DisasContext *ctx, arg_cmpb *a)
static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a)
{
nullify_over(ctx);
- return do_cmpb(ctx, a->r, load_const(ctx, a->i), a->c, a->f, a->n, a->disp);
+ return do_cmpb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a->disp);
}
static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1,
@@ -3033,7 +3026,7 @@ static bool trans_addb(DisasContext *ctx, arg_addb *a)
static bool trans_addbi(DisasContext *ctx, arg_addbi *a)
{
nullify_over(ctx);
- return do_addb(ctx, a->r, load_const(ctx, a->i), a->c, a->f, a->n, a->disp);
+ return do_addb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a->disp);
}
static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
@@ -3345,7 +3338,7 @@ static bool trans_depwi_sar(DisasContext *ctx, arg_depwi_sar *a)
if (a->c) {
nullify_over(ctx);
}
- return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_const(ctx, a->i));
+ return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, tcg_constant_reg(a->i));
}
static bool trans_be(DisasContext *ctx, arg_be *a)
@@ -3852,7 +3845,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
return true;
}
if (inv) {
- TCGv_reg c = load_const(ctx, mask);
+ TCGv_reg c = tcg_constant_reg(mask);
tcg_gen_or_reg(t, t, c);
ctx->null_cond = cond_make(TCG_COND_EQ, t, c);
} else {
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 05/61] target/hppa: Fix hppa64 case in machine.c
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (3 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 04/61] target/hppa: Remove load_const Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 06/61] target/hppa: Fix load in do_load_32 Richard Henderson
` (55 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Typo of VMSTATE_UINTTR_V and VMSTATE_UINTTR_ARRAY_V macros.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/machine.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/hppa/machine.c b/target/hppa/machine.c
index 905991d7f9..0c0bba68c0 100644
--- a/target/hppa/machine.c
+++ b/target/hppa/machine.c
@@ -24,9 +24,9 @@
#if TARGET_REGISTER_BITS == 64
#define qemu_put_betr qemu_put_be64
#define qemu_get_betr qemu_get_be64
-#define VMSTATE_UINTTL_V(_f, _s, _v) \
+#define VMSTATE_UINTTR_V(_f, _s, _v) \
VMSTATE_UINT64_V(_f, _s, _v)
-#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
+#define VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v)
#else
#define qemu_put_betr qemu_put_be32
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 06/61] target/hppa: Fix load in do_load_32
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (4 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 05/61] target/hppa: Fix hppa64 case in machine.c Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-19 9:42 ` Philippe Mathieu-Daudé
2023-10-18 21:50 ` [PATCH 07/61] target/hppa: Truncate rotate count in trans_shrpw_sar Richard Henderson
` (54 subsequent siblings)
60 siblings, 1 reply; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
The destination is TCGv_i32, so use tcg_gen_qemu_ld_i32
not tcg_gen_qemu_ld_reg.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 21f97f63a9..ff559ed21d 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1430,7 +1430,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
ctx->mmu_idx == MMU_PHYS_IDX);
- tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
+ tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
if (modify) {
save_gpr(ctx, rb, ofs);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 07/61] target/hppa: Truncate rotate count in trans_shrpw_sar
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (5 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 06/61] target/hppa: Fix load in do_load_32 Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 08/61] target/hppa: Fix trans_ds for hppa64 Richard Henderson
` (53 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
When forcing rotate by i32, the shift count must be as well.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index ff559ed21d..e6ab113a1c 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3105,8 +3105,11 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a)
tcg_gen_shr_reg(dest, dest, cpu_sar);
} else if (a->r1 == a->r2) {
TCGv_i32 t32 = tcg_temp_new_i32();
+ TCGv_i32 s32 = tcg_temp_new_i32();
+
tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2));
- tcg_gen_rotr_i32(t32, t32, cpu_sar);
+ tcg_gen_trunc_reg_i32(s32, cpu_sar);
+ tcg_gen_rotr_i32(t32, t32, s32);
tcg_gen_extu_i32_reg(dest, t32);
} else {
TCGv_i64 t = tcg_temp_new_i64();
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 08/61] target/hppa: Fix trans_ds for hppa64
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (6 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 07/61] target/hppa: Truncate rotate count in trans_shrpw_sar Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 09/61] target/hppa: Fix do_add, do_sub " Richard Henderson
` (52 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
This instruction always uses the input carry from bit 32,
but produces all 16 output carry bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 48 +++++++++++++++++++++++++++++++----------
1 file changed, 37 insertions(+), 11 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index e6ab113a1c..fb7a295367 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -803,6 +803,12 @@ static bool cond_need_cb(int c)
return c == 4 || c == 5;
}
+/* Need extensions from TCGv_i32 to TCGv_reg. */
+static bool cond_need_ext(DisasContext *ctx, bool d)
+{
+ return TARGET_REGISTER_BITS == 64 && !d;
+}
+
/*
* Compute conditional for arithmetic. See Page 5-3, Table 5-1, of
* the Parisc 1.1 Architecture Reference Manual for details.
@@ -1040,6 +1046,22 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg res,
return cond;
}
+static TCGv_reg get_carry(DisasContext *ctx, bool d,
+ TCGv_reg cb, TCGv_reg cb_msb)
+{
+ if (cond_need_ext(ctx, d)) {
+ TCGv_reg t = tcg_temp_new();
+ tcg_gen_extract_reg(t, cb, 32, 1);
+ return t;
+ }
+ return cb_msb;
+}
+
+static TCGv_reg get_psw_carry(DisasContext *ctx, bool d)
+{
+ return get_carry(ctx, d, cpu_psw_cb, cpu_psw_cb_msb);
+}
+
/* Compute signed overflow for addition. */
static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res,
TCGv_reg in1, TCGv_reg in2)
@@ -2712,6 +2734,7 @@ static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf *a)
static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
{
TCGv_reg dest, add1, add2, addc, zero, in1, in2;
+ TCGv_reg cout;
nullify_over(ctx);
@@ -2726,18 +2749,20 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
/* Form R1 << 1 | PSW[CB]{8}. */
tcg_gen_add_reg(add1, in1, in1);
- tcg_gen_add_reg(add1, add1, cpu_psw_cb_msb);
+ tcg_gen_add_reg(add1, add1, get_psw_carry(ctx, false));
- /* Add or subtract R2, depending on PSW[V]. Proper computation of
- carry{8} requires that we subtract via + ~R2 + 1, as described in
- the manual. By extracting and masking V, we can produce the
- proper inputs to the addition without movcond. */
- tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1);
+ /*
+ * Add or subtract R2, depending on PSW[V]. Proper computation of
+ * carry requires that we subtract via + ~R2 + 1, as described in
+ * the manual. By extracting and masking V, we can produce the
+ * proper inputs to the addition without movcond.
+ */
+ tcg_gen_sextract_reg(addc, cpu_psw_v, 31, 1);
tcg_gen_xor_reg(add2, in2, addc);
tcg_gen_andi_reg(addc, addc, 1);
- /* ??? This is only correct for 32-bit. */
- tcg_gen_add2_i32(dest, cpu_psw_cb_msb, add1, zero, add2, zero);
- tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero);
+
+ tcg_gen_add2_reg(dest, cpu_psw_cb_msb, add1, zero, add2, zero);
+ tcg_gen_add2_reg(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero);
/* Write back the result register. */
save_gpr(ctx, a->t, dest);
@@ -2747,7 +2772,8 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest);
/* Write back PSW[V] for the division step. */
- tcg_gen_neg_reg(cpu_psw_v, cpu_psw_cb_msb);
+ cout = get_psw_carry(ctx, false);
+ tcg_gen_neg_reg(cpu_psw_v, cout);
tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2);
/* Install the new nullification. */
@@ -2757,7 +2783,7 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
/* ??? The lshift is supposed to contribute to overflow. */
sv = do_add_sv(ctx, dest, add1, add2);
}
- ctx->null_cond = do_cond(a->cf, dest, cpu_psw_cb_msb, sv);
+ ctx->null_cond = do_cond(a->cf, dest, cout, sv);
}
return nullify_end(ctx);
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 09/61] target/hppa: Fix do_add, do_sub for hppa64
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (7 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 08/61] target/hppa: Fix trans_ds for hppa64 Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 10/61] target/hppa: Fix bb_sar " Richard Henderson
` (51 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Select the proper carry bit for input to the arithmetic
and for output for the condition.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 50 ++++++++++++++++++++++++++---------------
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index fb7a295367..8ebe7523a7 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1094,13 +1094,15 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
TCGv_reg in2, unsigned shift, bool is_l,
bool is_tsv, bool is_tc, bool is_c, unsigned cf)
{
- TCGv_reg dest, cb, cb_msb, sv, tmp;
+ TCGv_reg dest, cb, cb_msb, cb_cond, sv, tmp;
unsigned c = cf >> 1;
DisasCond cond;
+ bool d = false;
dest = tcg_temp_new();
cb = NULL;
cb_msb = NULL;
+ cb_cond = NULL;
if (shift) {
tmp = tcg_temp_new();
@@ -1111,19 +1113,22 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
if (!is_l || cond_need_cb(c)) {
TCGv_reg zero = tcg_constant_reg(0);
cb_msb = tcg_temp_new();
+ cb = tcg_temp_new();
+
tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero);
if (is_c) {
- tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, zero);
+ tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb,
+ get_psw_carry(ctx, d), zero);
}
- if (!is_l) {
- cb = tcg_temp_new();
- tcg_gen_xor_reg(cb, in1, in2);
- tcg_gen_xor_reg(cb, cb, dest);
+ tcg_gen_xor_reg(cb, in1, in2);
+ tcg_gen_xor_reg(cb, cb, dest);
+ if (cond_need_cb(c)) {
+ cb_cond = get_carry(ctx, d, cb, cb_msb);
}
} else {
tcg_gen_add_reg(dest, in1, in2);
if (is_c) {
- tcg_gen_add_reg(dest, dest, cpu_psw_cb_msb);
+ tcg_gen_add_reg(dest, dest, get_psw_carry(ctx, d));
}
}
@@ -1138,7 +1143,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
}
/* Emit any conditional trap before any writeback. */
- cond = do_cond(cf, dest, cb_msb, sv);
+ cond = do_cond(cf, dest, cb_cond, sv);
if (is_tc) {
tmp = tcg_temp_new();
tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
@@ -1192,6 +1197,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
TCGv_reg dest, sv, cb, cb_msb, zero, tmp;
unsigned c = cf >> 1;
DisasCond cond;
+ bool d = false;
dest = tcg_temp_new();
cb = tcg_temp_new();
@@ -1201,15 +1207,17 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
if (is_b) {
/* DEST,C = IN1 + ~IN2 + C. */
tcg_gen_not_reg(cb, in2);
- tcg_gen_add2_reg(dest, cb_msb, in1, zero, cpu_psw_cb_msb, zero);
+ tcg_gen_add2_reg(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), zero);
tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero);
tcg_gen_xor_reg(cb, cb, in1);
tcg_gen_xor_reg(cb, cb, dest);
} else {
- /* DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer
- operations by seeding the high word with 1 and subtracting. */
- tcg_gen_movi_reg(cb_msb, 1);
- tcg_gen_sub2_reg(dest, cb_msb, in1, cb_msb, in2, zero);
+ /*
+ * DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer
+ * operations by seeding the high word with 1 and subtracting.
+ */
+ TCGv_reg one = tcg_constant_reg(1);
+ tcg_gen_sub2_reg(dest, cb_msb, in1, one, in2, zero);
tcg_gen_eqv_reg(cb, in1, in2);
tcg_gen_xor_reg(cb, cb, dest);
}
@@ -1227,7 +1235,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
if (!is_b) {
cond = do_sub_cond(cf, dest, in1, in2, sv);
} else {
- cond = do_cond(cf, dest, cb_msb, sv);
+ cond = do_cond(cf, dest, get_carry(ctx, d, cb, cb_msb), sv);
}
/* Emit any conditional trap before any writeback. */
@@ -3019,18 +3027,24 @@ static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a)
static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1,
unsigned c, unsigned f, unsigned n, int disp)
{
- TCGv_reg dest, in2, sv, cb_msb;
+ TCGv_reg dest, in2, sv, cb_cond;
DisasCond cond;
+ bool d = false;
in2 = load_gpr(ctx, r);
dest = tcg_temp_new();
sv = NULL;
- cb_msb = NULL;
+ cb_cond = NULL;
if (cond_need_cb(c)) {
- cb_msb = tcg_temp_new();
+ TCGv_reg cb = tcg_temp_new();
+ TCGv_reg cb_msb = tcg_temp_new();
+
tcg_gen_movi_reg(cb_msb, 0);
tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb);
+ tcg_gen_xor_reg(cb, in1, in2);
+ tcg_gen_xor_reg(cb, cb, dest);
+ cb_cond = get_carry(ctx, d, cb, cb_msb);
} else {
tcg_gen_add_reg(dest, in1, in2);
}
@@ -3038,7 +3052,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1,
sv = do_add_sv(ctx, dest, in1, in2);
}
- cond = do_cond(c * 2 + f, dest, cb_msb, sv);
+ cond = do_cond(c * 2 + f, dest, cb_cond, sv);
save_gpr(ctx, r, dest);
return do_cbranch(ctx, disp, n, &cond);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 10/61] target/hppa: Fix bb_sar for hppa64
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (8 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 09/61] target/hppa: Fix do_add, do_sub " Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 11/61] target/hppa: Fix extrw and depw with sar " Richard Henderson
` (50 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 8ebe7523a7..119422870c 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3073,14 +3073,21 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
{
TCGv_reg tmp, tcg_r;
DisasCond cond;
+ bool d = false;
nullify_over(ctx);
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
- tcg_gen_shl_reg(tmp, tcg_r, cpu_sar);
+ if (cond_need_ext(ctx, d)) {
+ /* Force shift into [32,63] */
+ tcg_gen_ori_reg(tmp, cpu_sar, 32);
+ tcg_gen_shl_reg(tmp, tcg_r, tmp);
+ } else {
+ tcg_gen_shl_reg(tmp, tcg_r, cpu_sar);
+ }
- cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
+ cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
@@ -3088,12 +3095,15 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
{
TCGv_reg tmp, tcg_r;
DisasCond cond;
+ bool d = false;
+ int p;
nullify_over(ctx);
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
- tcg_gen_shli_reg(tmp, tcg_r, a->p);
+ p = a->p | (cond_need_ext(ctx, d) ? 32 : 0);
+ tcg_gen_shli_reg(tmp, tcg_r, p);
cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
return do_cbranch(ctx, a->disp, a->n, &cond);
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 11/61] target/hppa: Fix extrw and depw with sar for hppa64
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (9 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 10/61] target/hppa: Fix bb_sar " Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 12/61] target/hppa: Introduce TYPE_HPPA64_CPU Richard Henderson
` (49 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
These are 32-bit operations regardless of processor.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 119422870c..f86ea9b9ca 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3230,7 +3230,9 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a)
tmp = tcg_temp_new();
/* Recall that SAR is using big-endian bit numbering. */
- tcg_gen_xori_reg(tmp, cpu_sar, TARGET_REGISTER_BITS - 1);
+ tcg_gen_andi_reg(tmp, cpu_sar, 31);
+ tcg_gen_xori_reg(tmp, tmp, 31);
+
if (a->se) {
tcg_gen_sar_reg(dest, src, tmp);
tcg_gen_sextract_reg(dest, dest, 0, len);
@@ -3355,7 +3357,8 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c,
tmp = tcg_temp_new();
/* Convert big-endian bit numbering in SAR to left-shift. */
- tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1);
+ tcg_gen_andi_reg(shift, cpu_sar, 31);
+ tcg_gen_xori_reg(shift, shift, 31);
mask = tcg_temp_new();
tcg_gen_movi_reg(mask, msb + (msb - 1));
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 12/61] target/hppa: Introduce TYPE_HPPA64_CPU
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (10 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 11/61] target/hppa: Fix extrw and depw with sar " Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-19 9:44 ` Philippe Mathieu-Daudé
2023-10-18 21:50 ` [PATCH 13/61] target/hppa: Make HPPA_BTLB_ENTRIES variable Richard Henderson
` (48 subsequent siblings)
60 siblings, 1 reply; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Prepare for the qemu binary supporting both pa10 and pa20
at the same time.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu-qom.h | 1 +
target/hppa/cpu.h | 7 +++++++
target/hppa/cpu.c | 17 +++++++++++++++++
target/hppa/translate.c | 3 +++
4 files changed, 28 insertions(+)
diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h
index b96e0318c7..4a85ebf5e0 100644
--- a/target/hppa/cpu-qom.h
+++ b/target/hppa/cpu-qom.h
@@ -24,6 +24,7 @@
#include "qom/object.h"
#define TYPE_HPPA_CPU "hppa-cpu"
+#define TYPE_HPPA64_CPU "hppa64-cpu"
OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 798d0c26d7..743fc90e14 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -239,10 +239,17 @@ struct ArchCPU {
CPUHPPAState env;
QEMUTimer *alarm_timer;
+
+ bool is_pa20;
};
#include "exec/cpu-all.h"
+static inline bool hppa_is_pa20(HPPACPU *cpu)
+{
+ return cpu->is_pa20;
+}
+
static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 1644297bf8..ed5b6afd10 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -218,9 +218,26 @@ static const TypeInfo hppa_cpu_type_info = {
.class_init = hppa_cpu_class_init,
};
+#ifdef TARGET_HPPA64
+static void hppa64_cpu_initfn(Object *obj)
+{
+ HPPACPU *cpu = HPPA_CPU(obj);
+ cpu->is_pa20 = true;
+}
+
+static const TypeInfo hppa64_cpu_type_info = {
+ .name = TYPE_HPPA64_CPU,
+ .parent = TYPE_HPPA_CPU,
+ .instance_init = hppa64_cpu_initfn,
+};
+#endif
+
static void hppa_cpu_register_types(void)
{
type_register_static(&hppa_cpu_type_info);
+#ifdef TARGET_HPPA64
+ type_register_static(&hppa64_cpu_type_info);
+#endif
}
type_init(hppa_cpu_register_types)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index f86ea9b9ca..9d6670f91c 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -262,6 +262,7 @@ typedef struct DisasContext {
int mmu_idx;
int privilege;
bool psw_n_nonzero;
+ bool is_pa20;
#ifdef CONFIG_USER_ONLY
MemOp unalign;
@@ -4087,10 +4088,12 @@ static bool trans_diag(DisasContext *ctx, arg_diag *a)
static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ HPPACPU *cpu = HPPA_CPU(cs);
int bound;
ctx->cs = cs;
ctx->tb_flags = ctx->base.tb->flags;
+ ctx->is_pa20 = cpu->is_pa20;
#ifdef CONFIG_USER_ONLY
ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX);
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* Re: [PATCH 12/61] target/hppa: Introduce TYPE_HPPA64_CPU
2023-10-18 21:50 ` [PATCH 12/61] target/hppa: Introduce TYPE_HPPA64_CPU Richard Henderson
@ 2023-10-19 9:44 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 67+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-19 9:44 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: deller
On 18/10/23 23:50, Richard Henderson wrote:
> Prepare for the qemu binary supporting both pa10 and pa20
> at the same time.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/hppa/cpu-qom.h | 1 +
> target/hppa/cpu.h | 7 +++++++
> target/hppa/cpu.c | 17 +++++++++++++++++
> target/hppa/translate.c | 3 +++
> 4 files changed, 28 insertions(+)
> +#ifdef TARGET_HPPA64
> +static void hppa64_cpu_initfn(Object *obj)
> +{
> + HPPACPU *cpu = HPPA_CPU(obj);
> + cpu->is_pa20 = true;
> +}
> +
> +static const TypeInfo hppa64_cpu_type_info = {
> + .name = TYPE_HPPA64_CPU,
> + .parent = TYPE_HPPA_CPU,
> + .instance_init = hppa64_cpu_initfn,
> +};
> +#endif
> +
> static void hppa_cpu_register_types(void)
> {
> type_register_static(&hppa_cpu_type_info);
> +#ifdef TARGET_HPPA64
> + type_register_static(&hppa64_cpu_type_info);
> +#endif
> }
Preferably switching to DEFINE_TYPES(),
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 67+ messages in thread
* [PATCH 13/61] target/hppa: Make HPPA_BTLB_ENTRIES variable
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (11 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 12/61] target/hppa: Introduce TYPE_HPPA64_CPU Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 14/61] target/hppa: Implement cpu_list Richard Henderson
` (47 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Depend on !HPPACPU.is_pa20.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu.h | 16 ++++++++--------
hw/hppa/machine.c | 6 +-----
target/hppa/cpu.c | 3 +++
target/hppa/mem_helper.c | 41 ++++++++++++++++++++++------------------
4 files changed, 35 insertions(+), 31 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 743fc90e14..22690e351d 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -210,15 +210,15 @@ typedef struct CPUArchState {
target_ureg cr_back[2]; /* back of cr17/cr18 */
target_ureg shadow[7]; /* shadow registers */
- /* ??? The number of entries isn't specified by the architecture. */
-#ifdef TARGET_HPPA64
-#define HPPA_BTLB_FIXED 0 /* BTLBs are not supported in 64-bit machines */
-#else
-#define HPPA_BTLB_FIXED 16
-#endif
-#define HPPA_BTLB_VARIABLE 0
+ /*
+ * ??? The number of entries isn't specified by the architecture.
+ * BTLBs are not supported in 64-bit machines.
+ */
+#define PA10_BTLB_FIXED 16
+#define PA10_BTLB_VARIABLE 0
+#define HPPA_BTLB_ENTRIES(E) (env_archcpu(E)->is_pa20 ? 0 \
+ : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE)
#define HPPA_TLB_ENTRIES 256
-#define HPPA_BTLB_ENTRIES (HPPA_BTLB_FIXED + HPPA_BTLB_VARIABLE)
/* ??? Implement a unified itlb/dtlb for the moment. */
/* ??? We should use a more intelligent data structure. */
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index cf28cb9586..07f8ebeb6a 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -133,7 +133,7 @@ static FWCfgState *create_fw_cfg(MachineState *ms)
fw_cfg_add_file(fw_cfg, "/etc/firmware-min-version",
g_memdup(&val, sizeof(val)), sizeof(val));
- val = cpu_to_le64(HPPA_TLB_ENTRIES - HPPA_BTLB_ENTRIES);
+ val = cpu_to_le64(HPPA_TLB_ENTRIES - HPPA_BTLB_ENTRIES(&cpu[0]->env));
fw_cfg_add_file(fw_cfg, "/etc/cpu/tlb_entries",
g_memdup(&val, sizeof(val)), sizeof(val));
@@ -429,10 +429,6 @@ static void hppa_machine_reset(MachineState *ms, ShutdownCause reason)
cs->exception_index = -1;
cs->halted = 0;
-
- /* clear any existing TLB and BTLB entries */
- memset(cpu[i]->env.tlb, 0, sizeof(cpu[i]->env.tlb));
- cpu[i]->env.tlb_last = HPPA_BTLB_ENTRIES;
}
/* already initialized by machine_hppa_init()? */
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index ed5b6afd10..41abdb04d0 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -139,6 +139,9 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
HPPACPU *cpu = HPPA_CPU(cs);
cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
hppa_cpu_alarm_timer, cpu);
+
+ memset(cpu->env.tlb, 0, sizeof(cpu->env.tlb));
+ cpu->env.tlb_last = HPPA_BTLB_ENTRIES(&cpu->env);
}
#endif
}
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 350485f619..b2a75f6408 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -57,7 +57,7 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent,
HPPA_MMU_FLUSH_MASK, TARGET_LONG_BITS);
/* never clear BTLBs, unless forced to do so. */
- if (ent < &env->tlb[HPPA_BTLB_ENTRIES] && !force_flush_btlb) {
+ if (ent < &env->tlb[HPPA_BTLB_ENTRIES(env)] && !force_flush_btlb) {
return;
}
@@ -68,11 +68,11 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent,
static hppa_tlb_entry *hppa_alloc_tlb_ent(CPUHPPAState *env)
{
hppa_tlb_entry *ent;
- uint32_t i;
+ uint32_t i, btlb_entries = HPPA_BTLB_ENTRIES(env);
- if (env->tlb_last < HPPA_BTLB_ENTRIES || env->tlb_last >= ARRAY_SIZE(env->tlb)) {
- i = HPPA_BTLB_ENTRIES;
- env->tlb_last = HPPA_BTLB_ENTRIES + 1;
+ if (env->tlb_last < btlb_entries || env->tlb_last >= ARRAY_SIZE(env->tlb)) {
+ i = btlb_entries;
+ env->tlb_last = btlb_entries + 1;
} else {
i = env->tlb_last;
env->tlb_last++;
@@ -279,7 +279,7 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
int i;
/* Zap any old entries covering ADDR; notice empty entries on the way. */
- for (i = HPPA_BTLB_ENTRIES; i < ARRAY_SIZE(env->tlb); ++i) {
+ for (i = HPPA_BTLB_ENTRIES(env); i < ARRAY_SIZE(env->tlb); ++i) {
hppa_tlb_entry *ent = &env->tlb[i];
if (ent->va_b <= addr && addr <= ent->va_e) {
if (ent->entry_valid) {
@@ -363,11 +363,13 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr)
number of pages/entries (we choose all), and is local to the cpu. */
void HELPER(ptlbe)(CPUHPPAState *env)
{
+ uint32_t btlb_entries = HPPA_BTLB_ENTRIES(env);
+
trace_hppa_tlb_ptlbe(env);
qemu_log_mask(CPU_LOG_MMU, "FLUSH ALL TLB ENTRIES\n");
- memset(&env->tlb[HPPA_BTLB_ENTRIES], 0,
- sizeof(env->tlb) - HPPA_BTLB_ENTRIES * sizeof(env->tlb[0]));
- env->tlb_last = HPPA_BTLB_ENTRIES;
+ memset(&env->tlb[btlb_entries], 0,
+ sizeof(env->tlb) - btlb_entries * sizeof(env->tlb[0]));
+ env->tlb_last = btlb_entries;
tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
}
@@ -427,13 +429,16 @@ void HELPER(diag_btlb)(CPUHPPAState *env)
hppa_tlb_entry *btlb;
uint64_t virt_page;
uint32_t *vaddr;
+ uint32_t btlb_entries;
-#ifdef TARGET_HPPA64
/* BTLBs are not supported on 64-bit CPUs */
- env->gr[28] = -1; /* nonexistent procedure */
- return;
-#endif
+ if (env_archcpu(env)->is_pa20) {
+ env->gr[28] = -1; /* nonexistent procedure */
+ return;
+ }
+
env->gr[28] = 0; /* PDC_OK */
+ btlb_entries = HPPA_BTLB_ENTRIES(env);
switch (env->gr[25]) {
case 0:
@@ -446,8 +451,8 @@ void HELPER(diag_btlb)(CPUHPPAState *env)
} else {
vaddr[0] = cpu_to_be32(1);
vaddr[1] = cpu_to_be32(16 * 1024);
- vaddr[2] = cpu_to_be32(HPPA_BTLB_FIXED);
- vaddr[3] = cpu_to_be32(HPPA_BTLB_VARIABLE);
+ vaddr[2] = cpu_to_be32(PA10_BTLB_FIXED);
+ vaddr[3] = cpu_to_be32(PA10_BTLB_VARIABLE);
}
break;
case 1:
@@ -464,7 +469,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env)
(long long) virt_page << TARGET_PAGE_BITS,
(long long) (virt_page + len) << TARGET_PAGE_BITS,
(long long) virt_page, phys_page, len, slot);
- if (slot < HPPA_BTLB_ENTRIES) {
+ if (slot < btlb_entries) {
btlb = &env->tlb[slot];
/* force flush of possibly existing BTLB entry */
hppa_flush_tlb_ent(env, btlb, true);
@@ -484,7 +489,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env)
slot = env->gr[22];
qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE slot %d\n",
slot);
- if (slot < HPPA_BTLB_ENTRIES) {
+ if (slot < btlb_entries) {
btlb = &env->tlb[slot];
hppa_flush_tlb_ent(env, btlb, true);
} else {
@@ -494,7 +499,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env)
case 3:
/* Purge all BTLB entries */
qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE_ALL\n");
- for (slot = 0; slot < HPPA_BTLB_ENTRIES; slot++) {
+ for (slot = 0; slot < btlb_entries; slot++) {
btlb = &env->tlb[slot];
hppa_flush_tlb_ent(env, btlb, true);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 14/61] target/hppa: Implement cpu_list
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (12 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 13/61] target/hppa: Make HPPA_BTLB_ENTRIES variable Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 15/61] target/hppa: Implement hppa_cpu_class_by_name Richard Henderson
` (46 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu.h | 5 +++++
target/hppa/cpu.c | 24 ++++++++++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 22690e351d..30010858a9 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -365,4 +365,9 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr);
#endif
G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);
+#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
+
+#define cpu_list hppa_cpu_list
+void hppa_cpu_list(void);
+
#endif /* HPPA_CPU_H */
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 41abdb04d0..1975aa9621 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -162,6 +162,30 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_HPPA_CPU);
}
+static void hppa_cpu_list_entry(gpointer data, gpointer user_data)
+{
+ ObjectClass *oc = data;
+ CPUClass *cc = CPU_CLASS(oc);
+ const char *tname = object_class_get_name(oc);
+ g_autofree char *name = g_strndup(tname, strchr(tname, '-') - tname);
+
+ if (cc->deprecation_note) {
+ qemu_printf(" %s (deprecated)\n", name);
+ } else {
+ qemu_printf(" %s\n", name);
+ }
+}
+
+void hppa_cpu_list(void)
+{
+ GSList *list;
+
+ list = object_class_get_list_sorted(TYPE_HPPA_CPU, false);
+ qemu_printf("Available CPUs:\n");
+ g_slist_foreach(list, hppa_cpu_list_entry, NULL);
+ g_slist_free(list);
+}
+
#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 15/61] target/hppa: Implement hppa_cpu_class_by_name
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (13 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 14/61] target/hppa: Implement cpu_list Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 16/61] target/hppa: Update cpu_hppa_get/put_psw for hppa64 Richard Henderson
` (45 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/hppa/target_elf.h | 2 +-
target/hppa/cpu.c | 10 +++++++++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/linux-user/hppa/target_elf.h b/linux-user/hppa/target_elf.h
index 82b4e9535e..9bb865ae92 100644
--- a/linux-user/hppa/target_elf.h
+++ b/linux-user/hppa/target_elf.h
@@ -9,6 +9,6 @@
#define HPPA_TARGET_ELF_H
static inline const char *cpu_get_model(uint32_t eflags)
{
- return "any";
+ return TYPE_HPPA_CPU;
}
#endif
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 1975aa9621..6bf415139f 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -159,7 +159,15 @@ static void hppa_cpu_initfn(Object *obj)
static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
{
- return object_class_by_name(TYPE_HPPA_CPU);
+ g_autofree char *typename = g_strconcat(cpu_model, "-cpu", NULL);
+ ObjectClass *oc = object_class_by_name(typename);
+
+ if (oc &&
+ !object_class_is_abstract(oc) &&
+ object_class_dynamic_cast(oc, TYPE_HPPA_CPU)) {
+ return oc;
+ }
+ return NULL;
}
static void hppa_cpu_list_entry(gpointer data, gpointer user_data)
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 16/61] target/hppa: Update cpu_hppa_get/put_psw for hppa64
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (14 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 15/61] target/hppa: Implement hppa_cpu_class_by_name Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 17/61] target/hppa: Handle absolute addresses for pa2.0 Richard Henderson
` (44 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
With 64-bit registers, there are 16 carry bits in the PSW.
Clear reserved bits based on cpu revision.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/helper.c | 63 ++++++++++++++++++++++++++++++++++++--------
1 file changed, 52 insertions(+), 11 deletions(-)
diff --git a/target/hppa/helper.c b/target/hppa/helper.c
index a8d3f456ee..40e859ba08 100644
--- a/target/hppa/helper.c
+++ b/target/hppa/helper.c
@@ -28,19 +28,35 @@
target_ureg cpu_hppa_get_psw(CPUHPPAState *env)
{
target_ureg psw;
+ target_ureg mask1 = (target_ureg)-1 / 0xf;
+ target_ureg maskf = (target_ureg)-1 / 0xffff * 0xf;
/* Fold carry bits down to 8 consecutive bits. */
- /* ??? Needs tweaking for hppa64. */
- /* .......b...c...d...e...f...g...h */
- psw = (env->psw_cb >> 4) & 0x01111111;
- /* .......b..bc..cd..de..ef..fg..gh */
+ /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^i^^^j^^^k^^^l^^^m^^^n^^^o^^^p^^^^ */
+ /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^^ */
+ psw = (env->psw_cb >> 4) & mask1;
+ /* .......b...c...d...e...f...g...h...i...j...k...l...m...n...o...p */
+ /* .......b...c...d...e...f...g...h */
psw |= psw >> 3;
- /* .............bcd............efgh */
- psw |= (psw >> 6) & 0x000f000f;
- /* .........................bcdefgh */
- psw |= (psw >> 12) & 0xf;
- psw |= env->psw_cb_msb << 7;
- psw = (psw & 0xff) << 8;
+ /* .......b..bc..cd..de..ef..fg..gh..hi..ij..jk..kl..lm..mn..no..op */
+ /* .......b..bc..cd..de..ef..fg..gh */
+ psw |= psw >> 6;
+ psw &= maskf;
+ /* .............bcd............efgh............ijkl............mnop */
+ /* .............bcd............efgh */
+ psw |= psw >> 12;
+ /* .............bcd.........bcdefgh........efghijkl........ijklmnop */
+ /* .............bcd.........bcdefgh */
+ psw |= env->psw_cb_msb << (TARGET_REGISTER_BITS == 64 ? 39 : 7);
+ /* .............bcd........abcdefgh........efghijkl........ijklmnop */
+ /* .............bcd........abcdefgh */
+
+ /* For hppa64, the two 8-bit fields are discontiguous. */
+ if (env_archcpu(env)->is_pa20) {
+ psw = (psw & 0xff00000000ull) | ((psw & 0xff) << 8);
+ } else {
+ psw = (psw & 0xff) << 8;
+ }
psw |= env->psw_n * PSW_N;
psw |= (env->psw_v < 0) * PSW_V;
@@ -51,14 +67,39 @@ target_ureg cpu_hppa_get_psw(CPUHPPAState *env)
void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
{
+ uint64_t reserved;
target_ureg old_psw = env->psw;
target_ureg cb = 0;
+ /* Do not allow reserved bits to be set. */
+ if (env_archcpu(env)->is_pa20) {
+ reserved = MAKE_64BIT_MASK(40, 24) | MAKE_64BIT_MASK(28, 4);
+ reserved |= PSW_G; /* PA1.x only */
+ reserved |= PSW_E; /* not implemented */
+ } else {
+ reserved = MAKE_64BIT_MASK(32, 32) | MAKE_64BIT_MASK(28, 2);
+ reserved |= PSW_O | PSW_W; /* PA2.0 only */
+ reserved |= PSW_E | PSW_Y | PSW_Z; /* not implemented */
+ }
+ psw &= ~reserved;
+
env->psw = psw & ~(PSW_N | PSW_V | PSW_CB);
env->psw_n = (psw / PSW_N) & 1;
env->psw_v = -((psw / PSW_V) & 1);
- env->psw_cb_msb = (psw >> 15) & 1;
+#if TARGET_REGISTER_BITS == 32
+ env->psw_cb_msb = (psw >> 15) & 1;
+#else
+ env->psw_cb_msb = (psw >> 39) & 1;
+ cb |= ((psw >> 38) & 1) << 60;
+ cb |= ((psw >> 37) & 1) << 56;
+ cb |= ((psw >> 36) & 1) << 52;
+ cb |= ((psw >> 35) & 1) << 48;
+ cb |= ((psw >> 34) & 1) << 44;
+ cb |= ((psw >> 33) & 1) << 40;
+ cb |= ((psw >> 32) & 1) << 36;
+ cb |= ((psw >> 15) & 1) << 32;
+#endif
cb |= ((psw >> 14) & 1) << 28;
cb |= ((psw >> 13) & 1) << 24;
cb |= ((psw >> 12) & 1) << 20;
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 17/61] target/hppa: Handle absolute addresses for pa2.0
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (15 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 16/61] target/hppa: Update cpu_hppa_get/put_psw for hppa64 Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 18/61] target/hppa: Adjust hppa_cpu_dump_state for hppa64 Richard Henderson
` (43 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
With pa2.0, absolute addresses are not the same as physical addresses,
and undergo a transformation based on PSW_W.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu.h | 3 +++
target/hppa/helper.c | 4 ++--
target/hppa/mem_helper.c | 47 ++++++++++++++++++++++++++++++++++++++--
target/hppa/sys_helper.c | 9 ++++++++
4 files changed, 59 insertions(+), 4 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 30010858a9..671e43ebd8 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -283,6 +283,9 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
return hppa_form_gva_psw(env->psw, spc, off);
}
+hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr);
+hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr);
+
/*
* Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
* TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
diff --git a/target/hppa/helper.c b/target/hppa/helper.c
index 40e859ba08..0ef890184a 100644
--- a/target/hppa/helper.c
+++ b/target/hppa/helper.c
@@ -109,8 +109,8 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
cb |= ((psw >> 8) & 1) << 4;
env->psw_cb = cb;
- /* If PSW_P changes, it affects how we translate addresses. */
- if ((psw ^ old_psw) & PSW_P) {
+ /* If P or W changes, it affects how we translate addresses. */
+ if ((psw ^ old_psw) & (PSW_P | PSW_W)) {
#ifndef CONFIG_USER_ONLY
tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
#endif
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index b2a75f6408..169e878479 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -25,6 +25,45 @@
#include "hw/core/cpu.h"
#include "trace.h"
+hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr)
+{
+ if (likely(extract64(addr, 58, 4) != 0xf)) {
+ /* Memory address space */
+ return addr & MAKE_64BIT_MASK(0, 62);
+ }
+ if (extract64(addr, 54, 4) != 0) {
+ /* I/O address space */
+ return addr | MAKE_64BIT_MASK(62, 2);
+ }
+ /* PDC address space */
+ return (addr & MAKE_64BIT_MASK(0, 54)) | MAKE_64BIT_MASK(60, 4);
+}
+
+hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr)
+{
+ if (likely(extract32(addr, 28, 4) != 0xf)) {
+ /* Memory address space */
+ return addr & MAKE_64BIT_MASK(0, 32);
+ }
+ if (extract32(addr, 24, 4) != 0) {
+ /* I/O address space */
+ return addr | MAKE_64BIT_MASK(32, 32);
+ }
+ /* PDC address space */
+ return (addr & MAKE_64BIT_MASK(0, 24)) | MAKE_64BIT_MASK(60, 4);
+}
+
+static hwaddr hppa_abs_to_phys(CPUHPPAState *env, vaddr addr)
+{
+ if (!env_archcpu(env)->is_pa20) {
+ return addr;
+ } else if (env->psw & PSW_W) {
+ return hppa_abs_to_phys_pa2_w1(addr);
+ } else {
+ return hppa_abs_to_phys_pa2_w0(addr);
+ }
+}
+
static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr)
{
int i;
@@ -99,7 +138,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
/* Virtual translation disabled. Direct map virtual to physical. */
if (mmu_idx == MMU_PHYS_IDX) {
- phys = addr;
+ phys = hppa_abs_to_phys(env, addr);
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
goto egress;
}
@@ -299,7 +338,11 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
/* Note that empty->entry_valid == 0 already. */
empty->va_b = addr & TARGET_PAGE_MASK;
empty->va_e = empty->va_b + TARGET_PAGE_SIZE - 1;
- empty->pa = extract32(reg, 5, 20) << TARGET_PAGE_BITS;
+ /*
+ * FIXME: This is wrong, as this is a pa1.1 function.
+ * But for the moment translate abs address for pa2.0.
+ */
+ empty->pa = hppa_abs_to_phys(env, extract32(reg, 5, 20) << TARGET_PAGE_BITS);
trace_hppa_tlb_itlba(env, empty, empty->va_b, empty->va_e, empty->pa);
}
diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c
index 4bb4cf611c..f0dd5a08e7 100644
--- a/target/hppa/sys_helper.c
+++ b/target/hppa/sys_helper.c
@@ -71,6 +71,15 @@ target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm)
* so let this go without comment.
*/
env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM);
+
+ /*
+ * Changes to PSW_W change the translation of absolute to physical.
+ * This currently (incorrectly) affects all translations.
+ */
+ if ((psw ^ env->psw) & (PSW_P | PSW_W)) {
+ tlb_flush(env_cpu(env));
+ }
+
return psw & PSW_SM;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 18/61] target/hppa: Adjust hppa_cpu_dump_state for hppa64
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (16 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 17/61] target/hppa: Handle absolute addresses for pa2.0 Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 19/61] hw/hppa: Translate phys addresses for the cpu Richard Henderson
` (42 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Dump all 64 bits for pa2.0 and low 32 bits for pa1.x.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/helper.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/hppa/helper.c b/target/hppa/helper.c
index 0ef890184a..04cdbafe9d 100644
--- a/target/hppa/helper.c
+++ b/target/hppa/helper.c
@@ -124,13 +124,17 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
target_ureg psw = cpu_hppa_get_psw(env);
target_ureg psw_cb;
char psw_c[20];
- int i;
+ int i, w;
+ uint64_t m;
+
+ w = cpu->is_pa20 ? 16 : 8;
+ m = cpu->is_pa20 ? UINT64_MAX : UINT32_MAX;
qemu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx
- " IIR " TREG_FMT_lx "\n",
+ " IIR %0*" PRIx64 "\n",
hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f),
hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b),
- env->cr[CR_IIR]);
+ w, m & env->cr[CR_IIR]);
psw_c[0] = (psw & PSW_W ? 'W' : '-');
psw_c[1] = (psw & PSW_E ? 'E' : '-');
@@ -151,13 +155,15 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
psw_c[16] = (psw & PSW_D ? 'D' : '-');
psw_c[17] = (psw & PSW_I ? 'I' : '-');
psw_c[18] = '\0';
- psw_cb = ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28);
+ psw_cb = ((env->psw_cb >> 4) & ((target_ureg)-1 / 0xf))
+ | (env->psw_cb_msb << (TARGET_REGISTER_BITS - 4));
- qemu_fprintf(f, "PSW " TREG_FMT_lx " CB " TREG_FMT_lx " %s\n",
- psw, psw_cb, psw_c);
+ qemu_fprintf(f, "PSW %0*" PRIx64 " CB %0*" PRIx64 " %s\n",
+ w, m & psw, w, m & psw_cb, psw_c);
for (i = 0; i < 32; i++) {
- qemu_fprintf(f, "GR%02d " TREG_FMT_lx "%c", i, env->gr[i],
+ qemu_fprintf(f, "GR%02d %0*" PRIx64 "%c",
+ i, w, m & env->gr[i],
(i & 3) == 3 ? '\n' : ' ');
}
#ifndef CONFIG_USER_ONLY
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 19/61] hw/hppa: Translate phys addresses for the cpu
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (17 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 18/61] target/hppa: Adjust hppa_cpu_dump_state for hppa64 Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 20/61] target/hppa: Fix hppa64 addressing Richard Henderson
` (41 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Hack the machine to use pa2.0 physical layout when required,
using the PSW.W=0 absolute to physical mapping.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/hppa/machine.c | 87 ++++++++++++++++++++++++++++-------------------
1 file changed, 52 insertions(+), 35 deletions(-)
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index 07f8ebeb6a..765f338544 100644
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -81,7 +81,7 @@ static const MemoryRegionOps hppa_pci_ignore_ops = {
},
};
-static ISABus *hppa_isa_bus(void)
+static ISABus *hppa_isa_bus(hwaddr addr)
{
ISABus *isa_bus;
qemu_irq *isa_irqs;
@@ -90,8 +90,7 @@ static ISABus *hppa_isa_bus(void)
isa_region = g_new(MemoryRegion, 1);
memory_region_init_io(isa_region, NULL, &hppa_pci_ignore_ops,
NULL, "isa-io", 0x800);
- memory_region_add_subregion(get_system_memory(), IDE_HPA,
- isa_region);
+ memory_region_add_subregion(get_system_memory(), addr, isa_region);
isa_bus = isa_bus_new(NULL, get_system_memory(), isa_region,
&error_abort);
@@ -103,7 +102,7 @@ static ISABus *hppa_isa_bus(void)
return isa_bus;
}
-static uint64_t cpu_hppa_to_phys(void *opaque, uint64_t addr)
+static uint64_t linux_kernel_virt_to_phys(void *opaque, uint64_t addr)
{
addr &= (0x10000000 - 1);
return addr;
@@ -118,13 +117,13 @@ static void fw_cfg_boot_set(void *opaque, const char *boot_device,
fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
}
-static FWCfgState *create_fw_cfg(MachineState *ms)
+static FWCfgState *create_fw_cfg(MachineState *ms, hwaddr addr)
{
FWCfgState *fw_cfg;
uint64_t val;
const char qemu_version[] = QEMU_VERSION;
- fw_cfg = fw_cfg_init_mem(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4);
+ fw_cfg = fw_cfg_init_mem(addr, addr + 4);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, ms->smp.cpus);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, HPPA_MAX_CPUS);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ms->ram_size);
@@ -173,6 +172,16 @@ static DinoState *dino_init(MemoryRegion *addr_space)
return DINO_PCI_HOST_BRIDGE(dev);
}
+static uint64_t translate_pa10(void *dummy, uint64_t addr)
+{
+ return (uint32_t)addr;
+}
+
+static uint64_t translate_pa20(void *dummy, uint64_t addr)
+{
+ return hppa_abs_to_phys_pa2_w0(addr);
+}
+
static void machine_hppa_init(MachineState *machine)
{
const char *kernel_filename = machine->kernel_filename;
@@ -188,20 +197,33 @@ static void machine_hppa_init(MachineState *machine)
uint64_t kernel_entry = 0, kernel_low, kernel_high;
MemoryRegion *addr_space = get_system_memory();
MemoryRegion *rom_region;
- MemoryRegion *cpu_region;
long i;
unsigned int smp_cpus = machine->smp.cpus;
SysBusDevice *s;
+ uint64_t (*translate)(void *, uint64_t);
/* Create CPUs. */
for (i = 0; i < smp_cpus; i++) {
- char *name = g_strdup_printf("cpu%ld-io-eir", i);
cpu[i] = HPPA_CPU(cpu_create(machine->cpu_type));
+ }
- cpu_region = g_new(MemoryRegion, 1);
+ /*
+ * For now, treat address layout as if PSW_W is clear.
+ * TODO: create a proper hppa64 board model and load elf64 firmware.
+ */
+ if (cpu[0]->is_pa20) {
+ translate = translate_pa20;
+ } else {
+ translate = translate_pa10;
+ }
+
+ for (i = 0; i < smp_cpus; i++) {
+ char *name = g_strdup_printf("cpu%ld-io-eir", i);
+ MemoryRegion *cpu_region = g_new(MemoryRegion, 1);
memory_region_init_io(cpu_region, OBJECT(cpu[i]), &hppa_io_eir_ops,
cpu[i], name, 4);
- memory_region_add_subregion(addr_space, CPU_HPA + i * 0x1000,
+ memory_region_add_subregion(addr_space,
+ translate(NULL, CPU_HPA + i * 0x1000),
cpu_region);
g_free(name);
}
@@ -216,41 +238,41 @@ static void machine_hppa_init(MachineState *machine)
/* Init Lasi chip */
lasi_dev = DEVICE(lasi_init());
- memory_region_add_subregion(addr_space, LASI_HPA,
+ memory_region_add_subregion(addr_space, translate(NULL, LASI_HPA),
sysbus_mmio_get_region(
SYS_BUS_DEVICE(lasi_dev), 0));
/* Init Dino (PCI host bus chip). */
dino_dev = DEVICE(dino_init(addr_space));
- memory_region_add_subregion(addr_space, DINO_HPA,
+ memory_region_add_subregion(addr_space, translate(NULL, DINO_HPA),
sysbus_mmio_get_region(
SYS_BUS_DEVICE(dino_dev), 0));
pci_bus = PCI_BUS(qdev_get_child_bus(dino_dev, "pci"));
assert(pci_bus);
/* Create ISA bus. */
- isa_bus = hppa_isa_bus();
+ isa_bus = hppa_isa_bus(translate(NULL, IDE_HPA));
assert(isa_bus);
/* Realtime clock, used by firmware for PDC_TOD call. */
mc146818_rtc_init(isa_bus, 2000, NULL);
/* Serial ports: Lasi and Dino use a 7.272727 MHz clock. */
- serial_mm_init(addr_space, LASI_UART_HPA + 0x800, 0,
+ serial_mm_init(addr_space, translate(NULL, LASI_UART_HPA + 0x800), 0,
qdev_get_gpio_in(lasi_dev, LASI_IRQ_UART_HPA), 7272727 / 16,
serial_hd(0), DEVICE_BIG_ENDIAN);
- serial_mm_init(addr_space, DINO_UART_HPA + 0x800, 0,
+ serial_mm_init(addr_space, translate(NULL, DINO_UART_HPA + 0x800), 0,
qdev_get_gpio_in(dino_dev, DINO_IRQ_RS232INT), 7272727 / 16,
serial_hd(1), DEVICE_BIG_ENDIAN);
/* Parallel port */
- parallel_mm_init(addr_space, LASI_LPT_HPA + 0x800, 0,
+ parallel_mm_init(addr_space, translate(NULL, LASI_LPT_HPA + 0x800), 0,
qdev_get_gpio_in(lasi_dev, LASI_IRQ_LAN_HPA),
parallel_hds[0]);
/* fw_cfg configuration interface */
- create_fw_cfg(machine);
+ create_fw_cfg(machine, translate(NULL, FW_CFG_IO_BASE));
/* SCSI disk setup. */
dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a"));
@@ -262,13 +284,13 @@ static void machine_hppa_init(MachineState *machine)
dev = qdev_new("artist");
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
- sysbus_mmio_map(s, 0, LASI_GFX_HPA);
- sysbus_mmio_map(s, 1, ARTIST_FB_ADDR);
+ sysbus_mmio_map(s, 0, translate(NULL, LASI_GFX_HPA));
+ sysbus_mmio_map(s, 1, translate(NULL, ARTIST_FB_ADDR));
}
/* Network setup. */
if (enable_lasi_lan()) {
- lasi_82596_init(addr_space, LASI_LAN_HPA,
+ lasi_82596_init(addr_space, translate(NULL, LASI_LAN_HPA),
qdev_get_gpio_in(lasi_dev, LASI_IRQ_LAN_HPA));
}
@@ -283,10 +305,11 @@ static void machine_hppa_init(MachineState *machine)
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
qdev_get_gpio_in(lasi_dev, LASI_IRQ_PS2KBD_HPA));
- memory_region_add_subregion(addr_space, LASI_PS2KBD_HPA,
+ memory_region_add_subregion(addr_space, translate(NULL, LASI_PS2KBD_HPA),
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
0));
- memory_region_add_subregion(addr_space, LASI_PS2KBD_HPA + 0x100,
+ memory_region_add_subregion(addr_space,
+ translate(NULL, LASI_PS2KBD_HPA + 0x100),
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1));
@@ -303,15 +326,10 @@ static void machine_hppa_init(MachineState *machine)
exit(1);
}
- size = load_elf(firmware_filename, NULL, NULL, NULL,
+ size = load_elf(firmware_filename, NULL, translate, NULL,
&firmware_entry, &firmware_low, &firmware_high, NULL,
true, EM_PARISC, 0, 0);
- /* Unfortunately, load_elf sign-extends reading elf32. */
- firmware_entry = (target_ureg)firmware_entry;
- firmware_low = (target_ureg)firmware_low;
- firmware_high = (target_ureg)firmware_high;
-
if (size < 0) {
error_report("could not load firmware '%s'", firmware_filename);
exit(1);
@@ -319,7 +337,8 @@ static void machine_hppa_init(MachineState *machine)
qemu_log_mask(CPU_LOG_PAGE, "Firmware loaded at 0x%08" PRIx64
"-0x%08" PRIx64 ", entry at 0x%08" PRIx64 ".\n",
firmware_low, firmware_high, firmware_entry);
- if (firmware_low < FIRMWARE_START || firmware_high >= FIRMWARE_END) {
+ if (firmware_low < translate(NULL, FIRMWARE_START) ||
+ firmware_high >= translate(NULL, FIRMWARE_END)) {
error_report("Firmware overlaps with memory or IO space");
exit(1);
}
@@ -328,18 +347,16 @@ static void machine_hppa_init(MachineState *machine)
rom_region = g_new(MemoryRegion, 1);
memory_region_init_ram(rom_region, NULL, "firmware",
(FIRMWARE_END - FIRMWARE_START), &error_fatal);
- memory_region_add_subregion(addr_space, FIRMWARE_START, rom_region);
+ memory_region_add_subregion(addr_space,
+ translate(NULL, FIRMWARE_START), rom_region);
/* Load kernel */
if (kernel_filename) {
- size = load_elf(kernel_filename, NULL, &cpu_hppa_to_phys,
+ size = load_elf(kernel_filename, NULL, linux_kernel_virt_to_phys,
NULL, &kernel_entry, &kernel_low, &kernel_high, NULL,
true, EM_PARISC, 0, 0);
- /* Unfortunately, load_elf sign-extends reading elf32. */
- kernel_entry = (target_ureg) cpu_hppa_to_phys(NULL, kernel_entry);
- kernel_low = (target_ureg)kernel_low;
- kernel_high = (target_ureg)kernel_high;
+ kernel_entry = linux_kernel_virt_to_phys(NULL, kernel_entry);
if (size < 0) {
error_report("could not load kernel '%s'", kernel_filename);
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 20/61] target/hppa: Fix hppa64 addressing
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (18 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 19/61] hw/hppa: Translate phys addresses for the cpu Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 21/61] target/hppa: sar register allows only 5 bits on 32-bit CPU Richard Henderson
` (40 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0.
In space_select, the bits that choose the space depend on PSW_W.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu.h | 7 +++----
target/hppa/translate.c | 22 +++++++++++++---------
2 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 671e43ebd8..1a12b2a186 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -272,7 +272,7 @@ static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
#ifdef CONFIG_USER_ONLY
return off;
#else
- off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull);
+ off &= psw & PSW_W ? MAKE_64BIT_MASK(0, 62) : MAKE_64BIT_MASK(0, 32);
return spc | off;
#endif
}
@@ -313,9 +313,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
flags |= env->psw & (PSW_W | PSW_C | PSW_D);
flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
- *pc = (env->psw & PSW_C
- ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4)
- : env->iaoq_f & -4);
+ *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0),
+ env->iaoq_f & -4);
*cs_base = env->iasq_f;
/* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 9d6670f91c..ace6fb0ab2 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -764,6 +764,13 @@ static bool gen_illegal(DisasContext *ctx)
} while (0)
#endif
+static target_ureg gva_offset_mask(DisasContext *ctx)
+{
+ return (ctx->tb_flags & PSW_W
+ ? MAKE_64BIT_MASK(0, 62)
+ : MAKE_64BIT_MASK(0, 32));
+}
+
static bool use_goto_tb(DisasContext *ctx, target_ureg dest)
{
return translator_use_goto_tb(&ctx->base, dest);
@@ -1398,7 +1405,8 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base)
tmp = tcg_temp_new();
spc = tcg_temp_new_tl();
- tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5);
+ /* Extract top 2 bits of the address, shift left 3 for uint64_t index. */
+ tcg_gen_shri_reg(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5);
tcg_gen_andi_reg(tmp, tmp, 030);
tcg_gen_trunc_reg_ptr(ptr, tmp);
@@ -1415,6 +1423,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs,
{
TCGv_reg base = load_gpr(ctx, rb);
TCGv_reg ofs;
+ TCGv_tl addr;
/* Note that RX is mutually exclusive with DISP. */
if (rx) {
@@ -1429,18 +1438,13 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs,
}
*pofs = ofs;
-#ifdef CONFIG_USER_ONLY
- *pgva = (modify <= 0 ? ofs : base);
-#else
- TCGv_tl addr = tcg_temp_new_tl();
+ *pgva = addr = tcg_temp_new_tl();
tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base);
- if (ctx->tb_flags & PSW_W) {
- tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull);
- }
+ tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx));
+#ifndef CONFIG_USER_ONLY
if (!is_phys) {
tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base));
}
- *pgva = addr;
#endif
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 21/61] target/hppa: sar register allows only 5 bits on 32-bit CPU
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (19 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 20/61] target/hppa: Fix hppa64 addressing Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 22/61] target/hppa: Pass d to do_cond Richard Henderson
` (39 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
From: Helge Deller <deller@gmx.de>
The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.
The interesting part is, that this register allows to detect at runtime
if a physical CPU is capable to execute PA2.0 (64-bit) instructions.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/hppa/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index ace6fb0ab2..e2b692a6c5 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2155,7 +2155,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
if (ctl == CR_SAR) {
reg = load_gpr(ctx, a->r);
tmp = tcg_temp_new();
- tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1);
+ tcg_gen_andi_reg(tmp, reg, ctx->is_pa20 ? 63 : 31);
save_or_nullify(ctx, cpu_sar, tmp);
cond_free(&ctx->null_cond);
@@ -2216,7 +2216,7 @@ static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a)
TCGv_reg tmp = tcg_temp_new();
tcg_gen_not_reg(tmp, load_gpr(ctx, a->r));
- tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1);
+ tcg_gen_andi_reg(tmp, tmp, ctx->is_pa20 ? 63 : 31);
save_or_nullify(ctx, cpu_sar, tmp);
cond_free(&ctx->null_cond);
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 22/61] target/hppa: Pass d to do_cond
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (20 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 21/61] target/hppa: sar register allows only 5 bits on 32-bit CPU Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 23/61] target/hppa: Pass d to do_sub_cond Richard Henderson
` (38 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Hoist the resolution of d up one level above do_cond.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 82 +++++++++++++++++++++++++++--------------
1 file changed, 54 insertions(+), 28 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index e2b692a6c5..d6edad9adb 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -814,7 +814,7 @@ static bool cond_need_cb(int c)
/* Need extensions from TCGv_i32 to TCGv_reg. */
static bool cond_need_ext(DisasContext *ctx, bool d)
{
- return TARGET_REGISTER_BITS == 64 && !d;
+ return TARGET_REGISTER_BITS == 64 && !(ctx->is_pa20 && d);
}
/*
@@ -822,8 +822,8 @@ static bool cond_need_ext(DisasContext *ctx, bool d)
* the Parisc 1.1 Architecture Reference Manual for details.
*/
-static DisasCond do_cond(unsigned cf, TCGv_reg res,
- TCGv_reg cb_msb, TCGv_reg sv)
+static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
+ TCGv_reg res, TCGv_reg cb_msb, TCGv_reg sv)
{
DisasCond cond;
TCGv_reg tmp;
@@ -833,11 +833,19 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res,
cond = cond_make_f();
break;
case 1: /* = / <> (Z / !Z) */
+ if (cond_need_ext(ctx, d)) {
+ tmp = tcg_temp_new();
+ tcg_gen_ext32u_reg(tmp, res);
+ res = tmp;
+ }
cond = cond_make_0(TCG_COND_EQ, res);
break;
case 2: /* < / >= (N ^ V / !(N ^ V) */
tmp = tcg_temp_new();
tcg_gen_xor_reg(tmp, res, sv);
+ if (cond_need_ext(ctx, d)) {
+ tcg_gen_ext32s_reg(tmp, tmp);
+ }
cond = cond_make_0_tmp(TCG_COND_LT, tmp);
break;
case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
@@ -852,20 +860,35 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res,
*/
tmp = tcg_temp_new();
tcg_gen_eqv_reg(tmp, res, sv);
- tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1);
- tcg_gen_and_reg(tmp, tmp, res);
+ if (cond_need_ext(ctx, d)) {
+ tcg_gen_sextract_reg(tmp, tmp, 31, 1);
+ tcg_gen_and_reg(tmp, tmp, res);
+ tcg_gen_ext32u_reg(tmp, tmp);
+ } else {
+ tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1);
+ tcg_gen_and_reg(tmp, tmp, res);
+ }
cond = cond_make_0_tmp(TCG_COND_EQ, tmp);
break;
case 4: /* NUV / UV (!C / C) */
+ /* Only bit 0 of cb_msb is ever set. */
cond = cond_make_0(TCG_COND_EQ, cb_msb);
break;
case 5: /* ZNV / VNZ (!C | Z / C & !Z) */
tmp = tcg_temp_new();
tcg_gen_neg_reg(tmp, cb_msb);
tcg_gen_and_reg(tmp, tmp, res);
+ if (cond_need_ext(ctx, d)) {
+ tcg_gen_ext32u_reg(tmp, tmp);
+ }
cond = cond_make_0_tmp(TCG_COND_EQ, tmp);
break;
case 6: /* SV / NSV (V / !V) */
+ if (cond_need_ext(ctx, d)) {
+ tmp = tcg_temp_new();
+ tcg_gen_ext32s_reg(tmp, sv);
+ sv = tmp;
+ }
cond = cond_make_0(TCG_COND_LT, sv);
break;
case 7: /* OD / EV */
@@ -887,10 +910,11 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res,
can use the inputs directly. This can allow other computation to be
deleted as unused. */
-static DisasCond do_sub_cond(unsigned cf, TCGv_reg res,
+static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, TCGv_reg res,
TCGv_reg in1, TCGv_reg in2, TCGv_reg sv)
{
DisasCond cond;
+ bool d = false;
switch (cf >> 1) {
case 1: /* = / <> */
@@ -909,7 +933,7 @@ static DisasCond do_sub_cond(unsigned cf, TCGv_reg res,
cond = cond_make(TCG_COND_LEU, in1, in2);
break;
default:
- return do_cond(cf, res, NULL, sv);
+ return do_cond(ctx, cf, d, res, NULL, sv);
}
if (cf & 1) {
cond.c = tcg_invert_cond(cond.c);
@@ -927,8 +951,10 @@ static DisasCond do_sub_cond(unsigned cf, TCGv_reg res,
* how cases c={2,3} are treated.
*/
-static DisasCond do_log_cond(unsigned cf, TCGv_reg res)
+static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, TCGv_reg res)
{
+ bool d = false;
+
switch (cf) {
case 0: /* never */
case 9: /* undef, C */
@@ -957,7 +983,7 @@ static DisasCond do_log_cond(unsigned cf, TCGv_reg res)
case 14: /* OD */
case 15: /* EV */
- return do_cond(cf, res, NULL, NULL);
+ return do_cond(ctx, cf, d, res, NULL, NULL);
default:
g_assert_not_reached();
@@ -966,7 +992,7 @@ static DisasCond do_log_cond(unsigned cf, TCGv_reg res)
/* Similar, but for shift/extract/deposit conditions. */
-static DisasCond do_sed_cond(unsigned orig, TCGv_reg res)
+static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, TCGv_reg res)
{
unsigned c, f;
@@ -979,7 +1005,7 @@ static DisasCond do_sed_cond(unsigned orig, TCGv_reg res)
}
f = (orig & 4) / 4;
- return do_log_cond(c * 2 + f, res);
+ return do_log_cond(ctx, c * 2 + f, res);
}
/* Similar, but for unit conditions. */
@@ -1151,7 +1177,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
}
/* Emit any conditional trap before any writeback. */
- cond = do_cond(cf, dest, cb_cond, sv);
+ cond = do_cond(ctx, cf, d, dest, cb_cond, sv);
if (is_tc) {
tmp = tcg_temp_new();
tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
@@ -1241,9 +1267,9 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
/* Compute the condition. We cannot use the special case for borrow. */
if (!is_b) {
- cond = do_sub_cond(cf, dest, in1, in2, sv);
+ cond = do_sub_cond(ctx, cf, dest, in1, in2, sv);
} else {
- cond = do_cond(cf, dest, get_carry(ctx, d, cb, cb_msb), sv);
+ cond = do_cond(ctx, cf, d, dest, get_carry(ctx, d, cb, cb_msb), sv);
}
/* Emit any conditional trap before any writeback. */
@@ -1306,7 +1332,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1,
}
/* Form the condition for the compare. */
- cond = do_sub_cond(cf, dest, in1, in2, sv);
+ cond = do_sub_cond(ctx, cf, dest, in1, in2, sv);
/* Clear. */
tcg_gen_movi_reg(dest, 0);
@@ -1330,7 +1356,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1,
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (cf) {
- ctx->null_cond = do_log_cond(cf, dest);
+ ctx->null_cond = do_log_cond(ctx, cf, dest);
}
}
@@ -2796,7 +2822,7 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
/* ??? The lshift is supposed to contribute to overflow. */
sv = do_add_sv(ctx, dest, add1, add2);
}
- ctx->null_cond = do_cond(a->cf, dest, cout, sv);
+ ctx->null_cond = do_cond(ctx, a->cf, false, dest, cout, sv);
}
return nullify_end(ctx);
@@ -3013,7 +3039,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1,
sv = do_sub_sv(ctx, dest, in1, in2);
}
- cond = do_sub_cond(c * 2 + f, dest, in1, in2, sv);
+ cond = do_sub_cond(ctx, c * 2 + f, dest, in1, in2, sv);
return do_cbranch(ctx, disp, n, &cond);
}
@@ -3057,7 +3083,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1,
sv = do_add_sv(ctx, dest, in1, in2);
}
- cond = do_cond(c * 2 + f, dest, cb_cond, sv);
+ cond = do_cond(ctx, c * 2 + f, d, dest, cb_cond, sv);
save_gpr(ctx, r, dest);
return do_cbranch(ctx, disp, n, &cond);
}
@@ -3128,7 +3154,7 @@ static bool trans_movb(DisasContext *ctx, arg_movb *a)
tcg_gen_mov_reg(dest, cpu_gr[a->r1]);
}
- cond = do_sed_cond(a->c, dest);
+ cond = do_sed_cond(ctx, a->c, dest);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
@@ -3142,7 +3168,7 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi *a)
dest = dest_gpr(ctx, a->r);
tcg_gen_movi_reg(dest, a->i);
- cond = do_sed_cond(a->c, dest);
+ cond = do_sed_cond(ctx, a->c, dest);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
@@ -3180,7 +3206,7 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, dest);
}
return nullify_end(ctx);
}
@@ -3216,7 +3242,7 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, dest);
}
return nullify_end(ctx);
}
@@ -3250,7 +3276,7 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, dest);
}
return nullify_end(ctx);
}
@@ -3277,7 +3303,7 @@ static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, dest);
}
return nullify_end(ctx);
}
@@ -3314,7 +3340,7 @@ static bool trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, dest);
}
return nullify_end(ctx);
}
@@ -3344,7 +3370,7 @@ static bool trans_depw_imm(DisasContext *ctx, arg_depw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, dest);
}
return nullify_end(ctx);
}
@@ -3381,7 +3407,7 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c,
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (c) {
- ctx->null_cond = do_sed_cond(c, dest);
+ ctx->null_cond = do_sed_cond(ctx, c, dest);
}
return nullify_end(ctx);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 23/61] target/hppa: Pass d to do_sub_cond
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (21 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 22/61] target/hppa: Pass d to do_cond Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 24/61] target/hppa: Pass d to do_log_cond Richard Henderson
` (37 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Hoist the resolution of d up one level above do_sub_cond.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 77 ++++++++++++++++++++++++++---------------
1 file changed, 49 insertions(+), 28 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index d6edad9adb..7c95c479dc 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -446,12 +446,15 @@ static DisasCond cond_make_n(void)
};
}
-static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0)
+static DisasCond cond_make_tmp(TCGCond c, TCGv_reg a0, TCGv_reg a1)
{
assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS);
- return (DisasCond){
- .c = c, .a0 = a0, .a1 = tcg_constant_reg(0)
- };
+ return (DisasCond){ .c = c, .a0 = a0, .a1 = a1 };
+}
+
+static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0)
+{
+ return cond_make_tmp(c, a0, tcg_constant_reg(0));
}
static DisasCond cond_make_0(TCGCond c, TCGv_reg a0)
@@ -463,15 +466,12 @@ static DisasCond cond_make_0(TCGCond c, TCGv_reg a0)
static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1)
{
- DisasCond r = { .c = c };
+ TCGv_reg t0 = tcg_temp_new();
+ TCGv_reg t1 = tcg_temp_new();
- assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS);
- r.a0 = tcg_temp_new();
- tcg_gen_mov_reg(r.a0, a0);
- r.a1 = tcg_temp_new();
- tcg_gen_mov_reg(r.a1, a1);
-
- return r;
+ tcg_gen_mov_reg(t0, a0);
+ tcg_gen_mov_reg(t1, a1);
+ return cond_make_tmp(c, t0, t1);
}
static void cond_free(DisasCond *cond)
@@ -910,36 +910,55 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
can use the inputs directly. This can allow other computation to be
deleted as unused. */
-static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, TCGv_reg res,
- TCGv_reg in1, TCGv_reg in2, TCGv_reg sv)
+static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d,
+ TCGv_reg res, TCGv_reg in1,
+ TCGv_reg in2, TCGv_reg sv)
{
- DisasCond cond;
- bool d = false;
+ TCGCond tc;
+ bool ext_uns;
switch (cf >> 1) {
case 1: /* = / <> */
- cond = cond_make(TCG_COND_EQ, in1, in2);
+ tc = TCG_COND_EQ;
+ ext_uns = true;
break;
case 2: /* < / >= */
- cond = cond_make(TCG_COND_LT, in1, in2);
+ tc = TCG_COND_LT;
+ ext_uns = false;
break;
case 3: /* <= / > */
- cond = cond_make(TCG_COND_LE, in1, in2);
+ tc = TCG_COND_LE;
+ ext_uns = false;
break;
case 4: /* << / >>= */
- cond = cond_make(TCG_COND_LTU, in1, in2);
+ tc = TCG_COND_LTU;
+ ext_uns = true;
break;
case 5: /* <<= / >> */
- cond = cond_make(TCG_COND_LEU, in1, in2);
+ tc = TCG_COND_LEU;
+ ext_uns = true;
break;
default:
return do_cond(ctx, cf, d, res, NULL, sv);
}
- if (cf & 1) {
- cond.c = tcg_invert_cond(cond.c);
- }
- return cond;
+ if (cf & 1) {
+ tc = tcg_invert_cond(tc);
+ }
+ if (cond_need_ext(ctx, d)) {
+ TCGv_reg t1 = tcg_temp_new();
+ TCGv_reg t2 = tcg_temp_new();
+
+ if (ext_uns) {
+ tcg_gen_ext32u_reg(t1, in1);
+ tcg_gen_ext32u_reg(t2, in2);
+ } else {
+ tcg_gen_ext32s_reg(t1, in1);
+ tcg_gen_ext32s_reg(t2, in2);
+ }
+ return cond_make_tmp(tc, t1, t2);
+ }
+ return cond_make(tc, in1, in2);
}
/*
@@ -1267,7 +1286,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
/* Compute the condition. We cannot use the special case for borrow. */
if (!is_b) {
- cond = do_sub_cond(ctx, cf, dest, in1, in2, sv);
+ cond = do_sub_cond(ctx, cf, d, dest, in1, in2, sv);
} else {
cond = do_cond(ctx, cf, d, dest, get_carry(ctx, d, cb, cb_msb), sv);
}
@@ -1321,6 +1340,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1,
{
TCGv_reg dest, sv;
DisasCond cond;
+ bool d = false;
dest = tcg_temp_new();
tcg_gen_sub_reg(dest, in1, in2);
@@ -1332,7 +1352,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1,
}
/* Form the condition for the compare. */
- cond = do_sub_cond(ctx, cf, dest, in1, in2, sv);
+ cond = do_sub_cond(ctx, cf, d, dest, in1, in2, sv);
/* Clear. */
tcg_gen_movi_reg(dest, 0);
@@ -3028,6 +3048,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1,
{
TCGv_reg dest, in2, sv;
DisasCond cond;
+ bool d = false;
in2 = load_gpr(ctx, r);
dest = tcg_temp_new();
@@ -3039,7 +3060,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1,
sv = do_sub_sv(ctx, dest, in1, in2);
}
- cond = do_sub_cond(ctx, c * 2 + f, dest, in1, in2, sv);
+ cond = do_sub_cond(ctx, c * 2 + f, d, dest, in1, in2, sv);
return do_cbranch(ctx, disp, n, &cond);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 24/61] target/hppa: Pass d to do_log_cond
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (22 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 23/61] target/hppa: Pass d to do_sub_cond Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:50 ` [PATCH 25/61] target/hppa: Pass d to do_sed_cond Richard Henderson
` (36 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Hoist the resolution of d up one level above do_log_cond.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 48 ++++++++++++++++++++++++++++++++---------
1 file changed, 38 insertions(+), 10 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 7c95c479dc..7a3b0f1de7 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -970,9 +970,11 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d,
* how cases c={2,3} are treated.
*/
-static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, TCGv_reg res)
+static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d,
+ TCGv_reg res)
{
- bool d = false;
+ TCGCond tc;
+ bool ext_uns;
switch (cf) {
case 0: /* never */
@@ -988,17 +990,29 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, TCGv_reg res)
return cond_make_t();
case 2: /* == */
- return cond_make_0(TCG_COND_EQ, res);
+ tc = TCG_COND_EQ;
+ ext_uns = true;
+ break;
case 3: /* <> */
- return cond_make_0(TCG_COND_NE, res);
+ tc = TCG_COND_NE;
+ ext_uns = true;
+ break;
case 4: /* < */
- return cond_make_0(TCG_COND_LT, res);
+ tc = TCG_COND_LT;
+ ext_uns = false;
+ break;
case 5: /* >= */
- return cond_make_0(TCG_COND_GE, res);
+ tc = TCG_COND_GE;
+ ext_uns = false;
+ break;
case 6: /* <= */
- return cond_make_0(TCG_COND_LE, res);
+ tc = TCG_COND_LE;
+ ext_uns = false;
+ break;
case 7: /* > */
- return cond_make_0(TCG_COND_GT, res);
+ tc = TCG_COND_GT;
+ ext_uns = false;
+ break;
case 14: /* OD */
case 15: /* EV */
@@ -1007,6 +1021,18 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, TCGv_reg res)
default:
g_assert_not_reached();
}
+
+ if (cond_need_ext(ctx, d)) {
+ TCGv_reg tmp = tcg_temp_new();
+
+ if (ext_uns) {
+ tcg_gen_ext32u_reg(tmp, res);
+ } else {
+ tcg_gen_ext32s_reg(tmp, res);
+ }
+ return cond_make_0_tmp(tc, tmp);
+ }
+ return cond_make_0(tc, res);
}
/* Similar, but for shift/extract/deposit conditions. */
@@ -1014,6 +1040,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, TCGv_reg res)
static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, TCGv_reg res)
{
unsigned c, f;
+ bool d = false;
/* Convert the compressed condition codes to standard.
0-2 are the same as logicals (nv,<,<=), while 3 is OD.
@@ -1024,7 +1051,7 @@ static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, TCGv_reg res)
}
f = (orig & 4) / 4;
- return do_log_cond(ctx, c * 2 + f, res);
+ return do_log_cond(ctx, c * 2 + f, d, res);
}
/* Similar, but for unit conditions. */
@@ -1368,6 +1395,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1,
void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
{
TCGv_reg dest = dest_gpr(ctx, rt);
+ bool d = false;
/* Perform the operation, and writeback. */
fn(dest, in1, in2);
@@ -1376,7 +1404,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1,
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (cf) {
- ctx->null_cond = do_log_cond(ctx, cf, dest);
+ ctx->null_cond = do_log_cond(ctx, cf, d, dest);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 25/61] target/hppa: Pass d to do_sed_cond
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (23 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 24/61] target/hppa: Pass d to do_log_cond Richard Henderson
@ 2023-10-18 21:50 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 26/61] target/hppa: Pass d to do_unit_cond Richard Henderson
` (35 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:50 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Hoist the resolution of d up one level above do_sed_cond.
The MOVB comparison and the existing shift/extract/deposit
are all 32-bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 24 +++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 7a3b0f1de7..1a51ac4869 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1037,10 +1037,10 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d,
/* Similar, but for shift/extract/deposit conditions. */
-static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, TCGv_reg res)
+static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d,
+ TCGv_reg res)
{
unsigned c, f;
- bool d = false;
/* Convert the compressed condition codes to standard.
0-2 are the same as logicals (nv,<,<=), while 3 is OD.
@@ -3203,7 +3203,8 @@ static bool trans_movb(DisasContext *ctx, arg_movb *a)
tcg_gen_mov_reg(dest, cpu_gr[a->r1]);
}
- cond = do_sed_cond(ctx, a->c, dest);
+ /* All MOVB conditions are 32-bit. */
+ cond = do_sed_cond(ctx, a->c, false, dest);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
@@ -3217,7 +3218,8 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi *a)
dest = dest_gpr(ctx, a->r);
tcg_gen_movi_reg(dest, a->i);
- cond = do_sed_cond(ctx, a->c, dest);
+ /* All MOVBI conditions are 32-bit. */
+ cond = do_sed_cond(ctx, a->c, false, dest);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
@@ -3255,7 +3257,7 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3291,7 +3293,7 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3325,7 +3327,7 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3352,7 +3354,7 @@ static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3389,7 +3391,7 @@ static bool trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3419,7 +3421,7 @@ static bool trans_depw_imm(DisasContext *ctx, arg_depw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
}
return nullify_end(ctx);
}
@@ -3456,7 +3458,7 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c,
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (c) {
- ctx->null_cond = do_sed_cond(ctx, c, dest);
+ ctx->null_cond = do_sed_cond(ctx, c, false, dest);
}
return nullify_end(ctx);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 26/61] target/hppa: Pass d to do_unit_cond
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (24 preceding siblings ...)
2023-10-18 21:50 ` [PATCH 25/61] target/hppa: Pass d to do_sed_cond Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 27/61] linux-user/hppa: Fixes for TARGET_ABI32 Richard Henderson
` (34 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Hoist the resolution of d up one level above do_unit_cond.
All computations are logical, and are simplified by using a mask of the
correct width, after which the result may be compared with zero.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 1a51ac4869..8bea28f0fd 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1056,11 +1056,12 @@ static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d,
/* Similar, but for unit conditions. */
-static DisasCond do_unit_cond(unsigned cf, TCGv_reg res,
+static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_reg res,
TCGv_reg in1, TCGv_reg in2)
{
DisasCond cond;
TCGv_reg tmp, cb = NULL;
+ target_ureg d_repl = d ? 0x0000000100000001ull : 1;
if (cf & 8) {
/* Since we want to test lots of carry-out bits all at once, do not
@@ -1087,32 +1088,32 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg res,
* https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
*/
tmp = tcg_temp_new();
- tcg_gen_subi_reg(tmp, res, 0x01010101u);
+ tcg_gen_subi_reg(tmp, res, d_repl * 0x01010101u);
tcg_gen_andc_reg(tmp, tmp, res);
- tcg_gen_andi_reg(tmp, tmp, 0x80808080u);
+ tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80808080u);
cond = cond_make_0(TCG_COND_NE, tmp);
break;
case 3: /* SHZ / NHZ */
tmp = tcg_temp_new();
- tcg_gen_subi_reg(tmp, res, 0x00010001u);
+ tcg_gen_subi_reg(tmp, res, d_repl * 0x00010001u);
tcg_gen_andc_reg(tmp, tmp, res);
- tcg_gen_andi_reg(tmp, tmp, 0x80008000u);
+ tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80008000u);
cond = cond_make_0(TCG_COND_NE, tmp);
break;
case 4: /* SDC / NDC */
- tcg_gen_andi_reg(cb, cb, 0x88888888u);
+ tcg_gen_andi_reg(cb, cb, d_repl * 0x88888888u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
case 6: /* SBC / NBC */
- tcg_gen_andi_reg(cb, cb, 0x80808080u);
+ tcg_gen_andi_reg(cb, cb, d_repl * 0x80808080u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
case 7: /* SHC / NHC */
- tcg_gen_andi_reg(cb, cb, 0x80008000u);
+ tcg_gen_andi_reg(cb, cb, d_repl * 0x80008000u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
@@ -1428,6 +1429,7 @@ static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1,
{
TCGv_reg dest;
DisasCond cond;
+ bool d = false;
if (cf == 0) {
dest = dest_gpr(ctx, rt);
@@ -1438,7 +1440,7 @@ static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1,
dest = tcg_temp_new();
fn(dest, in1, in2);
- cond = do_unit_cond(cf, dest, in1, in2);
+ cond = do_unit_cond(cf, d, dest, in1, in2);
if (is_tc) {
TCGv_reg tmp = tcg_temp_new();
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 27/61] linux-user/hppa: Fixes for TARGET_ABI32
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (25 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 26/61] target/hppa: Pass d to do_unit_cond Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-19 9:49 ` Philippe Mathieu-Daudé
2023-10-18 21:51 ` [PATCH 28/61] target/hppa: Drop attempted gdbstub support for hppa64 Richard Henderson
` (33 subsequent siblings)
60 siblings, 1 reply; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Avoid target_ulong and use abi_* types.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/hppa/signal.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/linux-user/hppa/signal.c b/linux-user/hppa/signal.c
index ec5f5412d1..4400ce4df4 100644
--- a/linux-user/hppa/signal.c
+++ b/linux-user/hppa/signal.c
@@ -72,7 +72,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPUArchState *env)
static void restore_sigcontext(CPUArchState *env, struct target_sigcontext *sc)
{
- target_ulong psw;
+ abi_ulong psw;
int i;
__get_user(psw, &sc->sc_gr[0]);
@@ -146,10 +146,10 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
haddr = ka->_sa_handler;
if (haddr & 2) {
/* Function descriptor. */
- target_ulong *fdesc, dest;
+ abi_ptr *fdesc, dest;
haddr &= -4;
- fdesc = lock_user(VERIFY_READ, haddr, 2 * sizeof(target_ulong), 1);
+ fdesc = lock_user(VERIFY_READ, haddr, 2 * sizeof(abi_ptr), 1);
if (!fdesc) {
goto give_sigsegv;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 28/61] target/hppa: Drop attempted gdbstub support for hppa64
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (26 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 27/61] linux-user/hppa: Fixes for TARGET_ABI32 Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 29/61] target/hppa: Remove TARGET_HPPA64 Richard Henderson
` (32 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
There is no support for hppa64 in gdb. Any attempt to provide the
data for the larger hppa64 registers results in an error from gdb.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/gdbstub.c | 26 +++++++++++---------------
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c
index 48a514384f..748431097c 100644
--- a/target/hppa/gdbstub.c
+++ b/target/hppa/gdbstub.c
@@ -21,11 +21,17 @@
#include "cpu.h"
#include "gdbstub/helpers.h"
+/*
+ * GDB 15 only supports PA1.0 via the remote protocol, and ignores
+ * any provided xml. Which means that any attempt to provide more
+ * data results in "Remote 'g' packet reply is too long".
+ */
+
int hppa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
HPPACPU *cpu = HPPA_CPU(cs);
CPUHPPAState *env = &cpu->env;
- target_ureg val;
+ uint32_t val;
switch (n) {
case 0:
@@ -139,24 +145,14 @@ int hppa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
break;
}
- if (TARGET_REGISTER_BITS == 64) {
- return gdb_get_reg64(mem_buf, val);
- } else {
- return gdb_get_reg32(mem_buf, val);
- }
+ return gdb_get_reg32(mem_buf, val);
}
int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
HPPACPU *cpu = HPPA_CPU(cs);
CPUHPPAState *env = &cpu->env;
- target_ureg val;
-
- if (TARGET_REGISTER_BITS == 64) {
- val = ldq_p(mem_buf);
- } else {
- val = ldl_p(mem_buf);
- }
+ uint32_t val = ldl_p(mem_buf);
switch (n) {
case 0:
@@ -166,7 +162,7 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
env->gr[n] = val;
break;
case 32:
- env->cr[CR_SAR] = val;
+ env->cr[CR_SAR] = val & (cpu->is_pa20 ? 63 : 31);
break;
case 33:
env->iaoq_f = val;
@@ -278,5 +274,5 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
}
break;
}
- return sizeof(target_ureg);
+ return 4;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 29/61] target/hppa: Remove TARGET_HPPA64
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (27 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 28/61] target/hppa: Drop attempted gdbstub support for hppa64 Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 30/61] target/hppa: Decode d for logical instructions Richard Henderson
` (31 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Allow both user-only and system mode to run pa2.0 cpus.
Avoid creating a separate qemu-system-hppa64 binary;
force the qemu-hppa binary to use TARGET_ABI32.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
configs/targets/hppa-linux-user.mak | 1 +
target/hppa/cpu-param.h | 23 +++++++----------------
target/hppa/cpu.h | 9 ---------
target/hppa/cpu.c | 4 ----
target/hppa/translate.c | 2 --
5 files changed, 8 insertions(+), 31 deletions(-)
diff --git a/configs/targets/hppa-linux-user.mak b/configs/targets/hppa-linux-user.mak
index 361ea39d71..8e0a80492f 100644
--- a/configs/targets/hppa-linux-user.mak
+++ b/configs/targets/hppa-linux-user.mak
@@ -1,4 +1,5 @@
TARGET_ARCH=hppa
+TARGET_ABI32=y
TARGET_SYSTBL_ABI=common,32
TARGET_SYSTBL=syscall.tbl
TARGET_BIG_ENDIAN=y
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index c2791ae5f2..2fb8e7924b 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -8,26 +8,17 @@
#ifndef HPPA_CPU_PARAM_H
#define HPPA_CPU_PARAM_H
-#ifdef TARGET_HPPA64
-# define TARGET_LONG_BITS 64
-# define TARGET_REGISTER_BITS 64
-# define TARGET_VIRT_ADDR_SPACE_BITS 64
-# define TARGET_PHYS_ADDR_SPACE_BITS 64
-#elif defined(CONFIG_USER_ONLY)
-# define TARGET_LONG_BITS 32
-# define TARGET_REGISTER_BITS 32
+#define TARGET_LONG_BITS 64
+#define TARGET_REGISTER_BITS 64
+
+#if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32)
+# define TARGET_PHYS_ADDR_SPACE_BITS 32
# define TARGET_VIRT_ADDR_SPACE_BITS 32
-# define TARGET_PHYS_ADDR_SPACE_BITS 32
#else
-/*
- * In order to form the GVA from space:offset,
- * we need a 64-bit virtual address space.
- */
-# define TARGET_LONG_BITS 64
-# define TARGET_REGISTER_BITS 32
+# define TARGET_PHYS_ADDR_SPACE_BITS 64
# define TARGET_VIRT_ADDR_SPACE_BITS 64
-# define TARGET_PHYS_ADDR_SPACE_BITS 32
#endif
+
#define TARGET_PAGE_BITS 12
#endif
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 1a12b2a186..251f85444a 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -107,11 +107,7 @@
#define PSW_T 0x01000000
#define PSW_S 0x02000000
#define PSW_E 0x04000000
-#ifdef TARGET_HPPA64
#define PSW_W 0x08000000 /* PA2.0 only */
-#else
-#define PSW_W 0
-#endif
#define PSW_Z 0x40000000 /* PA1.x only */
#define PSW_Y 0x80000000 /* PA1.x only */
@@ -124,13 +120,8 @@
#define PSW_SM_P PSW_P
#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
-#ifdef TARGET_HPPA64
#define PSW_SM_E 0x100
#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
-#else
-#define PSW_SM_E 0
-#define PSW_SM_W 0
-#endif
#define CR_RC 0
#define CR_PID1 8
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 6bf415139f..bbb6080e2d 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -253,7 +253,6 @@ static const TypeInfo hppa_cpu_type_info = {
.class_init = hppa_cpu_class_init,
};
-#ifdef TARGET_HPPA64
static void hppa64_cpu_initfn(Object *obj)
{
HPPACPU *cpu = HPPA_CPU(obj);
@@ -265,14 +264,11 @@ static const TypeInfo hppa64_cpu_type_info = {
.parent = TYPE_HPPA_CPU,
.instance_init = hppa64_cpu_initfn,
};
-#endif
static void hppa_cpu_register_types(void)
{
type_register_static(&hppa_cpu_type_info);
-#ifdef TARGET_HPPA64
type_register_static(&hppa64_cpu_type_info);
-#endif
}
type_init(hppa_cpu_register_types)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 8bea28f0fd..94969cf2f0 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2156,7 +2156,6 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a)
switch (ctl) {
case CR_SAR:
-#ifdef TARGET_HPPA64
if (a->e == 0) {
/* MFSAR without ,W masks low 5 bits. */
tmp = dest_gpr(ctx, rt);
@@ -2164,7 +2163,6 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a)
save_gpr(ctx, rt, tmp);
goto done;
}
-#endif
save_gpr(ctx, rt, cpu_sar);
goto done;
case CR_IT: /* Interval Timer */
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 30/61] target/hppa: Decode d for logical instructions
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (28 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 29/61] target/hppa: Remove TARGET_HPPA64 Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 31/61] target/hppa: Decode d for unit instructions Richard Henderson
` (30 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 10 ++++++----
target/hppa/translate.c | 15 +++++++--------
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index aebe03ccfd..26ca9f1063 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -61,6 +61,7 @@
&rr_cf t r cf
&rrr_cf t r1 r2 cf
+&rrr_cf_d t r1 r2 cf d
&rrr_cf_sh t r1 r2 cf sh
&rri_cf t r i cf
@@ -73,6 +74,7 @@
@rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf
@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
+@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d
@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh
@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0
@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11
@@ -150,10 +152,10 @@ lci 000001 ----- ----- -- 01001100 0 t:5
# Arith/Log
####
-andcm 000010 ..... ..... .... 000000 - ..... @rrr_cf
-and 000010 ..... ..... .... 001000 - ..... @rrr_cf
-or 000010 ..... ..... .... 001001 - ..... @rrr_cf
-xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf
+andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d
+and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d
+or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d
+xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d
uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf
ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf
cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 94969cf2f0..5eecced442 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1392,11 +1392,10 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1,
}
static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1,
- TCGv_reg in2, unsigned cf,
+ TCGv_reg in2, unsigned cf, bool d,
void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
{
TCGv_reg dest = dest_gpr(ctx, rt);
- bool d = false;
/* Perform the operation, and writeback. */
fn(dest, in1, in2);
@@ -1409,7 +1408,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1,
}
}
-static bool do_log_reg(DisasContext *ctx, arg_rrr_cf *a,
+static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a,
void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
{
TCGv_reg tcg_r1, tcg_r2;
@@ -1419,7 +1418,7 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_cf *a,
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
- do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, fn);
+ do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, fn);
return nullify_end(ctx);
}
@@ -2672,17 +2671,17 @@ static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf *a)
return do_sub_reg(ctx, a, true, true, false);
}
-static bool trans_andcm(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_andcm(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_log_reg(ctx, a, tcg_gen_andc_reg);
}
-static bool trans_and(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_and(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_log_reg(ctx, a, tcg_gen_and_reg);
}
-static bool trans_or(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a)
{
if (a->cf == 0) {
unsigned r2 = a->r2;
@@ -2734,7 +2733,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a)
return do_log_reg(ctx, a, tcg_gen_or_reg);
}
-static bool trans_xor(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_log_reg(ctx, a, tcg_gen_xor_reg);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 31/61] target/hppa: Decode d for unit instructions
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (29 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 30/61] target/hppa: Decode d for logical instructions Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 32/61] target/hppa: Decode d for cmpclr instructions Richard Henderson
` (29 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 14 +++++++-------
target/hppa/translate.c | 25 ++++++++++++-------------
2 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 26ca9f1063..03b1a11cac 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -59,7 +59,7 @@
# All insns that need to form a virtual address should use this set.
&ldst t b x disp sp m scale size
-&rr_cf t r cf
+&rr_cf_d t r cf d
&rrr_cf t r1 r2 cf
&rrr_cf_d t r1 r2 cf d
&rrr_cf_sh t r1 r2 cf sh
@@ -72,7 +72,7 @@
# Format definitions
####
-@rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf
+@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d
@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d
@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh
@@ -156,13 +156,13 @@ andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d
and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d
or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d
xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d
-uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf
+uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d
ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf
cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf
-uaddcm 000010 ..... ..... .... 100110 0 ..... @rrr_cf
-uaddcm_tc 000010 ..... ..... .... 100111 0 ..... @rrr_cf
-dcor 000010 ..... 00000 .... 101110 0 ..... @rr_cf
-dcor_i 000010 ..... 00000 .... 101111 0 ..... @rr_cf
+uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d
+uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d
+dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d
+dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d
add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh
add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 5eecced442..ed00b58fbc 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1423,12 +1423,11 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a,
}
static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1,
- TCGv_reg in2, unsigned cf, bool is_tc,
+ TCGv_reg in2, unsigned cf, bool d, bool is_tc,
void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
{
TCGv_reg dest;
DisasCond cond;
- bool d = false;
if (cf == 0) {
dest = dest_gpr(ctx, rt);
@@ -2751,7 +2750,7 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a)
return nullify_end(ctx);
}
-static bool trans_uxor(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a)
{
TCGv_reg tcg_r1, tcg_r2;
@@ -2760,11 +2759,11 @@ static bool trans_uxor(DisasContext *ctx, arg_rrr_cf *a)
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
- do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, false, tcg_gen_xor_reg);
+ do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_reg);
return nullify_end(ctx);
}
-static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc)
+static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc)
{
TCGv_reg tcg_r1, tcg_r2, tmp;
@@ -2775,21 +2774,21 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc)
tcg_r2 = load_gpr(ctx, a->r2);
tmp = tcg_temp_new();
tcg_gen_not_reg(tmp, tcg_r2);
- do_unit(ctx, a->t, tcg_r1, tmp, a->cf, is_tc, tcg_gen_add_reg);
+ do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_reg);
return nullify_end(ctx);
}
-static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_uaddcm(ctx, a, false);
}
-static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_uaddcm(ctx, a, true);
}
-static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, bool is_i)
+static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i)
{
TCGv_reg tmp;
@@ -2800,19 +2799,19 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, bool is_i)
if (!is_i) {
tcg_gen_not_reg(tmp, tmp);
}
- tcg_gen_andi_reg(tmp, tmp, 0x11111111);
+ tcg_gen_andi_reg(tmp, tmp, (target_ureg)0x1111111111111111ull);
tcg_gen_muli_reg(tmp, tmp, 6);
- do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, false,
+ do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false,
is_i ? tcg_gen_add_reg : tcg_gen_sub_reg);
return nullify_end(ctx);
}
-static bool trans_dcor(DisasContext *ctx, arg_rr_cf *a)
+static bool trans_dcor(DisasContext *ctx, arg_rr_cf_d *a)
{
return do_dcor(ctx, a, false);
}
-static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf *a)
+static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf_d *a)
{
return do_dcor(ctx, a, true);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 32/61] target/hppa: Decode d for cmpclr instructions
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (30 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 31/61] target/hppa: Decode d for unit instructions Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 33/61] target/hppa: Decode d for add instructions Richard Henderson
` (28 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 6 ++++--
target/hppa/translate.c | 11 +++++------
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 03b1a11cac..d4a03b0299 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -64,6 +64,7 @@
&rrr_cf_d t r1 r2 cf d
&rrr_cf_sh t r1 r2 cf sh
&rri_cf t r i cf
+&rri_cf_d t r i cf d
&rrb_c_f disp n c f r1 r2
&rib_c_f disp n c f r i
@@ -78,6 +79,7 @@
@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh
@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0
@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11
+@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11
@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \
&rrb_c_f disp=%assemble_12
@@ -158,7 +160,7 @@ or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d
xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d
uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d
ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf
-cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf
+cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d
uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d
uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d
dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d
@@ -189,7 +191,7 @@ addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf
subi 100101 ..... ..... .... 0 ........... @rri_cf
subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf
-cmpiclr 100100 ..... ..... .... 0 ........... @rri_cf
+cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d
####
# Index Mem
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index ed00b58fbc..58d69cb748 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1364,11 +1364,10 @@ static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv)
}
static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1,
- TCGv_reg in2, unsigned cf)
+ TCGv_reg in2, unsigned cf, bool d)
{
TCGv_reg dest, sv;
DisasCond cond;
- bool d = false;
dest = tcg_temp_new();
tcg_gen_sub_reg(dest, in1, in2);
@@ -2737,7 +2736,7 @@ static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a)
return do_log_reg(ctx, a, tcg_gen_xor_reg);
}
-static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf_d *a)
{
TCGv_reg tcg_r1, tcg_r2;
@@ -2746,7 +2745,7 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a)
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
- do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf);
+ do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d);
return nullify_end(ctx);
}
@@ -2904,7 +2903,7 @@ static bool trans_subi_tsv(DisasContext *ctx, arg_rri_cf *a)
return do_sub_imm(ctx, a, true);
}
-static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a)
+static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf_d *a)
{
TCGv_reg tcg_im, tcg_r2;
@@ -2914,7 +2913,7 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a)
tcg_im = tcg_constant_reg(a->i);
tcg_r2 = load_gpr(ctx, a->r);
- do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf);
+ do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf, a->d);
return nullify_end(ctx);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 33/61] target/hppa: Decode d for add instructions
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (31 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 32/61] target/hppa: Decode d for cmpclr instructions Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 34/61] target/hppa: Decode d for sub instructions Richard Henderson
` (27 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 16 ++++++++--------
target/hppa/translate.c | 21 +++++++++++----------
2 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index d4a03b0299..0f29869949 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -62,7 +62,7 @@
&rr_cf_d t r cf d
&rrr_cf t r1 r2 cf
&rrr_cf_d t r1 r2 cf d
-&rrr_cf_sh t r1 r2 cf sh
+&rrr_cf_d_sh t r1 r2 cf d sh
&rri_cf t r i cf
&rri_cf_d t r i cf d
@@ -76,8 +76,8 @@
@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d
@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d
-@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh
-@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0
+@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh
+@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0
@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11
@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11
@@ -166,11 +166,11 @@ uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d
dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d
dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d
-add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh
-add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh
-add_tsv 000010 ..... ..... .... 1110.. 0 ..... @rrr_cf_sh
-add_c 000010 ..... ..... .... 011100 0 ..... @rrr_cf_sh0
-add_c_tsv 000010 ..... ..... .... 111100 0 ..... @rrr_cf_sh0
+add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh
+add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh
+add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh
+add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0
+add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0
sub 000010 ..... ..... .... 010000 - ..... @rrr_cf
sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 58d69cb748..1bf61628d1 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1173,12 +1173,11 @@ static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res,
static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
TCGv_reg in2, unsigned shift, bool is_l,
- bool is_tsv, bool is_tc, bool is_c, unsigned cf)
+ bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d)
{
TCGv_reg dest, cb, cb_msb, cb_cond, sv, tmp;
unsigned c = cf >> 1;
DisasCond cond;
- bool d = false;
dest = tcg_temp_new();
cb = NULL;
@@ -1243,7 +1242,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
ctx->null_cond = cond;
}
-static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_sh *a,
+static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a,
bool is_l, bool is_tsv, bool is_tc, bool is_c)
{
TCGv_reg tcg_r1, tcg_r2;
@@ -1253,7 +1252,8 @@ static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_sh *a,
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
- do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, is_tsv, is_tc, is_c, a->cf);
+ do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l,
+ is_tsv, is_tc, is_c, a->cf, a->d);
return nullify_end(ctx);
}
@@ -1267,7 +1267,8 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a,
}
tcg_im = tcg_constant_reg(a->i);
tcg_r2 = load_gpr(ctx, a->r);
- do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf);
+ /* All ADDI conditions are 32-bit. */
+ do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf, false);
return nullify_end(ctx);
}
@@ -2614,27 +2615,27 @@ static bool trans_lci(DisasContext *ctx, arg_lci *a)
return true;
}
-static bool trans_add(DisasContext *ctx, arg_rrr_cf_sh *a)
+static bool trans_add(DisasContext *ctx, arg_rrr_cf_d_sh *a)
{
return do_add_reg(ctx, a, false, false, false, false);
}
-static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_sh *a)
+static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_d_sh *a)
{
return do_add_reg(ctx, a, true, false, false, false);
}
-static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_sh *a)
+static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_d_sh *a)
{
return do_add_reg(ctx, a, false, true, false, false);
}
-static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_sh *a)
+static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_d_sh *a)
{
return do_add_reg(ctx, a, false, false, false, true);
}
-static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_sh *a)
+static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_d_sh *a)
{
return do_add_reg(ctx, a, false, true, false, true);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 34/61] target/hppa: Decode d for sub instructions
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (32 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 33/61] target/hppa: Decode d for add instructions Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 35/61] target/hppa: Decode d for bb instructions Richard Henderson
` (26 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 12 ++++++------
target/hppa/translate.c | 22 +++++++++++-----------
2 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 0f29869949..ad454adcbb 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -172,12 +172,12 @@ add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh
add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0
add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0
-sub 000010 ..... ..... .... 010000 - ..... @rrr_cf
-sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf
-sub_tc 000010 ..... ..... .... 010011 0 ..... @rrr_cf
-sub_tsv_tc 000010 ..... ..... .... 110011 0 ..... @rrr_cf
-sub_b 000010 ..... ..... .... 010100 0 ..... @rrr_cf
-sub_b_tsv 000010 ..... ..... .... 110100 0 ..... @rrr_cf
+sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d
+sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d
+sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d
+sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d
+sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d
+sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d
ldil 001000 t:5 ..................... i=%assemble_21
addil 001010 r:5 ..................... i=%assemble_21
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 1bf61628d1..e21a206466 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1274,12 +1274,11 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a,
static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
TCGv_reg in2, bool is_tsv, bool is_b,
- bool is_tc, unsigned cf)
+ bool is_tc, unsigned cf, bool d)
{
TCGv_reg dest, sv, cb, cb_msb, zero, tmp;
unsigned c = cf >> 1;
DisasCond cond;
- bool d = false;
dest = tcg_temp_new();
cb = tcg_temp_new();
@@ -1337,7 +1336,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
ctx->null_cond = cond;
}
-static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf *a,
+static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf_d *a,
bool is_tsv, bool is_b, bool is_tc)
{
TCGv_reg tcg_r1, tcg_r2;
@@ -1347,7 +1346,7 @@ static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf *a,
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
- do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf);
+ do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf, a->d);
return nullify_end(ctx);
}
@@ -1360,7 +1359,8 @@ static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv)
}
tcg_im = tcg_constant_reg(a->i);
tcg_r2 = load_gpr(ctx, a->r);
- do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf);
+ /* All SUBI conditions are 32-bit. */
+ do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf, false);
return nullify_end(ctx);
}
@@ -2640,32 +2640,32 @@ static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_d_sh *a)
return do_add_reg(ctx, a, false, true, false, true);
}
-static bool trans_sub(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_sub(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_sub_reg(ctx, a, false, false, false);
}
-static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_sub_reg(ctx, a, true, false, false);
}
-static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_sub_reg(ctx, a, false, false, true);
}
-static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_sub_reg(ctx, a, true, false, true);
}
-static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_sub_reg(ctx, a, false, true, false);
}
-static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf *a)
+static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf_d *a)
{
return do_sub_reg(ctx, a, true, true, false);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 35/61] target/hppa: Decode d for bb instructions
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (33 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 34/61] target/hppa: Decode d for sub instructions Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 36/61] target/hppa: Decode d for cmpb instructions Richard Henderson
` (25 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Manipulate the shift count so that the bit to be tested
is always placed at the MSB.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 4 ++--
target/hppa/translate.c | 6 ++----
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index ad454adcbb..b185523021 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -290,8 +290,8 @@ fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd
# Conditional Branches
####
-bb_sar 110000 00000 r:5 c:1 10 ........... n:1 . disp=%assemble_12
-bb_imm 110001 p:5 r:5 c:1 10 ........... n:1 . disp=%assemble_12
+bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
+bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
movb 110010 ..... ..... ... ........... . . @rrb_cf f=0
movbi 110011 ..... ..... ... ........... . . @rib_cf f=0
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index e21a206466..33da82b7c8 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3151,13 +3151,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
{
TCGv_reg tmp, tcg_r;
DisasCond cond;
- bool d = false;
nullify_over(ctx);
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
- if (cond_need_ext(ctx, d)) {
+ if (cond_need_ext(ctx, a->d)) {
/* Force shift into [32,63] */
tcg_gen_ori_reg(tmp, cpu_sar, 32);
tcg_gen_shl_reg(tmp, tcg_r, tmp);
@@ -3173,14 +3172,13 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
{
TCGv_reg tmp, tcg_r;
DisasCond cond;
- bool d = false;
int p;
nullify_over(ctx);
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
- p = a->p | (cond_need_ext(ctx, d) ? 32 : 0);
+ p = a->p | (cond_need_ext(ctx, a->d) ? 32 : 0);
tcg_gen_shli_reg(tmp, tcg_r, p);
cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 36/61] target/hppa: Decode d for cmpb instructions
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (34 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 35/61] target/hppa: Decode d for bb instructions Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 37/61] target/hppa: Decode CMPIB double-word Richard Henderson
` (24 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 9 +++++++--
target/hppa/translate.c | 12 ++++++++----
2 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index b185523021..fc327e2bb3 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -67,6 +67,7 @@
&rri_cf_d t r i cf d
&rrb_c_f disp n c f r1 r2
+&rrb_c_d_f disp n c d f r1 r2
&rib_c_f disp n c f r i
####
@@ -83,6 +84,8 @@
@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \
&rrb_c_f disp=%assemble_12
+@rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \
+ &rrb_c_d_f disp=%assemble_12
@rib_cf ...... r:5 ..... c:3 ........... n:1 . \
&rib_c_f disp=%assemble_12 i=%im5_16
@@ -296,8 +299,10 @@ bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
movb 110010 ..... ..... ... ........... . . @rrb_cf f=0
movbi 110011 ..... ..... ... ........... . . @rib_cf f=0
-cmpb 100000 ..... ..... ... ........... . . @rrb_cf f=0
-cmpb 100010 ..... ..... ... ........... . . @rrb_cf f=1
+cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=0 f=0
+cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=0 f=1
+cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=1 f=0
+cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=1 f=1
cmpbi 100001 ..... ..... ... ........... . . @rib_cf f=0
cmpbi 100011 ..... ..... ... ........... . . @rib_cf f=1
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 33da82b7c8..681c955125 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3070,11 +3070,10 @@ static bool trans_ldo(DisasContext *ctx, arg_ldo *a)
}
static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1,
- unsigned c, unsigned f, unsigned n, int disp)
+ unsigned c, unsigned f, bool d, unsigned n, int disp)
{
TCGv_reg dest, in2, sv;
DisasCond cond;
- bool d = false;
in2 = load_gpr(ctx, r);
dest = tcg_temp_new();
@@ -3092,14 +3091,19 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1,
static bool trans_cmpb(DisasContext *ctx, arg_cmpb *a)
{
+ if (!ctx->is_pa20 && a->d) {
+ return false;
+ }
nullify_over(ctx);
- return do_cmpb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->disp);
+ return do_cmpb(ctx, a->r2, load_gpr(ctx, a->r1),
+ a->c, a->f, a->d, a->n, a->disp);
}
static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a)
{
nullify_over(ctx);
- return do_cmpb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a->disp);
+ return do_cmpb(ctx, a->r, tcg_constant_reg(a->i),
+ a->c, a->f, false, a->n, a->disp);
}
static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1,
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 37/61] target/hppa: Decode CMPIB double-word
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (35 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 36/61] target/hppa: Decode d for cmpb instructions Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 38/61] target/hppa: Decode ADDB double-word Richard Henderson
` (23 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 10 ++++++++--
target/hppa/translate.c | 11 ++++++++++-
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index fc327e2bb3..48f09c9b06 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -51,6 +51,7 @@
%pos_to_m 0:1 !function=pos_to_m
%neg_to_m 0:1 !function=neg_to_m
%a_to_m 2:1 !function=neg_to_m
+%cmpbid_c 13:2 !function=cmpbid_c
####
# Argument set definitions
@@ -69,6 +70,7 @@
&rrb_c_f disp n c f r1 r2
&rrb_c_d_f disp n c d f r1 r2
&rib_c_f disp n c f r i
+&rib_c_d_f disp n c d f r i
####
# Format definitions
@@ -88,6 +90,8 @@
&rrb_c_d_f disp=%assemble_12
@rib_cf ...... r:5 ..... c:3 ........... n:1 . \
&rib_c_f disp=%assemble_12 i=%im5_16
+@rib_cdf ...... r:5 ..... c:3 ........... n:1 . \
+ &rib_c_d_f disp=%assemble_12 i=%im5_16
####
# System
@@ -303,8 +307,10 @@ cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=0 f=0
cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=0 f=1
cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=1 f=0
cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=1 f=1
-cmpbi 100001 ..... ..... ... ........... . . @rib_cf f=0
-cmpbi 100011 ..... ..... ... ........... . . @rib_cf f=1
+cmpbi 100001 ..... ..... ... ........... . . @rib_cdf d=0 f=0
+cmpbi 100011 ..... ..... ... ........... . . @rib_cdf d=0 f=1
+cmpbi 111011 r:5 ..... f:1 .. ........... n:1 . \
+ &rib_c_d_f d=1 disp=%assemble_12 c=%cmpbid_c i=%im5_16
addb 101000 ..... ..... ... ........... . . @rrb_cf f=0
addb 101010 ..... ..... ... ........... . . @rrb_cf f=1
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 681c955125..753748082b 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -329,6 +329,12 @@ static int expand_shl11(DisasContext *ctx, int val)
return val << 11;
}
+/* Translate CMPI doubleword conditions to standard. */
+static int cmpbid_c(DisasContext *ctx, int val)
+{
+ return val ? val : 4; /* 0 == "*<<" */
+}
+
/* Include the auto-generated decoder. */
#include "decode-insns.c.inc"
@@ -3101,9 +3107,12 @@ static bool trans_cmpb(DisasContext *ctx, arg_cmpb *a)
static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a)
{
+ if (!ctx->is_pa20 && a->d) {
+ return false;
+ }
nullify_over(ctx);
return do_cmpb(ctx, a->r, tcg_constant_reg(a->i),
- a->c, a->f, false, a->n, a->disp);
+ a->c, a->f, a->d, a->n, a->disp);
}
static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1,
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 38/61] target/hppa: Decode ADDB double-word
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (36 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 37/61] target/hppa: Decode CMPIB double-word Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 39/61] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA Richard Henderson
` (22 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 753748082b..7e723dcd24 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3122,6 +3122,17 @@ static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1,
DisasCond cond;
bool d = false;
+ /*
+ * For hppa64, the ADDB conditions change, dropping ZNV, SV, OD
+ * in favor of double-word EQ, LT, LE.
+ */
+ if (ctx->is_pa20) {
+ d = c >= 5;
+ if (d) {
+ c &= 3;
+ }
+ }
+
in2 = load_gpr(ctx, r);
dest = tcg_temp_new();
sv = NULL;
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 39/61] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (37 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 38/61] target/hppa: Decode ADDB double-word Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 40/61] target/hppa: Implement DEPD, DEPDI Richard Henderson
` (21 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 15 +++++++++++----
target/hppa/translate.c | 4 ++++
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 48f09c9b06..33eec3f4c3 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -215,9 +215,14 @@ ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx
st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5
ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2
ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2
+ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 size=3
+ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx size=3
lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2
lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2
+lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 size=3
+lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx size=3
sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2
+sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3
stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0
@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \
@@ -244,6 +249,8 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi
# Offset Mem
####
+@ldstim11 ...... b:5 t:5 sp:2 .............. \
+ &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
@ldstim14 ...... b:5 t:5 sp:2 .............. \
&ldst disp=%lowsign_14 x=0 scale=0 m=0
@ldstim14m ...... b:5 t:5 sp:2 .............. \
@@ -275,11 +282,11 @@ fstw 011110 b:5 ..... sp:2 .............. \
fstw 011111 b:5 ..... sp:2 ...........0.. \
&ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
-fldd 010100 b:5 t:5 sp:2 .......... .. 1 . \
- &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
+ld 010100 ..... ..... .. ............0. @ldstim11
+fldd 010100 ..... ..... .. ............1. @ldstim11
-fstd 011100 b:5 t:5 sp:2 .......... .. 1 . \
- &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
+st 011100 ..... ..... .. ............0. @ldstim11
+fstd 011100 ..... ..... .. ............1. @ldstim11
####
# Floating-point Multiply Add
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 7e723dcd24..308b8dd263 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2951,6 +2951,10 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
TCGv_reg zero, dest, ofs;
TCGv_tl addr;
+ if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) {
+ return gen_illegal(ctx);
+ }
+
nullify_over(ctx);
if (a->m) {
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 40/61] target/hppa: Implement DEPD, DEPDI
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (38 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 39/61] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 41/61] target/hppa: Implement EXTRD Richard Henderson
` (20 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 19 ++++++++--
target/hppa/translate.c | 80 +++++++++++++++++++++++++++-------------
2 files changed, 69 insertions(+), 30 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 33eec3f4c3..12684b590e 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -46,6 +46,10 @@
%im5_0 0:s1 1:4
%im5_16 16:s1 17:4
+%len5 0:5 !function=assemble_6
+%len6_8 8:1 0:5 !function=assemble_6
+%len6_12 12:1 0:5 !function=assemble_6
+%cpos6_11 11:1 5:5
%ma_to_m 5:1 13:1 !function=ma_to_m
%ma2_to_m 2:2 !function=ma_to_m
%pos_to_m 0:1 !function=pos_to_m
@@ -334,10 +338,17 @@ shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5
extrw_sar 110100 r:5 t:5 c:3 10 se:1 00000 clen:5
extrw_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 clen:5
-depw_sar 110101 t:5 r:5 c:3 00 nz:1 00000 clen:5
-depw_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 clen:5
-depwi_sar 110101 t:5 ..... c:3 10 nz:1 00000 clen:5 i=%im5_16
-depwi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 clen:5 i=%im5_16
+dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=0 len=%len5
+dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=1 len=%len6_8
+dep_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 ..... d=0 len=%len5
+dep_imm 111100 t:5 r:5 c:3 .. nz:1 ..... ..... \
+ d=1 len=%len6_12 cpos=%cpos6_11
+depi_sar 110101 t:5 ..... c:3 10 nz:1 d:1 . 000 ..... \
+ i=%im5_16 len=%len6_8
+depi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 ..... \
+ d=0 i=%im5_16 len=%len5
+depi_imm 111101 t:5 ..... c:3 .. nz:1 ..... ..... \
+ d=1 i=%im5_16 len=%len6_12 cpos=%cpos6_11
####
# Branch External
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 308b8dd263..b3d3506f94 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -329,6 +329,17 @@ static int expand_shl11(DisasContext *ctx, int val)
return val << 11;
}
+static int assemble_6(DisasContext *ctx, int val)
+{
+ /*
+ * Officially, 32 * x + 32 - y.
+ * Here, x is already in bit 5, and y is [4:0].
+ * Since -y = ~y + 1, in 5 bits 32 - y => y ^ 31 + 1,
+ * with the overflow from bit 4 summing with x.
+ */
+ return (val ^ 31) + 1;
+}
+
/* Translate CMPI doubleword conditions to standard. */
static int cmpbid_c(DisasContext *ctx, int val)
{
@@ -3383,17 +3394,23 @@ static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a)
return nullify_end(ctx);
}
-static bool trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a)
+static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a)
{
- unsigned len = 32 - a->clen;
+ unsigned len, width;
target_sreg mask0, mask1;
TCGv_reg dest;
+ if (!ctx->is_pa20 && a->d) {
+ return false;
+ }
if (a->c) {
nullify_over(ctx);
}
- if (a->cpos + len > 32) {
- len = 32 - a->cpos;
+
+ len = a->len;
+ width = a->d ? 64 : 32;
+ if (a->cpos + len > width) {
+ len = width - a->cpos;
}
dest = dest_gpr(ctx, a->t);
@@ -3402,11 +3419,8 @@ static bool trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a)
if (a->nz) {
TCGv_reg src = load_gpr(ctx, a->t);
- if (mask1 != -1) {
- tcg_gen_andi_reg(dest, src, mask1);
- src = dest;
- }
- tcg_gen_ori_reg(dest, src, mask0);
+ tcg_gen_andi_reg(dest, src, mask1);
+ tcg_gen_ori_reg(dest, dest, mask0);
} else {
tcg_gen_movi_reg(dest, mask0);
}
@@ -3415,22 +3429,28 @@ static bool trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest);
}
return nullify_end(ctx);
}
-static bool trans_depw_imm(DisasContext *ctx, arg_depw_imm *a)
+static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a)
{
unsigned rs = a->nz ? a->t : 0;
- unsigned len = 32 - a->clen;
+ unsigned len, width;
TCGv_reg dest, val;
+ if (!ctx->is_pa20 && a->d) {
+ return false;
+ }
if (a->c) {
nullify_over(ctx);
}
- if (a->cpos + len > 32) {
- len = 32 - a->cpos;
+
+ len = a->len;
+ width = a->d ? 64 : 32;
+ if (a->cpos + len > width) {
+ len = width - a->cpos;
}
dest = dest_gpr(ctx, a->t);
@@ -3445,26 +3465,26 @@ static bool trans_depw_imm(DisasContext *ctx, arg_depw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest);
}
return nullify_end(ctx);
}
-static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c,
- unsigned nz, unsigned clen, TCGv_reg val)
+static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c,
+ bool d, bool nz, unsigned len, TCGv_reg val)
{
unsigned rs = nz ? rt : 0;
- unsigned len = 32 - clen;
+ unsigned widthm1 = d ? 63 : 31;
TCGv_reg mask, tmp, shift, dest;
- unsigned msb = 1U << (len - 1);
+ target_ureg msb = 1ULL << (len - 1);
dest = dest_gpr(ctx, rt);
shift = tcg_temp_new();
tmp = tcg_temp_new();
/* Convert big-endian bit numbering in SAR to left-shift. */
- tcg_gen_andi_reg(shift, cpu_sar, 31);
- tcg_gen_xori_reg(shift, shift, 31);
+ tcg_gen_andi_reg(shift, cpu_sar, widthm1);
+ tcg_gen_xori_reg(shift, shift, widthm1);
mask = tcg_temp_new();
tcg_gen_movi_reg(mask, msb + (msb - 1));
@@ -3482,25 +3502,33 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c,
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (c) {
- ctx->null_cond = do_sed_cond(ctx, c, false, dest);
+ ctx->null_cond = do_sed_cond(ctx, c, d, dest);
}
return nullify_end(ctx);
}
-static bool trans_depw_sar(DisasContext *ctx, arg_depw_sar *a)
+static bool trans_dep_sar(DisasContext *ctx, arg_dep_sar *a)
{
+ if (!ctx->is_pa20 && a->d) {
+ return false;
+ }
if (a->c) {
nullify_over(ctx);
}
- return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_gpr(ctx, a->r));
+ return do_dep_sar(ctx, a->t, a->c, a->d, a->nz, a->len,
+ load_gpr(ctx, a->r));
}
-static bool trans_depwi_sar(DisasContext *ctx, arg_depwi_sar *a)
+static bool trans_depi_sar(DisasContext *ctx, arg_depi_sar *a)
{
+ if (!ctx->is_pa20 && a->d) {
+ return false;
+ }
if (a->c) {
nullify_over(ctx);
}
- return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, tcg_constant_reg(a->i));
+ return do_dep_sar(ctx, a->t, a->c, a->d, a->nz, a->len,
+ tcg_constant_reg(a->i));
}
static bool trans_be(DisasContext *ctx, arg_be *a)
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 41/61] target/hppa: Implement EXTRD
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (39 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 40/61] target/hppa: Implement DEPD, DEPDI Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 42/61] target/hppa: Implement SHRPD Richard Henderson
` (19 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 7 +++++--
target/hppa/translate.c | 34 +++++++++++++++++++++++-----------
2 files changed, 28 insertions(+), 13 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 12684b590e..7b51f39b9e 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -335,8 +335,11 @@ addbi 101011 ..... ..... ... ........... . . @rib_cf f=1
shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5
shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5
-extrw_sar 110100 r:5 t:5 c:3 10 se:1 00000 clen:5
-extrw_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 clen:5
+extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=0 len=%len5
+extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=1 len=%len6_8
+extr_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 ..... d=0 len=%len5
+extr_imm 110110 r:5 t:5 c:3 .. se:1 ..... ..... \
+ d=1 len=%len6_12 pos=%cpos6_11
dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=0 len=%len5
dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=1 len=%len6_8
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index b3d3506f94..974ed558d7 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3333,11 +3333,14 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a)
return nullify_end(ctx);
}
-static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a)
+static bool trans_extr_sar(DisasContext *ctx, arg_extr_sar *a)
{
- unsigned len = 32 - a->clen;
+ unsigned widthm1 = a->d ? 63 : 31;
TCGv_reg dest, src, tmp;
+ if (!ctx->is_pa20 && a->d) {
+ return false;
+ }
if (a->c) {
nullify_over(ctx);
}
@@ -3347,36 +3350,45 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a)
tmp = tcg_temp_new();
/* Recall that SAR is using big-endian bit numbering. */
- tcg_gen_andi_reg(tmp, cpu_sar, 31);
- tcg_gen_xori_reg(tmp, tmp, 31);
+ tcg_gen_andi_reg(tmp, cpu_sar, widthm1);
+ tcg_gen_xori_reg(tmp, tmp, widthm1);
if (a->se) {
tcg_gen_sar_reg(dest, src, tmp);
- tcg_gen_sextract_reg(dest, dest, 0, len);
+ tcg_gen_sextract_reg(dest, dest, 0, a->len);
} else {
tcg_gen_shr_reg(dest, src, tmp);
- tcg_gen_extract_reg(dest, dest, 0, len);
+ tcg_gen_extract_reg(dest, dest, 0, a->len);
}
save_gpr(ctx, a->t, dest);
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest);
}
return nullify_end(ctx);
}
-static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a)
+static bool trans_extr_imm(DisasContext *ctx, arg_extr_imm *a)
{
- unsigned len = 32 - a->clen;
- unsigned cpos = 31 - a->pos;
+ unsigned len, cpos, width;
TCGv_reg dest, src;
+ if (!ctx->is_pa20 && a->d) {
+ return false;
+ }
if (a->c) {
nullify_over(ctx);
}
+ len = a->len;
+ width = a->d ? 64 : 32;
+ cpos = width - 1 - a->pos;
+ if (cpos + len > width) {
+ len = width - cpos;
+ }
+
dest = dest_gpr(ctx, a->t);
src = load_gpr(ctx, a->r);
if (a->se) {
@@ -3389,7 +3401,7 @@ static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a)
/* Install the new nullification. */
cond_free(&ctx->null_cond);
if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, false, dest);
+ ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest);
}
return nullify_end(ctx);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 42/61] target/hppa: Implement SHRPD
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (40 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 41/61] target/hppa: Implement EXTRD Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 43/61] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM Richard Henderson
` (18 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 6 ++-
target/hppa/translate.c | 79 ++++++++++++++++++++++++++++------------
2 files changed, 60 insertions(+), 25 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 7b51f39b9e..6f0c3f6ea5 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -332,8 +332,10 @@ addbi 101011 ..... ..... ... ........... . . @rib_cf f=1
# Shift, Extract, Deposit
####
-shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5
-shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5
+shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5
+shrp_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 d=0
+shrp_imm 110100 r2:5 r1:5 c:3 0. 1 ..... t:5 \
+ d=1 cpos=%cpos6_11
extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=0 len=%len5
extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=1 len=%len6_8
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 974ed558d7..a23c44e3d6 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3258,32 +3258,56 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi *a)
return do_cbranch(ctx, a->disp, a->n, &cond);
}
-static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a)
+static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a)
{
- TCGv_reg dest;
+ TCGv_reg dest, tmp;
+ if (!ctx->is_pa20 && a->d) {
+ return false;
+ }
if (a->c) {
nullify_over(ctx);
}
dest = dest_gpr(ctx, a->t);
if (a->r1 == 0) {
- tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2));
- tcg_gen_shr_reg(dest, dest, cpu_sar);
+ if (a->d) {
+ tcg_gen_shr_reg(dest, dest, cpu_sar);
+ } else {
+ tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2));
+ tmp = tcg_temp_new();
+ tcg_gen_andi_reg(tmp, cpu_sar, 31);
+ tcg_gen_shr_reg(dest, dest, tmp);
+ }
} else if (a->r1 == a->r2) {
- TCGv_i32 t32 = tcg_temp_new_i32();
- TCGv_i32 s32 = tcg_temp_new_i32();
+ if (a->d) {
+ tcg_gen_rotr_reg(dest, load_gpr(ctx, a->r2), cpu_sar);
+ } else {
+ TCGv_i32 t32 = tcg_temp_new_i32();
+ TCGv_i32 s32 = tcg_temp_new_i32();
- tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2));
- tcg_gen_trunc_reg_i32(s32, cpu_sar);
- tcg_gen_rotr_i32(t32, t32, s32);
- tcg_gen_extu_i32_reg(dest, t32);
+ tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2));
+ tcg_gen_trunc_reg_i32(s32, cpu_sar);
+ tcg_gen_andi_i32(s32, s32, 31);
+ tcg_gen_rotr_i32(t32, t32, s32);
+ tcg_gen_extu_i32_reg(dest, t32);
+ }
+ } else if (a->d) {
+ TCGv_reg t = tcg_temp_new();
+ TCGv_reg n = tcg_temp_new();
+
+ tcg_gen_xori_reg(n, cpu_sar, 63);
+ tcg_gen_shl_reg(t, load_gpr(ctx, a->r2), n);
+ tcg_gen_shli_reg(t, t, 1);
+ tcg_gen_shr_reg(dest, load_gpr(ctx, a->r1), cpu_sar);
+ tcg_gen_or_reg(dest, dest, t);
} else {
TCGv_i64 t = tcg_temp_new_i64();
TCGv_i64 s = tcg_temp_new_i64();
tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1));
tcg_gen_extu_reg_i64(s, cpu_sar);
+ tcg_gen_andi_i64(s, s, 31);
tcg_gen_shr_i64(t, t, s);
tcg_gen_trunc_i64_reg(dest, t);
}
@@ -3297,31 +3321,40 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a)
return nullify_end(ctx);
}
-static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a)
+static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a)
{
- unsigned sa = 31 - a->cpos;
+ unsigned width, sa;
TCGv_reg dest, t2;
+ if (!ctx->is_pa20 && a->d) {
+ return false;
+ }
if (a->c) {
nullify_over(ctx);
}
+ width = a->d ? 64 : 32;
+ sa = width - 1 - a->cpos;
+
dest = dest_gpr(ctx, a->t);
t2 = load_gpr(ctx, a->r2);
if (a->r1 == 0) {
- tcg_gen_extract_reg(dest, t2, sa, 32 - sa);
- } else if (TARGET_REGISTER_BITS == 32) {
+ tcg_gen_extract_reg(dest, t2, sa, width - sa);
+ } else if (width == TARGET_REGISTER_BITS) {
tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa);
- } else if (a->r1 == a->r2) {
- TCGv_i32 t32 = tcg_temp_new_i32();
- tcg_gen_trunc_reg_i32(t32, t2);
- tcg_gen_rotri_i32(t32, t32, sa);
- tcg_gen_extu_i32_reg(dest, t32);
} else {
- TCGv_i64 t64 = tcg_temp_new_i64();
- tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]);
- tcg_gen_shri_i64(t64, t64, sa);
- tcg_gen_trunc_i64_reg(dest, t64);
+ assert(!a->d);
+ if (a->r1 == a->r2) {
+ TCGv_i32 t32 = tcg_temp_new_i32();
+ tcg_gen_trunc_reg_i32(t32, t2);
+ tcg_gen_rotri_i32(t32, t32, sa);
+ tcg_gen_extu_i32_reg(dest, t32);
+ } else {
+ TCGv_i64 t64 = tcg_temp_new_i64();
+ tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]);
+ tcg_gen_shri_i64(t64, t64, sa);
+ tcg_gen_trunc_i64_reg(dest, t64);
+ }
}
save_gpr(ctx, a->t, dest);
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 43/61] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (41 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 42/61] target/hppa: Implement SHRPD Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 44/61] target/hppa: Implement STDBY Richard Henderson
` (17 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 2 ++
target/hppa/translate.c | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 6f0c3f6ea5..ba7731b517 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -381,6 +381,8 @@ bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \
disp=%assemble_22
b_gate 111010 ..... ..... 001 ........... . . @bl
blr 111010 l:5 x:5 010 00000000000 n:1 0
+nopbts 111010 00000 00000 010 0---------1 0 1 # clrbts/popbts
+nopbts 111010 00000 ----- 010 00000000000 0 1 # pushbts/pushnom
bv 111010 b:5 x:5 110 00000000000 n:1 0
bve 111010 b:5 00000 110 10000000000 n:1 - l=0
bve 111010 b:5 00000 111 10000000000 n:1 - l=2
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index a23c44e3d6..56c0a4fea1 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3746,6 +3746,12 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a)
#endif
}
+static bool trans_nopbts(DisasContext *ctx, arg_nopbts *a)
+{
+ /* All branch target stack instructions implement as nop. */
+ return ctx->is_pa20;
+}
+
/*
* Float class 0
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 44/61] target/hppa: Implement STDBY
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (42 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 43/61] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 45/61] target/hppa: Implement IDTLBT, IITLBT Richard Henderson
` (16 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/helper.h | 5 ++
target/hppa/insns.decode | 1 +
target/hppa/op_helper.c | 178 +++++++++++++++++++++++++++++++++++++--
target/hppa/translate.c | 31 +++++++
4 files changed, 210 insertions(+), 5 deletions(-)
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index 647f043c85..9920d38ded 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -16,6 +16,11 @@ DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr)
DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tr)
DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr)
+DEF_HELPER_FLAGS_3(stdby_b, TCG_CALL_NO_WG, void, env, tl, tr)
+DEF_HELPER_FLAGS_3(stdby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr)
+DEF_HELPER_FLAGS_3(stdby_e, TCG_CALL_NO_WG, void, env, tl, tr)
+DEF_HELPER_FLAGS_3(stdby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr)
+
DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl)
DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tr, env, tl, i32, i32)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index ba7731b517..9d8c6a1a16 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -228,6 +228,7 @@ lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx size=3
sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2
sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3
stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0
+stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1 ..... disp=%im5_0
@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \
&ldst t=%rt64 disp=0 size=2
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index 837e2b3117..94c9ca5858 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -56,11 +56,11 @@ void HELPER(tcond)(CPUHPPAState *env, target_ureg cond)
}
}
-static void atomic_store_3(CPUHPPAState *env, target_ulong addr,
- uint32_t val, uintptr_t ra)
+static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr,
+ uint32_t val, uint32_t mask, uintptr_t ra)
{
int mmu_idx = cpu_mmu_index(env, 0);
- uint32_t old, new, cmp, mask, *haddr;
+ uint32_t old, new, cmp, *haddr;
void *vaddr;
vaddr = probe_access(env, addr, 3, MMU_DATA_STORE, mmu_idx, ra);
@@ -81,6 +81,35 @@ static void atomic_store_3(CPUHPPAState *env, target_ulong addr,
}
}
+static void atomic_store_mask64(CPUHPPAState *env, target_ulong addr,
+ uint64_t val, uint64_t mask,
+ int size, uintptr_t ra)
+{
+#ifdef CONFIG_ATOMIC64
+ int mmu_idx = cpu_mmu_index(env, 0);
+ uint64_t old, new, cmp, *haddr;
+ void *vaddr;
+
+ vaddr = probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, ra);
+ if (vaddr == NULL) {
+ cpu_loop_exit_atomic(env_cpu(env), ra);
+ }
+ haddr = (uint64_t *)((uintptr_t)vaddr & -8);
+
+ old = *haddr;
+ while (1) {
+ new = be32_to_cpu((cpu_to_be32(old) & ~mask) | (val & mask));
+ cmp = qatomic_cmpxchg__nocheck(haddr, old, new);
+ if (cmp == old) {
+ return;
+ }
+ old = cmp;
+ }
+#else
+ cpu_loop_exit_atomic(env_cpu(env), ra);
+#endif
+}
+
static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg val,
bool parallel, uintptr_t ra)
{
@@ -94,7 +123,7 @@ static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg val,
case 1:
/* The 3 byte store must appear atomic. */
if (parallel) {
- atomic_store_3(env, addr, val, ra);
+ atomic_store_mask32(env, addr, val, 0x00ffffffu, ra);
} else {
cpu_stb_data_ra(env, addr, val >> 16, ra);
cpu_stw_data_ra(env, addr + 1, val, ra);
@@ -106,6 +135,62 @@ static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg val,
}
}
+static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val,
+ bool parallel, uintptr_t ra)
+{
+ switch (addr & 7) {
+ case 7:
+ cpu_stb_data_ra(env, addr, val, ra);
+ break;
+ case 6:
+ cpu_stw_data_ra(env, addr, val, ra);
+ break;
+ case 5:
+ /* The 3 byte store must appear atomic. */
+ if (parallel) {
+ atomic_store_mask32(env, addr, val, 0x00ffffffu, ra);
+ } else {
+ cpu_stb_data_ra(env, addr, val >> 16, ra);
+ cpu_stw_data_ra(env, addr + 1, val, ra);
+ }
+ break;
+ case 4:
+ cpu_stl_data_ra(env, addr, val, ra);
+ break;
+ case 3:
+ /* The 5 byte store must appear atomic. */
+ if (parallel) {
+ atomic_store_mask64(env, addr, val, 0x000000ffffffffffull, 5, ra);
+ } else {
+ cpu_stb_data_ra(env, addr, val >> 32, ra);
+ cpu_stl_data_ra(env, addr + 1, val, ra);
+ }
+ break;
+ case 2:
+ /* The 6 byte store must appear atomic. */
+ if (parallel) {
+ atomic_store_mask64(env, addr, val, 0x0000ffffffffffffull, 6, ra);
+ } else {
+ cpu_stw_data_ra(env, addr, val >> 32, ra);
+ cpu_stl_data_ra(env, addr + 2, val, ra);
+ }
+ break;
+ case 1:
+ /* The 7 byte store must appear atomic. */
+ if (parallel) {
+ atomic_store_mask64(env, addr, val, 0x00ffffffffffffffull, 7, ra);
+ } else {
+ cpu_stb_data_ra(env, addr, val >> 48, ra);
+ cpu_stw_data_ra(env, addr + 1, val >> 32, ra);
+ cpu_stl_data_ra(env, addr + 3, val, ra);
+ }
+ break;
+ default:
+ cpu_stl_data_ra(env, addr, val, ra);
+ break;
+ }
+}
+
void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val)
{
do_stby_b(env, addr, val, false, GETPC());
@@ -117,6 +202,17 @@ void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr,
do_stby_b(env, addr, val, true, GETPC());
}
+void HELPER(stdby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val)
+{
+ do_stdby_b(env, addr, val, false, GETPC());
+}
+
+void HELPER(stdby_b_parallel)(CPUHPPAState *env, target_ulong addr,
+ target_ureg val)
+{
+ do_stdby_b(env, addr, val, true, GETPC());
+}
+
static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg val,
bool parallel, uintptr_t ra)
{
@@ -124,7 +220,68 @@ static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg val,
case 3:
/* The 3 byte store must appear atomic. */
if (parallel) {
- atomic_store_3(env, addr - 3, val, ra);
+ atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra);
+ } else {
+ cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
+ cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
+ }
+ break;
+ case 2:
+ cpu_stw_data_ra(env, addr - 2, val >> 16, ra);
+ break;
+ case 1:
+ cpu_stb_data_ra(env, addr - 1, val >> 24, ra);
+ break;
+ default:
+ /* Nothing is stored, but protection is checked and the
+ cacheline is marked dirty. */
+ probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra);
+ break;
+ }
+}
+
+static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val,
+ bool parallel, uintptr_t ra)
+{
+ switch (addr & 7) {
+ case 7:
+ /* The 7 byte store must appear atomic. */
+ if (parallel) {
+ atomic_store_mask64(env, addr - 7, val,
+ 0xffffffffffffff00ull, 7, ra);
+ } else {
+ cpu_stl_data_ra(env, addr - 7, val >> 32, ra);
+ cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
+ cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
+ }
+ break;
+ case 6:
+ /* The 6 byte store must appear atomic. */
+ if (parallel) {
+ atomic_store_mask64(env, addr - 6, val,
+ 0xffffffffffff0000ull, 6, ra);
+ } else {
+ cpu_stl_data_ra(env, addr - 6, val >> 32, ra);
+ cpu_stw_data_ra(env, addr - 2, val >> 16, ra);
+ }
+ break;
+ case 5:
+ /* The 5 byte store must appear atomic. */
+ if (parallel) {
+ atomic_store_mask64(env, addr - 5, val,
+ 0xffffffffff000000ull, 5, ra);
+ } else {
+ cpu_stl_data_ra(env, addr - 5, val >> 32, ra);
+ cpu_stb_data_ra(env, addr - 1, val >> 24, ra);
+ }
+ break;
+ case 4:
+ cpu_stl_data_ra(env, addr - 4, val >> 32, ra);
+ break;
+ case 3:
+ /* The 3 byte store must appear atomic. */
+ if (parallel) {
+ atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra);
} else {
cpu_stw_data_ra(env, addr - 3, val >> 16, ra);
cpu_stb_data_ra(env, addr - 1, val >> 8, ra);
@@ -155,6 +312,17 @@ void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr,
do_stby_e(env, addr, val, true, GETPC());
}
+void HELPER(stdby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val)
+{
+ do_stdby_e(env, addr, val, false, GETPC());
+}
+
+void HELPER(stdby_e_parallel)(CPUHPPAState *env, target_ulong addr,
+ target_ureg val)
+{
+ do_stdby_e(env, addr, val, true, GETPC());
+}
+
void HELPER(ldc_check)(target_ulong addr)
{
if (unlikely(addr & 0xf)) {
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 56c0a4fea1..4a0ae5a772 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3031,6 +3031,37 @@ static bool trans_stby(DisasContext *ctx, arg_stby *a)
return nullify_end(ctx);
}
+static bool trans_stdby(DisasContext *ctx, arg_stby *a)
+{
+ TCGv_reg ofs, val;
+ TCGv_tl addr;
+
+ nullify_over(ctx);
+
+ form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m,
+ ctx->mmu_idx == MMU_PHYS_IDX);
+ val = load_gpr(ctx, a->r);
+ if (a->a) {
+ if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
+ gen_helper_stdby_e_parallel(tcg_env, addr, val);
+ } else {
+ gen_helper_stdby_e(tcg_env, addr, val);
+ }
+ } else {
+ if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
+ gen_helper_stdby_b_parallel(tcg_env, addr, val);
+ } else {
+ gen_helper_stdby_b(tcg_env, addr, val);
+ }
+ }
+ if (a->m) {
+ tcg_gen_andi_reg(ofs, ofs, ~7);
+ save_gpr(ctx, a->b, ofs);
+ }
+
+ return nullify_end(ctx);
+}
+
static bool trans_lda(DisasContext *ctx, arg_ldst *a)
{
int hold_mmu_idx = ctx->mmu_idx;
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 45/61] target/hppa: Implement IDTLBT, IITLBT
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (43 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 44/61] target/hppa: Implement STDBY Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 46/61] target/hppa: Remove TARGET_REGISTER_BITS Richard Henderson
` (15 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Rename the existing insert tlb helpers to emphasize that they
are for pa1.1 cpus. Implement a combined i/d tlb for pa2.0.
Still missing is the new 'P' tlb bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/helper.h | 5 ++--
target/hppa/insns.decode | 4 +++
target/hppa/mem_helper.c | 63 +++++++++++++++++++++++++++++++++-------
target/hppa/translate.c | 35 ++++++++++++++++++----
4 files changed, 89 insertions(+), 18 deletions(-)
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index 9920d38ded..58b6754dbe 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -94,8 +94,9 @@ DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr)
DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr)
DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr)
DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr)
-DEF_HELPER_FLAGS_3(itlba, TCG_CALL_NO_RWG, void, env, tl, tr)
-DEF_HELPER_FLAGS_3(itlbp, TCG_CALL_NO_RWG, void, env, tl, tr)
+DEF_HELPER_FLAGS_3(itlba_pa11, TCG_CALL_NO_RWG, void, env, tl, tr)
+DEF_HELPER_FLAGS_3(itlbp_pa11, TCG_CALL_NO_RWG, void, env, tl, tr)
+DEF_HELPER_FLAGS_3(itlbt_pa20, TCG_CALL_NO_RWG, void, env, tr, tr)
DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tr, env, tl)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 9d8c6a1a16..db1b9f750f 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -152,6 +152,10 @@ ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \
# pcxl and pcxl2 Fast TLB Insert instructions
ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000
+# pa2.0 tlb insert instructions
+ixtlbt 000001 r2:5 r1:5 000 1100000 0 00000 # idtlbt
+ixtlbt 000001 r2:5 r1:5 000 0100000 0 00000 # iitlbt
+
pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1
pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \
sp=%assemble_sr3x data=0
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 169e878479..d6f46b18e9 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -312,7 +312,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
}
/* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */
-void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
+void HELPER(itlba_pa11)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
{
hppa_tlb_entry *empty = NULL;
int i;
@@ -338,15 +338,12 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
/* Note that empty->entry_valid == 0 already. */
empty->va_b = addr & TARGET_PAGE_MASK;
empty->va_e = empty->va_b + TARGET_PAGE_SIZE - 1;
- /*
- * FIXME: This is wrong, as this is a pa1.1 function.
- * But for the moment translate abs address for pa2.0.
- */
- empty->pa = hppa_abs_to_phys(env, extract32(reg, 5, 20) << TARGET_PAGE_BITS);
+ empty->pa = extract32(reg, 5, 20) << TARGET_PAGE_BITS;
trace_hppa_tlb_itlba(env, empty, empty->va_b, empty->va_e, empty->pa);
}
-static void set_access_bits(CPUHPPAState *env, hppa_tlb_entry *ent, target_ureg reg)
+static void set_access_bits_pa11(CPUHPPAState *env, hppa_tlb_entry *ent,
+ target_ureg reg)
{
ent->access_id = extract32(reg, 1, 18);
ent->u = extract32(reg, 19, 1);
@@ -362,7 +359,7 @@ static void set_access_bits(CPUHPPAState *env, hppa_tlb_entry *ent, target_ureg
}
/* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */
-void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
+void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
{
hppa_tlb_entry *ent = hppa_find_tlb(env, addr);
@@ -370,8 +367,54 @@ void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
qemu_log_mask(LOG_GUEST_ERROR, "ITLBP not following ITLBA\n");
return;
}
+ set_access_bits_pa11(env, ent, reg);
+}
- set_access_bits(env, ent, reg);
+void HELPER(itlbt_pa20)(CPUHPPAState *env, target_ureg r1, target_ureg r2)
+{
+ hppa_tlb_entry *ent, *empty = NULL;
+ vaddr va_b, va_e;
+ uint64_t page_size;
+
+ va_b = deposit64(env->cr[CR_IIAOQ], 32, 32, env->cr[CR_IIASQ]);
+ va_b &= TARGET_PAGE_MASK;
+ page_size = TARGET_PAGE_SIZE << (2 * (r1 & 0xf));
+ va_e = va_b + page_size - 1;
+
+ for (int i = 0; i < ARRAY_SIZE(env->tlb); ++i) {
+ ent = &env->tlb[i];
+ if (ent->entry_valid) {
+ if (ent->va_b <= va_e && va_b <= ent->va_e) {
+ hppa_flush_tlb_ent(env, ent, false);
+ empty = ent;
+ }
+ } else {
+ empty = ent;
+ }
+ }
+
+ /* If we didn't see an empty entry, evict one. */
+ ent = empty ? empty : hppa_alloc_tlb_ent(env);
+
+ ent->va_b = va_b;
+ ent->va_e = va_e;
+ ent->pa = (r1 << 7) & TARGET_PAGE_MASK;
+ ent->t = extract64(r2, 61, 1);
+ ent->d = extract64(r2, 60, 1);
+ ent->b = extract64(r2, 59, 1);
+ ent->ar_type = extract64(r2, 56, 3);
+ ent->ar_pl1 = extract64(r2, 54, 2);
+ ent->ar_pl2 = extract64(r2, 52, 2);
+ ent->u = extract64(r2, 51, 1);
+ /* o = bit 50 */
+ /* p = bit 49 */
+ ent->access_id = extract64(r2, 1, 31);
+ ent->entry_valid = 1;
+
+ trace_hppa_tlb_itlba(env, ent, ent->va_b, ent->va_e, ent->pa);
+ trace_hppa_tlb_itlbp(env, ent, ent->access_id, ent->u,
+ ent->ar_pl2, ent->ar_pl1, ent->ar_type,
+ ent->b, ent->d, ent->t);
}
/* Purge (Insn/Data) TLB. This is explicitly page-based, and is
@@ -520,7 +563,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env)
btlb->va_b = virt_page << TARGET_PAGE_BITS;
btlb->va_e = btlb->va_b + len * TARGET_PAGE_SIZE - 1;
btlb->pa = phys_page << TARGET_PAGE_BITS;
- set_access_bits(env, btlb, env->gr[20]);
+ set_access_bits_pa11(env, btlb, env->gr[20]);
btlb->t = 0;
btlb->d = 1;
} else {
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4a0ae5a772..44dcf310b6 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2493,6 +2493,9 @@ static bool trans_probe(DisasContext *ctx, arg_probe *a)
static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a)
{
+ if (ctx->is_pa20) {
+ return false;
+ }
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
TCGv_tl addr;
@@ -2503,9 +2506,9 @@ static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a)
form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false);
reg = load_gpr(ctx, a->r);
if (a->addr) {
- gen_helper_itlba(tcg_env, addr, reg);
+ gen_helper_itlba_pa11(tcg_env, addr, reg);
} else {
- gen_helper_itlbp(tcg_env, addr, reg);
+ gen_helper_itlbp_pa11(tcg_env, addr, reg);
}
/* Exit TB for TLB change if mmu is enabled. */
@@ -2551,6 +2554,9 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a)
*/
static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
{
+ if (ctx->is_pa20) {
+ return false;
+ }
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
TCGv_tl addr, atl, stl;
@@ -2562,8 +2568,6 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
* FIXME:
* if (not (pcxl or pcxl2))
* return gen_illegal(ctx);
- *
- * Note for future: these are 32-bit systems; no hppa64.
*/
atl = tcg_temp_new_tl();
@@ -2581,9 +2585,9 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
reg = load_gpr(ctx, a->r);
if (a->addr) {
- gen_helper_itlba(tcg_env, addr, reg);
+ gen_helper_itlba_pa11(tcg_env, addr, reg);
} else {
- gen_helper_itlbp(tcg_env, addr, reg);
+ gen_helper_itlbp_pa11(tcg_env, addr, reg);
}
/* Exit TB for TLB change if mmu is enabled. */
@@ -2594,6 +2598,25 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
#endif
}
+static bool trans_ixtlbt(DisasContext *ctx, arg_ixtlbt *a)
+{
+ if (!ctx->is_pa20) {
+ return false;
+ }
+ CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
+#ifndef CONFIG_USER_ONLY
+ nullify_over(ctx);
+
+ gen_helper_itlbt_pa20(tcg_env, load_gpr(ctx, a->r1), load_gpr(ctx, a->r2));
+
+ /* Exit TB for TLB change if mmu is enabled. */
+ if (ctx->tb_flags & PSW_C) {
+ ctx->base.is_jmp = DISAS_IAQ_N_STALE;
+ }
+ return nullify_end(ctx);
+#endif
+}
+
static bool trans_lpa(DisasContext *ctx, arg_ldst *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 46/61] target/hppa: Remove TARGET_REGISTER_BITS
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (44 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 45/61] target/hppa: Implement IDTLBT, IITLBT Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 47/61] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections Richard Henderson
` (14 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Rely only on TARGET_LONG_BITS, fixed at 64, and is_pa20.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu-param.h | 1 -
target/hppa/cpu.h | 50 ++++-------
target/hppa/helper.h | 49 +++++------
target/hppa/cpu.c | 2 +-
target/hppa/helper.c | 34 +++-----
target/hppa/int_helper.c | 17 ++--
target/hppa/machine.c | 9 --
target/hppa/mem_helper.c | 10 +--
target/hppa/op_helper.c | 30 +++----
target/hppa/sys_helper.c | 4 +-
target/hppa/translate.c | 184 ++++++++-------------------------------
11 files changed, 119 insertions(+), 271 deletions(-)
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index 2fb8e7924b..6746869a3b 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -9,7 +9,6 @@
#define HPPA_CPU_PARAM_H
#define TARGET_LONG_BITS 64
-#define TARGET_REGISTER_BITS 64
#if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32)
# define TARGET_PHYS_ADDR_SPACE_BITS 32
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 251f85444a..5ce05046c0 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -141,22 +141,10 @@
#define CR_IPSW 22
#define CR_EIRR 23
-#if TARGET_REGISTER_BITS == 32
-typedef uint32_t target_ureg;
-typedef int32_t target_sreg;
-#define TREG_FMT_lx "%08"PRIx32
-#define TREG_FMT_ld "%"PRId32
-#else
-typedef uint64_t target_ureg;
-typedef int64_t target_sreg;
-#define TREG_FMT_lx "%016"PRIx64
-#define TREG_FMT_ld "%"PRId64
-#endif
-
typedef struct {
uint64_t va_b;
uint64_t va_e;
- target_ureg pa;
+ target_ulong pa;
unsigned u : 1;
unsigned t : 1;
unsigned d : 1;
@@ -170,16 +158,16 @@ typedef struct {
} hppa_tlb_entry;
typedef struct CPUArchState {
- target_ureg iaoq_f; /* front */
- target_ureg iaoq_b; /* back, aka next instruction */
+ target_ulong iaoq_f; /* front */
+ target_ulong iaoq_b; /* back, aka next instruction */
- target_ureg gr[32];
+ target_ulong gr[32];
uint64_t fr[32];
uint64_t sr[8]; /* stored shifted into place for gva */
- target_ureg psw; /* All psw bits except the following: */
- target_ureg psw_n; /* boolean */
- target_sreg psw_v; /* in most significant bit */
+ target_ulong psw; /* All psw bits except the following: */
+ target_ulong psw_n; /* boolean */
+ target_long psw_v; /* in most significant bit */
/* Splitting the carry-borrow field into the MSB and "the rest", allows
* for "the rest" to be deleted when it is unused, but the MSB is in use.
@@ -188,8 +176,8 @@ typedef struct CPUArchState {
* host has the appropriate add-with-carry insn to compute the msb).
* Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
*/
- target_ureg psw_cb; /* in least significant bit of next nibble */
- target_ureg psw_cb_msb; /* boolean */
+ target_ulong psw_cb; /* in least significant bit of next nibble */
+ target_ulong psw_cb_msb; /* boolean */
uint64_t iasq_f;
uint64_t iasq_b;
@@ -197,9 +185,9 @@ typedef struct CPUArchState {
uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */
float_status fp_status;
- target_ureg cr[32]; /* control registers */
- target_ureg cr_back[2]; /* back of cr17/cr18 */
- target_ureg shadow[7]; /* shadow registers */
+ target_ulong cr[32]; /* control registers */
+ target_ulong cr_back[2]; /* back of cr17/cr18 */
+ target_ulong shadow[7]; /* shadow registers */
/*
* ??? The number of entries isn't specified by the architecture.
@@ -257,8 +245,8 @@ void hppa_translate_init(void);
#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
-static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
- target_ureg off)
+static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t spc,
+ target_ulong off)
{
#ifdef CONFIG_USER_ONLY
return off;
@@ -269,7 +257,7 @@ static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
}
static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
- target_ureg off)
+ target_ulong off)
{
return hppa_form_gva_psw(env->psw, spc, off);
}
@@ -313,8 +301,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
which is the primary case we care about -- using goto_tb within a page.
Failure is indicated by a zero difference. */
if (env->iasq_f == env->iasq_b) {
- target_sreg diff = env->iaoq_b - env->iaoq_f;
- if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) {
+ target_long diff = env->iaoq_b - env->iaoq_f;
+ if (diff == (int32_t)diff) {
*cs_base |= (uint32_t)diff;
}
}
@@ -328,8 +316,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
*pflags = flags;
}
-target_ureg cpu_hppa_get_psw(CPUHPPAState *env);
-void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg);
+target_ulong cpu_hppa_get_psw(CPUHPPAState *env);
+void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong);
void cpu_hppa_loaded_fr0(CPUHPPAState *env);
#ifdef CONFIG_USER_ONLY
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index 58b6754dbe..4b2c66316f 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -1,29 +1,20 @@
-#if TARGET_REGISTER_BITS == 64
-# define dh_alias_tr i64
-# define dh_typecode_tr dh_typecode_i64
-#else
-# define dh_alias_tr i32
-# define dh_typecode_tr dh_typecode_i32
-#endif
-#define dh_ctype_tr target_ureg
-
DEF_HELPER_2(excp, noreturn, env, int)
-DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tr)
-DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tr)
+DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl)
+DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl)
-DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tr)
-DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr)
-DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tr)
-DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr)
+DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tl)
-DEF_HELPER_FLAGS_3(stdby_b, TCG_CALL_NO_WG, void, env, tl, tr)
-DEF_HELPER_FLAGS_3(stdby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr)
-DEF_HELPER_FLAGS_3(stdby_e, TCG_CALL_NO_WG, void, env, tl, tr)
-DEF_HELPER_FLAGS_3(stdby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr)
+DEF_HELPER_FLAGS_3(stdby_b, TCG_CALL_NO_WG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(stdby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(stdby_e, TCG_CALL_NO_WG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(stdby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tl)
DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl)
-DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tr, env, tl, i32, i32)
+DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tl, env, tl, i32, i32)
DEF_HELPER_FLAGS_1(loaded_fr0, TCG_CALL_NO_RWG, void, env)
@@ -82,7 +73,7 @@ DEF_HELPER_FLAGS_4(fmpynfadd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
-DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tr)
+DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tl)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(halt, noreturn, env)
@@ -90,16 +81,16 @@ DEF_HELPER_1(reset, noreturn, env)
DEF_HELPER_1(getshadowregs, void, env)
DEF_HELPER_1(rfi, void, env)
DEF_HELPER_1(rfi_r, void, env)
-DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr)
-DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr)
-DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr)
-DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr)
-DEF_HELPER_FLAGS_3(itlba_pa11, TCG_CALL_NO_RWG, void, env, tl, tr)
-DEF_HELPER_FLAGS_3(itlbp_pa11, TCG_CALL_NO_RWG, void, env, tl, tr)
-DEF_HELPER_FLAGS_3(itlbt_pa20, TCG_CALL_NO_RWG, void, env, tr, tr)
+DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tl, env, tl)
+DEF_HELPER_FLAGS_3(itlba_pa11, TCG_CALL_NO_RWG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(itlbp_pa11, TCG_CALL_NO_RWG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(itlbt_pa20, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env)
-DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tr, env, tl)
+DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tl, env, tl)
DEF_HELPER_FLAGS_1(change_prot_id, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_1(diag_btlb, void, env)
#endif
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index bbb6080e2d..5654061a69 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -77,7 +77,7 @@ static void hppa_restore_state_to_opc(CPUState *cs,
HPPACPU *cpu = HPPA_CPU(cs);
cpu->env.iaoq_f = data[0];
- if (data[1] != (target_ureg)-1) {
+ if (data[1] != (target_ulong)-1) {
cpu->env.iaoq_b = data[1];
}
/*
diff --git a/target/hppa/helper.c b/target/hppa/helper.c
index 04cdbafe9d..f112648764 100644
--- a/target/hppa/helper.c
+++ b/target/hppa/helper.c
@@ -25,31 +25,25 @@
#include "exec/helper-proto.h"
#include "qemu/qemu-print.h"
-target_ureg cpu_hppa_get_psw(CPUHPPAState *env)
+target_ulong cpu_hppa_get_psw(CPUHPPAState *env)
{
- target_ureg psw;
- target_ureg mask1 = (target_ureg)-1 / 0xf;
- target_ureg maskf = (target_ureg)-1 / 0xffff * 0xf;
+ target_ulong psw;
+ target_ulong mask1 = (target_ulong)-1 / 0xf;
+ target_ulong maskf = (target_ulong)-1 / 0xffff * 0xf;
/* Fold carry bits down to 8 consecutive bits. */
/* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^i^^^j^^^k^^^l^^^m^^^n^^^o^^^p^^^^ */
- /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^^ */
psw = (env->psw_cb >> 4) & mask1;
/* .......b...c...d...e...f...g...h...i...j...k...l...m...n...o...p */
- /* .......b...c...d...e...f...g...h */
psw |= psw >> 3;
/* .......b..bc..cd..de..ef..fg..gh..hi..ij..jk..kl..lm..mn..no..op */
- /* .......b..bc..cd..de..ef..fg..gh */
psw |= psw >> 6;
psw &= maskf;
/* .............bcd............efgh............ijkl............mnop */
- /* .............bcd............efgh */
psw |= psw >> 12;
/* .............bcd.........bcdefgh........efghijkl........ijklmnop */
- /* .............bcd.........bcdefgh */
- psw |= env->psw_cb_msb << (TARGET_REGISTER_BITS == 64 ? 39 : 7);
+ psw |= env->psw_cb_msb << 39;
/* .............bcd........abcdefgh........efghijkl........ijklmnop */
- /* .............bcd........abcdefgh */
/* For hppa64, the two 8-bit fields are discontiguous. */
if (env_archcpu(env)->is_pa20) {
@@ -65,11 +59,11 @@ target_ureg cpu_hppa_get_psw(CPUHPPAState *env)
return psw;
}
-void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
+void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw)
{
uint64_t reserved;
- target_ureg old_psw = env->psw;
- target_ureg cb = 0;
+ target_ulong old_psw = env->psw;
+ target_ulong cb = 0;
/* Do not allow reserved bits to be set. */
if (env_archcpu(env)->is_pa20) {
@@ -87,9 +81,6 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
env->psw_n = (psw / PSW_N) & 1;
env->psw_v = -((psw / PSW_V) & 1);
-#if TARGET_REGISTER_BITS == 32
- env->psw_cb_msb = (psw >> 15) & 1;
-#else
env->psw_cb_msb = (psw >> 39) & 1;
cb |= ((psw >> 38) & 1) << 60;
cb |= ((psw >> 37) & 1) << 56;
@@ -99,7 +90,6 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
cb |= ((psw >> 33) & 1) << 40;
cb |= ((psw >> 32) & 1) << 36;
cb |= ((psw >> 15) & 1) << 32;
-#endif
cb |= ((psw >> 14) & 1) << 28;
cb |= ((psw >> 13) & 1) << 24;
cb |= ((psw >> 12) & 1) << 20;
@@ -121,8 +111,8 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
HPPACPU *cpu = HPPA_CPU(cs);
CPUHPPAState *env = &cpu->env;
- target_ureg psw = cpu_hppa_get_psw(env);
- target_ureg psw_cb;
+ target_ulong psw = cpu_hppa_get_psw(env);
+ target_ulong psw_cb;
char psw_c[20];
int i, w;
uint64_t m;
@@ -155,8 +145,8 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
psw_c[16] = (psw & PSW_D ? 'D' : '-');
psw_c[17] = (psw & PSW_I ? 'I' : '-');
psw_c[18] = '\0';
- psw_cb = ((env->psw_cb >> 4) & ((target_ureg)-1 / 0xf))
- | (env->psw_cb_msb << (TARGET_REGISTER_BITS - 4));
+ psw_cb = ((env->psw_cb >> 4) & 0x1111111111111111ull)
+ | (env->psw_cb_msb << 60);
qemu_fprintf(f, "PSW %0*" PRIx64 " CB %0*" PRIx64 " %s\n",
w, m & psw, w, m & psw_cb, psw_c);
diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c
index 3ab9934a1d..f355c4c76b 100644
--- a/target/hppa/int_helper.c
+++ b/target/hppa/int_helper.c
@@ -52,9 +52,9 @@ static void io_eir_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
HPPACPU *cpu = opaque;
- int le_bit = ~data & (TARGET_REGISTER_BITS - 1);
+ int le_bit = ~data & 31;
- cpu->env.cr[CR_EIRR] |= (target_ureg)1 << le_bit;
+ cpu->env.cr[CR_EIRR] |= (target_ulong)1 << le_bit;
eval_interrupt(cpu);
}
@@ -73,7 +73,7 @@ void hppa_cpu_alarm_timer(void *opaque)
io_eir_write(opaque, 0, 0, 4);
}
-void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val)
+void HELPER(write_eirr)(CPUHPPAState *env, target_ulong val)
{
env->cr[CR_EIRR] &= ~val;
qemu_mutex_lock_iothread();
@@ -81,7 +81,7 @@ void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val)
qemu_mutex_unlock_iothread();
}
-void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val)
+void HELPER(write_eiem)(CPUHPPAState *env, target_ulong val)
{
env->cr[CR_EIEM] = val;
qemu_mutex_lock_iothread();
@@ -94,12 +94,11 @@ void hppa_cpu_do_interrupt(CPUState *cs)
HPPACPU *cpu = HPPA_CPU(cs);
CPUHPPAState *env = &cpu->env;
int i = cs->exception_index;
- target_ureg iaoq_f = env->iaoq_f;
- target_ureg iaoq_b = env->iaoq_b;
+ target_ulong iaoq_f = env->iaoq_f;
+ target_ulong iaoq_b = env->iaoq_b;
uint64_t iasq_f = env->iasq_f;
uint64_t iasq_b = env->iasq_b;
-
- target_ureg old_psw;
+ target_ulong old_psw;
/* As documented in pa2.0 -- interruption handling. */
/* step 1 */
@@ -240,7 +239,7 @@ void hppa_cpu_do_interrupt(CPUState *cs)
name = unknown;
}
qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx
- " -> " TREG_FMT_lx " " TARGET_FMT_lx "\n",
+ " -> " TARGET_FMT_lx " " TARGET_FMT_lx "\n",
++count, name,
hppa_form_gva(env, iasq_f, iaoq_f),
hppa_form_gva(env, iasq_b, iaoq_b),
diff --git a/target/hppa/machine.c b/target/hppa/machine.c
index 0c0bba68c0..ab34b72910 100644
--- a/target/hppa/machine.c
+++ b/target/hppa/machine.c
@@ -21,21 +21,12 @@
#include "cpu.h"
#include "migration/cpu.h"
-#if TARGET_REGISTER_BITS == 64
#define qemu_put_betr qemu_put_be64
#define qemu_get_betr qemu_get_be64
#define VMSTATE_UINTTR_V(_f, _s, _v) \
VMSTATE_UINT64_V(_f, _s, _v)
#define VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v)
-#else
-#define qemu_put_betr qemu_put_be32
-#define qemu_get_betr qemu_get_be32
-#define VMSTATE_UINTTR_V(_f, _s, _v) \
- VMSTATE_UINT32_V(_f, _s, _v)
-#define VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, _v) \
- VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v)
-#endif
#define VMSTATE_UINTTR(_f, _s) \
VMSTATE_UINTTR_V(_f, _s, 0)
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index d6f46b18e9..96fc3103f8 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -312,7 +312,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
}
/* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */
-void HELPER(itlba_pa11)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
+void HELPER(itlba_pa11)(CPUHPPAState *env, target_ulong addr, target_ulong reg)
{
hppa_tlb_entry *empty = NULL;
int i;
@@ -343,7 +343,7 @@ void HELPER(itlba_pa11)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
}
static void set_access_bits_pa11(CPUHPPAState *env, hppa_tlb_entry *ent,
- target_ureg reg)
+ target_ulong reg)
{
ent->access_id = extract32(reg, 1, 18);
ent->u = extract32(reg, 19, 1);
@@ -359,7 +359,7 @@ static void set_access_bits_pa11(CPUHPPAState *env, hppa_tlb_entry *ent,
}
/* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */
-void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
+void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong addr, target_ulong reg)
{
hppa_tlb_entry *ent = hppa_find_tlb(env, addr);
@@ -370,7 +370,7 @@ void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
set_access_bits_pa11(env, ent, reg);
}
-void HELPER(itlbt_pa20)(CPUHPPAState *env, target_ureg r1, target_ureg r2)
+void HELPER(itlbt_pa20)(CPUHPPAState *env, target_ulong r1, target_ulong r2)
{
hppa_tlb_entry *ent, *empty = NULL;
vaddr va_b, va_e;
@@ -471,7 +471,7 @@ void HELPER(change_prot_id)(CPUHPPAState *env)
cpu_hppa_change_prot_id(env);
}
-target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulong addr)
+target_ulong HELPER(lpa)(CPUHPPAState *env, target_ulong addr)
{
hwaddr phys;
int prot, excp;
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index 94c9ca5858..0bccca1e11 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -42,14 +42,14 @@ G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra)
cpu_loop_exit_restore(cs, ra);
}
-void HELPER(tsv)(CPUHPPAState *env, target_ureg cond)
+void HELPER(tsv)(CPUHPPAState *env, target_ulong cond)
{
- if (unlikely((target_sreg)cond < 0)) {
+ if (unlikely((target_long)cond < 0)) {
hppa_dynamic_excp(env, EXCP_OVERFLOW, GETPC());
}
}
-void HELPER(tcond)(CPUHPPAState *env, target_ureg cond)
+void HELPER(tcond)(CPUHPPAState *env, target_ulong cond)
{
if (unlikely(cond)) {
hppa_dynamic_excp(env, EXCP_COND, GETPC());
@@ -110,7 +110,7 @@ static void atomic_store_mask64(CPUHPPAState *env, target_ulong addr,
#endif
}
-static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg val,
+static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong val,
bool parallel, uintptr_t ra)
{
switch (addr & 3) {
@@ -191,29 +191,29 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val,
}
}
-void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val)
+void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val)
{
do_stby_b(env, addr, val, false, GETPC());
}
void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr,
- target_ureg val)
+ target_ulong val)
{
do_stby_b(env, addr, val, true, GETPC());
}
-void HELPER(stdby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val)
+void HELPER(stdby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val)
{
do_stdby_b(env, addr, val, false, GETPC());
}
void HELPER(stdby_b_parallel)(CPUHPPAState *env, target_ulong addr,
- target_ureg val)
+ target_ulong val)
{
do_stdby_b(env, addr, val, true, GETPC());
}
-static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg val,
+static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong val,
bool parallel, uintptr_t ra)
{
switch (addr & 3) {
@@ -301,24 +301,24 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val,
}
}
-void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val)
+void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val)
{
do_stby_e(env, addr, val, false, GETPC());
}
void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr,
- target_ureg val)
+ target_ulong val)
{
do_stby_e(env, addr, val, true, GETPC());
}
-void HELPER(stdby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val)
+void HELPER(stdby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val)
{
do_stdby_e(env, addr, val, false, GETPC());
}
void HELPER(stdby_e_parallel)(CPUHPPAState *env, target_ulong addr,
- target_ureg val)
+ target_ulong val)
{
do_stdby_e(env, addr, val, true, GETPC());
}
@@ -332,7 +332,7 @@ void HELPER(ldc_check)(target_ulong addr)
}
}
-target_ureg HELPER(probe)(CPUHPPAState *env, target_ulong addr,
+target_ulong HELPER(probe)(CPUHPPAState *env, target_ulong addr,
uint32_t level, uint32_t want)
{
#ifdef CONFIG_USER_ONLY
@@ -364,7 +364,7 @@ target_ureg HELPER(probe)(CPUHPPAState *env, target_ulong addr,
#endif
}
-target_ureg HELPER(read_interval_timer)(void)
+target_ulong HELPER(read_interval_timer)(void)
{
#ifdef CONFIG_USER_ONLY
/* In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist.
diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c
index f0dd5a08e7..bb57413199 100644
--- a/target/hppa/sys_helper.c
+++ b/target/hppa/sys_helper.c
@@ -24,7 +24,7 @@
#include "qemu/timer.h"
#include "sysemu/runstate.h"
-void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val)
+void HELPER(write_interval_timer)(CPUHPPAState *env, target_ulong val)
{
HPPACPU *cpu = env_archcpu(env);
uint64_t current = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
@@ -58,7 +58,7 @@ void HELPER(reset)(CPUHPPAState *env)
helper_excp(env, EXCP_HLT);
}
-target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm)
+target_ulong HELPER(swap_system_mask)(CPUHPPAState *env, target_ulong nsm)
{
target_ulong psw = env->psw;
/*
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 44dcf310b6..46a9e83508 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -40,21 +40,10 @@
#undef tcg_temp_new
#undef tcg_global_mem_new
-#if TARGET_LONG_BITS == 64
#define TCGv_tl TCGv_i64
#define tcg_temp_new_tl tcg_temp_new_i64
-#if TARGET_REGISTER_BITS == 64
#define tcg_gen_extu_reg_tl tcg_gen_mov_i64
-#else
-#define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64
-#endif
-#else
-#define TCGv_tl TCGv_i32
-#define tcg_temp_new_tl tcg_temp_new_i32
-#define tcg_gen_extu_reg_tl tcg_gen_mov_i32
-#endif
-#if TARGET_REGISTER_BITS == 64
#define TCGv_reg TCGv_i64
#define tcg_temp_new tcg_temp_new_i64
@@ -147,98 +136,6 @@
#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64
#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64
#define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr
-#else
-#define TCGv_reg TCGv_i32
-#define tcg_temp_new tcg_temp_new_i32
-#define tcg_global_mem_new tcg_global_mem_new_i32
-
-#define tcg_gen_movi_reg tcg_gen_movi_i32
-#define tcg_gen_mov_reg tcg_gen_mov_i32
-#define tcg_gen_ld8u_reg tcg_gen_ld8u_i32
-#define tcg_gen_ld8s_reg tcg_gen_ld8s_i32
-#define tcg_gen_ld16u_reg tcg_gen_ld16u_i32
-#define tcg_gen_ld16s_reg tcg_gen_ld16s_i32
-#define tcg_gen_ld32u_reg tcg_gen_ld_i32
-#define tcg_gen_ld32s_reg tcg_gen_ld_i32
-#define tcg_gen_ld_reg tcg_gen_ld_i32
-#define tcg_gen_st8_reg tcg_gen_st8_i32
-#define tcg_gen_st16_reg tcg_gen_st16_i32
-#define tcg_gen_st32_reg tcg_gen_st32_i32
-#define tcg_gen_st_reg tcg_gen_st_i32
-#define tcg_gen_add_reg tcg_gen_add_i32
-#define tcg_gen_addi_reg tcg_gen_addi_i32
-#define tcg_gen_sub_reg tcg_gen_sub_i32
-#define tcg_gen_neg_reg tcg_gen_neg_i32
-#define tcg_gen_subfi_reg tcg_gen_subfi_i32
-#define tcg_gen_subi_reg tcg_gen_subi_i32
-#define tcg_gen_and_reg tcg_gen_and_i32
-#define tcg_gen_andi_reg tcg_gen_andi_i32
-#define tcg_gen_or_reg tcg_gen_or_i32
-#define tcg_gen_ori_reg tcg_gen_ori_i32
-#define tcg_gen_xor_reg tcg_gen_xor_i32
-#define tcg_gen_xori_reg tcg_gen_xori_i32
-#define tcg_gen_not_reg tcg_gen_not_i32
-#define tcg_gen_shl_reg tcg_gen_shl_i32
-#define tcg_gen_shli_reg tcg_gen_shli_i32
-#define tcg_gen_shr_reg tcg_gen_shr_i32
-#define tcg_gen_shri_reg tcg_gen_shri_i32
-#define tcg_gen_sar_reg tcg_gen_sar_i32
-#define tcg_gen_sari_reg tcg_gen_sari_i32
-#define tcg_gen_brcond_reg tcg_gen_brcond_i32
-#define tcg_gen_brcondi_reg tcg_gen_brcondi_i32
-#define tcg_gen_setcond_reg tcg_gen_setcond_i32
-#define tcg_gen_setcondi_reg tcg_gen_setcondi_i32
-#define tcg_gen_mul_reg tcg_gen_mul_i32
-#define tcg_gen_muli_reg tcg_gen_muli_i32
-#define tcg_gen_div_reg tcg_gen_div_i32
-#define tcg_gen_rem_reg tcg_gen_rem_i32
-#define tcg_gen_divu_reg tcg_gen_divu_i32
-#define tcg_gen_remu_reg tcg_gen_remu_i32
-#define tcg_gen_discard_reg tcg_gen_discard_i32
-#define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32
-#define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32
-#define tcg_gen_extu_i32_reg tcg_gen_mov_i32
-#define tcg_gen_ext_i32_reg tcg_gen_mov_i32
-#define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64
-#define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64
-#define tcg_gen_ext8u_reg tcg_gen_ext8u_i32
-#define tcg_gen_ext8s_reg tcg_gen_ext8s_i32
-#define tcg_gen_ext16u_reg tcg_gen_ext16u_i32
-#define tcg_gen_ext16s_reg tcg_gen_ext16s_i32
-#define tcg_gen_ext32u_reg tcg_gen_mov_i32
-#define tcg_gen_ext32s_reg tcg_gen_mov_i32
-#define tcg_gen_bswap16_reg tcg_gen_bswap16_i32
-#define tcg_gen_bswap32_reg tcg_gen_bswap32_i32
-#define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64
-#define tcg_gen_andc_reg tcg_gen_andc_i32
-#define tcg_gen_eqv_reg tcg_gen_eqv_i32
-#define tcg_gen_nand_reg tcg_gen_nand_i32
-#define tcg_gen_nor_reg tcg_gen_nor_i32
-#define tcg_gen_orc_reg tcg_gen_orc_i32
-#define tcg_gen_clz_reg tcg_gen_clz_i32
-#define tcg_gen_ctz_reg tcg_gen_ctz_i32
-#define tcg_gen_clzi_reg tcg_gen_clzi_i32
-#define tcg_gen_ctzi_reg tcg_gen_ctzi_i32
-#define tcg_gen_clrsb_reg tcg_gen_clrsb_i32
-#define tcg_gen_ctpop_reg tcg_gen_ctpop_i32
-#define tcg_gen_rotl_reg tcg_gen_rotl_i32
-#define tcg_gen_rotli_reg tcg_gen_rotli_i32
-#define tcg_gen_rotr_reg tcg_gen_rotr_i32
-#define tcg_gen_rotri_reg tcg_gen_rotri_i32
-#define tcg_gen_deposit_reg tcg_gen_deposit_i32
-#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32
-#define tcg_gen_extract_reg tcg_gen_extract_i32
-#define tcg_gen_sextract_reg tcg_gen_sextract_i32
-#define tcg_gen_extract2_reg tcg_gen_extract2_i32
-#define tcg_constant_reg tcg_constant_i32
-#define tcg_gen_movcond_reg tcg_gen_movcond_i32
-#define tcg_gen_add2_reg tcg_gen_add2_i32
-#define tcg_gen_sub2_reg tcg_gen_sub2_i32
-#define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32
-#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32
-#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32
-#define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr
-#endif /* TARGET_REGISTER_BITS */
typedef struct DisasCond {
TCGCond c;
@@ -249,9 +146,9 @@ typedef struct DisasContext {
DisasContextBase base;
CPUState *cs;
- target_ureg iaoq_f;
- target_ureg iaoq_b;
- target_ureg iaoq_n;
+ uint64_t iaoq_f;
+ uint64_t iaoq_b;
+ uint64_t iaoq_n;
TCGv_reg iaoq_n_var;
DisasCond null_cond;
@@ -727,7 +624,7 @@ static bool nullify_end(DisasContext *ctx)
return true;
}
-static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval)
+static void copy_iaoq_entry(TCGv_reg dest, uint64_t ival, TCGv_reg vval)
{
if (unlikely(ival == -1)) {
tcg_gen_mov_reg(dest, vval);
@@ -736,7 +633,7 @@ static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval)
}
}
-static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp)
+static inline uint64_t iaoq_dest(DisasContext *ctx, int64_t disp)
{
return ctx->iaoq_f + disp + 8;
}
@@ -781,14 +678,14 @@ static bool gen_illegal(DisasContext *ctx)
} while (0)
#endif
-static target_ureg gva_offset_mask(DisasContext *ctx)
+static uint64_t gva_offset_mask(DisasContext *ctx)
{
return (ctx->tb_flags & PSW_W
? MAKE_64BIT_MASK(0, 62)
: MAKE_64BIT_MASK(0, 32));
}
-static bool use_goto_tb(DisasContext *ctx, target_ureg dest)
+static bool use_goto_tb(DisasContext *ctx, uint64_t dest)
{
return translator_use_goto_tb(&ctx->base, dest);
}
@@ -804,7 +701,7 @@ static bool use_nullify_skip(DisasContext *ctx)
}
static void gen_goto_tb(DisasContext *ctx, int which,
- target_ureg f, target_ureg b)
+ uint64_t f, uint64_t b)
{
if (f != -1 && b != -1 && use_goto_tb(ctx, f)) {
tcg_gen_goto_tb(which);
@@ -831,7 +728,7 @@ static bool cond_need_cb(int c)
/* Need extensions from TCGv_i32 to TCGv_reg. */
static bool cond_need_ext(DisasContext *ctx, bool d)
{
- return TARGET_REGISTER_BITS == 64 && !(ctx->is_pa20 && d);
+ return !(ctx->is_pa20 && d);
}
/*
@@ -882,7 +779,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
tcg_gen_and_reg(tmp, tmp, res);
tcg_gen_ext32u_reg(tmp, tmp);
} else {
- tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1);
+ tcg_gen_sari_reg(tmp, tmp, 63);
tcg_gen_and_reg(tmp, tmp, res);
}
cond = cond_make_0_tmp(TCG_COND_EQ, tmp);
@@ -1078,7 +975,7 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_reg res,
{
DisasCond cond;
TCGv_reg tmp, cb = NULL;
- target_ureg d_repl = d ? 0x0000000100000001ull : 1;
+ uint64_t d_repl = d ? 0x0000000100000001ull : 1;
if (cf & 8) {
/* Since we want to test lots of carry-out bits all at once, do not
@@ -1509,7 +1406,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base)
#endif
static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs,
- unsigned rb, unsigned rx, int scale, target_sreg disp,
+ unsigned rb, unsigned rx, int scale, int64_t disp,
unsigned sp, int modify, bool is_phys)
{
TCGv_reg base = load_gpr(ctx, rb);
@@ -1545,7 +1442,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs,
* = 0 for no base register update.
*/
static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
- unsigned rx, int scale, target_sreg disp,
+ unsigned rx, int scale, int64_t disp,
unsigned sp, int modify, MemOp mop)
{
TCGv_reg ofs;
@@ -1563,7 +1460,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
}
static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,
- unsigned rx, int scale, target_sreg disp,
+ unsigned rx, int scale, int64_t disp,
unsigned sp, int modify, MemOp mop)
{
TCGv_reg ofs;
@@ -1581,7 +1478,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,
}
static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,
- unsigned rx, int scale, target_sreg disp,
+ unsigned rx, int scale, int64_t disp,
unsigned sp, int modify, MemOp mop)
{
TCGv_reg ofs;
@@ -1599,7 +1496,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,
}
static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
- unsigned rx, int scale, target_sreg disp,
+ unsigned rx, int scale, int64_t disp,
unsigned sp, int modify, MemOp mop)
{
TCGv_reg ofs;
@@ -1616,16 +1513,11 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
}
}
-#if TARGET_REGISTER_BITS == 64
#define do_load_reg do_load_64
#define do_store_reg do_store_64
-#else
-#define do_load_reg do_load_32
-#define do_store_reg do_store_32
-#endif
static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,
- unsigned rx, int scale, target_sreg disp,
+ unsigned rx, int scale, int64_t disp,
unsigned sp, int modify, MemOp mop)
{
TCGv_reg dest;
@@ -1646,7 +1538,7 @@ static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,
}
static bool do_floadw(DisasContext *ctx, unsigned rt, unsigned rb,
- unsigned rx, int scale, target_sreg disp,
+ unsigned rx, int scale, int64_t disp,
unsigned sp, int modify)
{
TCGv_i32 tmp;
@@ -1671,7 +1563,7 @@ static bool trans_fldw(DisasContext *ctx, arg_ldst *a)
}
static bool do_floadd(DisasContext *ctx, unsigned rt, unsigned rb,
- unsigned rx, int scale, target_sreg disp,
+ unsigned rx, int scale, int64_t disp,
unsigned sp, int modify)
{
TCGv_i64 tmp;
@@ -1696,7 +1588,7 @@ static bool trans_fldd(DisasContext *ctx, arg_ldst *a)
}
static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb,
- target_sreg disp, unsigned sp,
+ int64_t disp, unsigned sp,
int modify, MemOp mop)
{
nullify_over(ctx);
@@ -1705,7 +1597,7 @@ static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb,
}
static bool do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb,
- unsigned rx, int scale, target_sreg disp,
+ unsigned rx, int scale, int64_t disp,
unsigned sp, int modify)
{
TCGv_i32 tmp;
@@ -1725,7 +1617,7 @@ static bool trans_fstw(DisasContext *ctx, arg_ldst *a)
}
static bool do_fstored(DisasContext *ctx, unsigned rt, unsigned rb,
- unsigned rx, int scale, target_sreg disp,
+ unsigned rx, int scale, int64_t disp,
unsigned sp, int modify)
{
TCGv_i64 tmp;
@@ -1838,7 +1730,7 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned rt,
/* Emit an unconditional branch to a direct target, which may or may not
have already had nullification handled. */
-static bool do_dbranch(DisasContext *ctx, target_ureg dest,
+static bool do_dbranch(DisasContext *ctx, uint64_t dest,
unsigned link, bool is_n)
{
if (ctx->null_cond.c == TCG_COND_NEVER && ctx->null_lab == NULL) {
@@ -1875,10 +1767,10 @@ static bool do_dbranch(DisasContext *ctx, target_ureg dest,
/* Emit a conditional branch to a direct target. If the branch itself
is nullified, we should have already used nullify_over. */
-static bool do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n,
+static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n,
DisasCond *cond)
{
- target_ureg dest = iaoq_dest(ctx, disp);
+ uint64_t dest = iaoq_dest(ctx, disp);
TCGLabel *taken = NULL;
TCGCond c = cond->c;
bool n;
@@ -2839,7 +2731,7 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i)
if (!is_i) {
tcg_gen_not_reg(tmp, tmp);
}
- tcg_gen_andi_reg(tmp, tmp, (target_ureg)0x1111111111111111ull);
+ tcg_gen_andi_reg(tmp, tmp, (uint64_t)0x1111111111111111ull);
tcg_gen_muli_reg(tmp, tmp, 6);
do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false,
is_i ? tcg_gen_add_reg : tcg_gen_sub_reg);
@@ -2961,22 +2853,20 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf_d *a)
static bool trans_ld(DisasContext *ctx, arg_ldst *a)
{
- if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) {
+ if (!ctx->is_pa20 && a->size > MO_32) {
return gen_illegal(ctx);
- } else {
- return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0,
- a->disp, a->sp, a->m, a->size | MO_TE);
}
+ return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0,
+ a->disp, a->sp, a->m, a->size | MO_TE);
}
static bool trans_st(DisasContext *ctx, arg_ldst *a)
{
assert(a->x == 0 && a->scale == 0);
- if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) {
+ if (!ctx->is_pa20 && a->size > MO_32) {
return gen_illegal(ctx);
- } else {
- return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE);
}
+ return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE);
}
static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
@@ -2985,7 +2875,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
TCGv_reg zero, dest, ofs;
TCGv_tl addr;
- if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) {
+ if (!ctx->is_pa20 && a->size > MO_32) {
return gen_illegal(ctx);
}
@@ -3394,7 +3284,7 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a)
t2 = load_gpr(ctx, a->r2);
if (a->r1 == 0) {
tcg_gen_extract_reg(dest, t2, sa, width - sa);
- } else if (width == TARGET_REGISTER_BITS) {
+ } else if (width == TARGET_LONG_BITS) {
tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa);
} else {
assert(!a->d);
@@ -3496,7 +3386,7 @@ static bool trans_extr_imm(DisasContext *ctx, arg_extr_imm *a)
static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a)
{
unsigned len, width;
- target_sreg mask0, mask1;
+ uint64_t mask0, mask1;
TCGv_reg dest;
if (!ctx->is_pa20 && a->d) {
@@ -3575,7 +3465,7 @@ static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c,
unsigned rs = nz ? rt : 0;
unsigned widthm1 = d ? 63 : 31;
TCGv_reg mask, tmp, shift, dest;
- target_ureg msb = 1ULL << (len - 1);
+ uint64_t msb = 1ULL << (len - 1);
dest = dest_gpr(ctx, rt);
shift = tcg_temp_new();
@@ -3691,7 +3581,7 @@ static bool trans_bl(DisasContext *ctx, arg_bl *a)
static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a)
{
- target_ureg dest = iaoq_dest(ctx, a->disp);
+ uint64_t dest = iaoq_dest(ctx, a->disp);
nullify_over(ctx);
@@ -3819,7 +3709,7 @@ static bool trans_fid_f(DisasContext *ctx, arg_fid_f *a)
{
uint64_t ret;
- if (TARGET_REGISTER_BITS == 64) {
+ if (ctx->is_pa20) {
ret = 0x13080000000000ULL; /* PA8700 (PCX-W2) */
} else {
ret = 0x0f080000000000ULL; /* PA7300LC (PCX-L2) */
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 47/61] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (45 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 46/61] target/hppa: Remove TARGET_REGISTER_BITS Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 48/61] target/hppa: Remove remaining " Richard Henderson
` (13 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Remove all but those intended to change type to or from i64.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 914 ++++++++++++++++++----------------------
1 file changed, 408 insertions(+), 506 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 46a9e83508..682cb518d6 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -36,110 +36,15 @@
/* Since we have a distinction between register size and address size,
we need to redefine all of these. */
-#undef TCGv
-#undef tcg_temp_new
-#undef tcg_global_mem_new
-
-#define TCGv_tl TCGv_i64
-#define tcg_temp_new_tl tcg_temp_new_i64
#define tcg_gen_extu_reg_tl tcg_gen_mov_i64
-
-#define TCGv_reg TCGv_i64
-
-#define tcg_temp_new tcg_temp_new_i64
-#define tcg_global_mem_new tcg_global_mem_new_i64
-
-#define tcg_gen_movi_reg tcg_gen_movi_i64
-#define tcg_gen_mov_reg tcg_gen_mov_i64
-#define tcg_gen_ld8u_reg tcg_gen_ld8u_i64
-#define tcg_gen_ld8s_reg tcg_gen_ld8s_i64
-#define tcg_gen_ld16u_reg tcg_gen_ld16u_i64
-#define tcg_gen_ld16s_reg tcg_gen_ld16s_i64
-#define tcg_gen_ld32u_reg tcg_gen_ld32u_i64
-#define tcg_gen_ld32s_reg tcg_gen_ld32s_i64
-#define tcg_gen_ld_reg tcg_gen_ld_i64
-#define tcg_gen_st8_reg tcg_gen_st8_i64
-#define tcg_gen_st16_reg tcg_gen_st16_i64
-#define tcg_gen_st32_reg tcg_gen_st32_i64
-#define tcg_gen_st_reg tcg_gen_st_i64
-#define tcg_gen_add_reg tcg_gen_add_i64
-#define tcg_gen_addi_reg tcg_gen_addi_i64
-#define tcg_gen_sub_reg tcg_gen_sub_i64
-#define tcg_gen_neg_reg tcg_gen_neg_i64
-#define tcg_gen_subfi_reg tcg_gen_subfi_i64
-#define tcg_gen_subi_reg tcg_gen_subi_i64
-#define tcg_gen_and_reg tcg_gen_and_i64
-#define tcg_gen_andi_reg tcg_gen_andi_i64
-#define tcg_gen_or_reg tcg_gen_or_i64
-#define tcg_gen_ori_reg tcg_gen_ori_i64
-#define tcg_gen_xor_reg tcg_gen_xor_i64
-#define tcg_gen_xori_reg tcg_gen_xori_i64
-#define tcg_gen_not_reg tcg_gen_not_i64
-#define tcg_gen_shl_reg tcg_gen_shl_i64
-#define tcg_gen_shli_reg tcg_gen_shli_i64
-#define tcg_gen_shr_reg tcg_gen_shr_i64
-#define tcg_gen_shri_reg tcg_gen_shri_i64
-#define tcg_gen_sar_reg tcg_gen_sar_i64
-#define tcg_gen_sari_reg tcg_gen_sari_i64
-#define tcg_gen_brcond_reg tcg_gen_brcond_i64
-#define tcg_gen_brcondi_reg tcg_gen_brcondi_i64
-#define tcg_gen_setcond_reg tcg_gen_setcond_i64
-#define tcg_gen_setcondi_reg tcg_gen_setcondi_i64
-#define tcg_gen_mul_reg tcg_gen_mul_i64
-#define tcg_gen_muli_reg tcg_gen_muli_i64
-#define tcg_gen_div_reg tcg_gen_div_i64
-#define tcg_gen_rem_reg tcg_gen_rem_i64
-#define tcg_gen_divu_reg tcg_gen_divu_i64
-#define tcg_gen_remu_reg tcg_gen_remu_i64
-#define tcg_gen_discard_reg tcg_gen_discard_i64
-#define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32
#define tcg_gen_trunc_i64_reg tcg_gen_mov_i64
-#define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64
-#define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64
#define tcg_gen_extu_reg_i64 tcg_gen_mov_i64
#define tcg_gen_ext_reg_i64 tcg_gen_mov_i64
-#define tcg_gen_ext8u_reg tcg_gen_ext8u_i64
-#define tcg_gen_ext8s_reg tcg_gen_ext8s_i64
-#define tcg_gen_ext16u_reg tcg_gen_ext16u_i64
-#define tcg_gen_ext16s_reg tcg_gen_ext16s_i64
-#define tcg_gen_ext32u_reg tcg_gen_ext32u_i64
-#define tcg_gen_ext32s_reg tcg_gen_ext32s_i64
-#define tcg_gen_bswap16_reg tcg_gen_bswap16_i64
-#define tcg_gen_bswap32_reg tcg_gen_bswap32_i64
-#define tcg_gen_bswap64_reg tcg_gen_bswap64_i64
-#define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64
-#define tcg_gen_andc_reg tcg_gen_andc_i64
-#define tcg_gen_eqv_reg tcg_gen_eqv_i64
-#define tcg_gen_nand_reg tcg_gen_nand_i64
-#define tcg_gen_nor_reg tcg_gen_nor_i64
-#define tcg_gen_orc_reg tcg_gen_orc_i64
-#define tcg_gen_clz_reg tcg_gen_clz_i64
-#define tcg_gen_ctz_reg tcg_gen_ctz_i64
-#define tcg_gen_clzi_reg tcg_gen_clzi_i64
-#define tcg_gen_ctzi_reg tcg_gen_ctzi_i64
-#define tcg_gen_clrsb_reg tcg_gen_clrsb_i64
-#define tcg_gen_ctpop_reg tcg_gen_ctpop_i64
-#define tcg_gen_rotl_reg tcg_gen_rotl_i64
-#define tcg_gen_rotli_reg tcg_gen_rotli_i64
-#define tcg_gen_rotr_reg tcg_gen_rotr_i64
-#define tcg_gen_rotri_reg tcg_gen_rotri_i64
-#define tcg_gen_deposit_reg tcg_gen_deposit_i64
-#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64
-#define tcg_gen_extract_reg tcg_gen_extract_i64
-#define tcg_gen_sextract_reg tcg_gen_sextract_i64
-#define tcg_gen_extract2_reg tcg_gen_extract2_i64
-#define tcg_constant_reg tcg_constant_i64
-#define tcg_gen_movcond_reg tcg_gen_movcond_i64
-#define tcg_gen_add2_reg tcg_gen_add2_i64
-#define tcg_gen_sub2_reg tcg_gen_sub2_i64
-#define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64
-#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64
-#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64
-#define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr
+
typedef struct DisasCond {
TCGCond c;
- TCGv_reg a0, a1;
+ TCGv_i64 a0, a1;
} DisasCond;
typedef struct DisasContext {
@@ -149,7 +54,7 @@ typedef struct DisasContext {
uint64_t iaoq_f;
uint64_t iaoq_b;
uint64_t iaoq_n;
- TCGv_reg iaoq_n_var;
+ TCGv_i64 iaoq_n_var;
DisasCond null_cond;
TCGLabel *null_lab;
@@ -261,24 +166,24 @@ static int cmpbid_c(DisasContext *ctx, int val)
#define DISAS_EXIT DISAS_TARGET_3
/* global register indexes */
-static TCGv_reg cpu_gr[32];
+static TCGv_i64 cpu_gr[32];
static TCGv_i64 cpu_sr[4];
static TCGv_i64 cpu_srH;
-static TCGv_reg cpu_iaoq_f;
-static TCGv_reg cpu_iaoq_b;
+static TCGv_i64 cpu_iaoq_f;
+static TCGv_i64 cpu_iaoq_b;
static TCGv_i64 cpu_iasq_f;
static TCGv_i64 cpu_iasq_b;
-static TCGv_reg cpu_sar;
-static TCGv_reg cpu_psw_n;
-static TCGv_reg cpu_psw_v;
-static TCGv_reg cpu_psw_cb;
-static TCGv_reg cpu_psw_cb_msb;
+static TCGv_i64 cpu_sar;
+static TCGv_i64 cpu_psw_n;
+static TCGv_i64 cpu_psw_v;
+static TCGv_i64 cpu_psw_cb;
+static TCGv_i64 cpu_psw_cb_msb;
void hppa_translate_init(void)
{
#define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) }
- typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar;
+ typedef struct { TCGv_i64 *var; const char *name; int ofs; } GlobalVar;
static const GlobalVar vars[] = {
{ &cpu_sar, "sar", offsetof(CPUHPPAState, cr[CR_SAR]) },
DEF_VAR(psw_n),
@@ -356,35 +261,35 @@ static DisasCond cond_make_n(void)
return (DisasCond){
.c = TCG_COND_NE,
.a0 = cpu_psw_n,
- .a1 = tcg_constant_reg(0)
+ .a1 = tcg_constant_i64(0)
};
}
-static DisasCond cond_make_tmp(TCGCond c, TCGv_reg a0, TCGv_reg a1)
+static DisasCond cond_make_tmp(TCGCond c, TCGv_i64 a0, TCGv_i64 a1)
{
assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS);
return (DisasCond){ .c = c, .a0 = a0, .a1 = a1 };
}
-static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0)
+static DisasCond cond_make_0_tmp(TCGCond c, TCGv_i64 a0)
{
- return cond_make_tmp(c, a0, tcg_constant_reg(0));
+ return cond_make_tmp(c, a0, tcg_constant_i64(0));
}
-static DisasCond cond_make_0(TCGCond c, TCGv_reg a0)
+static DisasCond cond_make_0(TCGCond c, TCGv_i64 a0)
{
- TCGv_reg tmp = tcg_temp_new();
- tcg_gen_mov_reg(tmp, a0);
+ TCGv_i64 tmp = tcg_temp_new();
+ tcg_gen_mov_i64(tmp, a0);
return cond_make_0_tmp(c, tmp);
}
-static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1)
+static DisasCond cond_make(TCGCond c, TCGv_i64 a0, TCGv_i64 a1)
{
- TCGv_reg t0 = tcg_temp_new();
- TCGv_reg t1 = tcg_temp_new();
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
- tcg_gen_mov_reg(t0, a0);
- tcg_gen_mov_reg(t1, a1);
+ tcg_gen_mov_i64(t0, a0);
+ tcg_gen_mov_i64(t1, a1);
return cond_make_tmp(c, t0, t1);
}
@@ -403,18 +308,18 @@ static void cond_free(DisasCond *cond)
}
}
-static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg)
+static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg)
{
if (reg == 0) {
- TCGv_reg t = tcg_temp_new();
- tcg_gen_movi_reg(t, 0);
+ TCGv_i64 t = tcg_temp_new();
+ tcg_gen_movi_i64(t, 0);
return t;
} else {
return cpu_gr[reg];
}
}
-static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg)
+static TCGv_i64 dest_gpr(DisasContext *ctx, unsigned reg)
{
if (reg == 0 || ctx->null_cond.c != TCG_COND_NEVER) {
return tcg_temp_new();
@@ -423,17 +328,17 @@ static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg)
}
}
-static void save_or_nullify(DisasContext *ctx, TCGv_reg dest, TCGv_reg t)
+static void save_or_nullify(DisasContext *ctx, TCGv_i64 dest, TCGv_i64 t)
{
if (ctx->null_cond.c != TCG_COND_NEVER) {
- tcg_gen_movcond_reg(ctx->null_cond.c, dest, ctx->null_cond.a0,
+ tcg_gen_movcond_i64(ctx->null_cond.c, dest, ctx->null_cond.a0,
ctx->null_cond.a1, dest, t);
} else {
- tcg_gen_mov_reg(dest, t);
+ tcg_gen_mov_i64(dest, t);
}
}
-static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_reg t)
+static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_i64 t)
{
if (reg != 0) {
save_or_nullify(ctx, cpu_gr[reg], t);
@@ -542,17 +447,17 @@ static void nullify_over(DisasContext *ctx)
/* If we're using PSW[N], copy it to a temp because... */
if (ctx->null_cond.a0 == cpu_psw_n) {
ctx->null_cond.a0 = tcg_temp_new();
- tcg_gen_mov_reg(ctx->null_cond.a0, cpu_psw_n);
+ tcg_gen_mov_i64(ctx->null_cond.a0, cpu_psw_n);
}
/* ... we clear it before branching over the implementation,
so that (1) it's clear after nullifying this insn and
(2) if this insn nullifies the next, PSW[N] is valid. */
if (ctx->psw_n_nonzero) {
ctx->psw_n_nonzero = false;
- tcg_gen_movi_reg(cpu_psw_n, 0);
+ tcg_gen_movi_i64(cpu_psw_n, 0);
}
- tcg_gen_brcond_reg(ctx->null_cond.c, ctx->null_cond.a0,
+ tcg_gen_brcond_i64(ctx->null_cond.c, ctx->null_cond.a0,
ctx->null_cond.a1, ctx->null_lab);
cond_free(&ctx->null_cond);
}
@@ -563,12 +468,12 @@ static void nullify_save(DisasContext *ctx)
{
if (ctx->null_cond.c == TCG_COND_NEVER) {
if (ctx->psw_n_nonzero) {
- tcg_gen_movi_reg(cpu_psw_n, 0);
+ tcg_gen_movi_i64(cpu_psw_n, 0);
}
return;
}
if (ctx->null_cond.a0 != cpu_psw_n) {
- tcg_gen_setcond_reg(ctx->null_cond.c, cpu_psw_n,
+ tcg_gen_setcond_i64(ctx->null_cond.c, cpu_psw_n,
ctx->null_cond.a0, ctx->null_cond.a1);
ctx->psw_n_nonzero = true;
}
@@ -581,7 +486,7 @@ static void nullify_save(DisasContext *ctx)
static void nullify_set(DisasContext *ctx, bool x)
{
if (ctx->psw_n_nonzero || x) {
- tcg_gen_movi_reg(cpu_psw_n, x);
+ tcg_gen_movi_i64(cpu_psw_n, x);
}
}
@@ -624,12 +529,12 @@ static bool nullify_end(DisasContext *ctx)
return true;
}
-static void copy_iaoq_entry(TCGv_reg dest, uint64_t ival, TCGv_reg vval)
+static void copy_iaoq_entry(TCGv_i64 dest, uint64_t ival, TCGv_i64 vval)
{
if (unlikely(ival == -1)) {
- tcg_gen_mov_reg(dest, vval);
+ tcg_gen_mov_i64(dest, vval);
} else {
- tcg_gen_movi_reg(dest, ival);
+ tcg_gen_movi_i64(dest, ival);
}
}
@@ -655,7 +560,7 @@ static void gen_excp(DisasContext *ctx, int exception)
static bool gen_excp_iir(DisasContext *ctx, int exc)
{
nullify_over(ctx);
- tcg_gen_st_reg(tcg_constant_reg(ctx->insn),
+ tcg_gen_st_i64(tcg_constant_i64(ctx->insn),
tcg_env, offsetof(CPUHPPAState, cr[CR_IIR]));
gen_excp(ctx, exc);
return nullify_end(ctx);
@@ -705,8 +610,8 @@ static void gen_goto_tb(DisasContext *ctx, int which,
{
if (f != -1 && b != -1 && use_goto_tb(ctx, f)) {
tcg_gen_goto_tb(which);
- tcg_gen_movi_reg(cpu_iaoq_f, f);
- tcg_gen_movi_reg(cpu_iaoq_b, b);
+ tcg_gen_movi_i64(cpu_iaoq_f, f);
+ tcg_gen_movi_i64(cpu_iaoq_b, b);
tcg_gen_exit_tb(ctx->base.tb, which);
} else {
copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b);
@@ -725,7 +630,7 @@ static bool cond_need_cb(int c)
return c == 4 || c == 5;
}
-/* Need extensions from TCGv_i32 to TCGv_reg. */
+/* Need extensions from TCGv_i32 to TCGv_i64. */
static bool cond_need_ext(DisasContext *ctx, bool d)
{
return !(ctx->is_pa20 && d);
@@ -737,10 +642,10 @@ static bool cond_need_ext(DisasContext *ctx, bool d)
*/
static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
- TCGv_reg res, TCGv_reg cb_msb, TCGv_reg sv)
+ TCGv_i64 res, TCGv_i64 cb_msb, TCGv_i64 sv)
{
DisasCond cond;
- TCGv_reg tmp;
+ TCGv_i64 tmp;
switch (cf >> 1) {
case 0: /* Never / TR (0 / 1) */
@@ -749,16 +654,16 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
case 1: /* = / <> (Z / !Z) */
if (cond_need_ext(ctx, d)) {
tmp = tcg_temp_new();
- tcg_gen_ext32u_reg(tmp, res);
+ tcg_gen_ext32u_i64(tmp, res);
res = tmp;
}
cond = cond_make_0(TCG_COND_EQ, res);
break;
case 2: /* < / >= (N ^ V / !(N ^ V) */
tmp = tcg_temp_new();
- tcg_gen_xor_reg(tmp, res, sv);
+ tcg_gen_xor_i64(tmp, res, sv);
if (cond_need_ext(ctx, d)) {
- tcg_gen_ext32s_reg(tmp, tmp);
+ tcg_gen_ext32s_i64(tmp, tmp);
}
cond = cond_make_0_tmp(TCG_COND_LT, tmp);
break;
@@ -773,14 +678,14 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
* !(~(res ^ sv) >> 31 & res)
*/
tmp = tcg_temp_new();
- tcg_gen_eqv_reg(tmp, res, sv);
+ tcg_gen_eqv_i64(tmp, res, sv);
if (cond_need_ext(ctx, d)) {
- tcg_gen_sextract_reg(tmp, tmp, 31, 1);
- tcg_gen_and_reg(tmp, tmp, res);
- tcg_gen_ext32u_reg(tmp, tmp);
+ tcg_gen_sextract_i64(tmp, tmp, 31, 1);
+ tcg_gen_and_i64(tmp, tmp, res);
+ tcg_gen_ext32u_i64(tmp, tmp);
} else {
- tcg_gen_sari_reg(tmp, tmp, 63);
- tcg_gen_and_reg(tmp, tmp, res);
+ tcg_gen_sari_i64(tmp, tmp, 63);
+ tcg_gen_and_i64(tmp, tmp, res);
}
cond = cond_make_0_tmp(TCG_COND_EQ, tmp);
break;
@@ -790,24 +695,24 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
break;
case 5: /* ZNV / VNZ (!C | Z / C & !Z) */
tmp = tcg_temp_new();
- tcg_gen_neg_reg(tmp, cb_msb);
- tcg_gen_and_reg(tmp, tmp, res);
+ tcg_gen_neg_i64(tmp, cb_msb);
+ tcg_gen_and_i64(tmp, tmp, res);
if (cond_need_ext(ctx, d)) {
- tcg_gen_ext32u_reg(tmp, tmp);
+ tcg_gen_ext32u_i64(tmp, tmp);
}
cond = cond_make_0_tmp(TCG_COND_EQ, tmp);
break;
case 6: /* SV / NSV (V / !V) */
if (cond_need_ext(ctx, d)) {
tmp = tcg_temp_new();
- tcg_gen_ext32s_reg(tmp, sv);
+ tcg_gen_ext32s_i64(tmp, sv);
sv = tmp;
}
cond = cond_make_0(TCG_COND_LT, sv);
break;
case 7: /* OD / EV */
tmp = tcg_temp_new();
- tcg_gen_andi_reg(tmp, res, 1);
+ tcg_gen_andi_i64(tmp, res, 1);
cond = cond_make_0_tmp(TCG_COND_NE, tmp);
break;
default:
@@ -825,8 +730,8 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
deleted as unused. */
static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d,
- TCGv_reg res, TCGv_reg in1,
- TCGv_reg in2, TCGv_reg sv)
+ TCGv_i64 res, TCGv_i64 in1,
+ TCGv_i64 in2, TCGv_i64 sv)
{
TCGCond tc;
bool ext_uns;
@@ -860,15 +765,15 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d,
tc = tcg_invert_cond(tc);
}
if (cond_need_ext(ctx, d)) {
- TCGv_reg t1 = tcg_temp_new();
- TCGv_reg t2 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ TCGv_i64 t2 = tcg_temp_new();
if (ext_uns) {
- tcg_gen_ext32u_reg(t1, in1);
- tcg_gen_ext32u_reg(t2, in2);
+ tcg_gen_ext32u_i64(t1, in1);
+ tcg_gen_ext32u_i64(t2, in2);
} else {
- tcg_gen_ext32s_reg(t1, in1);
- tcg_gen_ext32s_reg(t2, in2);
+ tcg_gen_ext32s_i64(t1, in1);
+ tcg_gen_ext32s_i64(t2, in2);
}
return cond_make_tmp(tc, t1, t2);
}
@@ -885,7 +790,7 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d,
*/
static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d,
- TCGv_reg res)
+ TCGv_i64 res)
{
TCGCond tc;
bool ext_uns;
@@ -937,12 +842,12 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d,
}
if (cond_need_ext(ctx, d)) {
- TCGv_reg tmp = tcg_temp_new();
+ TCGv_i64 tmp = tcg_temp_new();
if (ext_uns) {
- tcg_gen_ext32u_reg(tmp, res);
+ tcg_gen_ext32u_i64(tmp, res);
} else {
- tcg_gen_ext32s_reg(tmp, res);
+ tcg_gen_ext32s_i64(tmp, res);
}
return cond_make_0_tmp(tc, tmp);
}
@@ -952,7 +857,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d,
/* Similar, but for shift/extract/deposit conditions. */
static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d,
- TCGv_reg res)
+ TCGv_i64 res)
{
unsigned c, f;
@@ -970,11 +875,11 @@ static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d,
/* Similar, but for unit conditions. */
-static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_reg res,
- TCGv_reg in1, TCGv_reg in2)
+static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res,
+ TCGv_i64 in1, TCGv_i64 in2)
{
DisasCond cond;
- TCGv_reg tmp, cb = NULL;
+ TCGv_i64 tmp, cb = NULL;
uint64_t d_repl = d ? 0x0000000100000001ull : 1;
if (cf & 8) {
@@ -984,10 +889,10 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_reg res,
*/
cb = tcg_temp_new();
tmp = tcg_temp_new();
- tcg_gen_or_reg(cb, in1, in2);
- tcg_gen_and_reg(tmp, in1, in2);
- tcg_gen_andc_reg(cb, cb, res);
- tcg_gen_or_reg(cb, cb, tmp);
+ tcg_gen_or_i64(cb, in1, in2);
+ tcg_gen_and_i64(tmp, in1, in2);
+ tcg_gen_andc_i64(cb, cb, res);
+ tcg_gen_or_i64(cb, cb, tmp);
}
switch (cf >> 1) {
@@ -1002,32 +907,32 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_reg res,
* https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
*/
tmp = tcg_temp_new();
- tcg_gen_subi_reg(tmp, res, d_repl * 0x01010101u);
- tcg_gen_andc_reg(tmp, tmp, res);
- tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80808080u);
+ tcg_gen_subi_i64(tmp, res, d_repl * 0x01010101u);
+ tcg_gen_andc_i64(tmp, tmp, res);
+ tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80808080u);
cond = cond_make_0(TCG_COND_NE, tmp);
break;
case 3: /* SHZ / NHZ */
tmp = tcg_temp_new();
- tcg_gen_subi_reg(tmp, res, d_repl * 0x00010001u);
- tcg_gen_andc_reg(tmp, tmp, res);
- tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80008000u);
+ tcg_gen_subi_i64(tmp, res, d_repl * 0x00010001u);
+ tcg_gen_andc_i64(tmp, tmp, res);
+ tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80008000u);
cond = cond_make_0(TCG_COND_NE, tmp);
break;
case 4: /* SDC / NDC */
- tcg_gen_andi_reg(cb, cb, d_repl * 0x88888888u);
+ tcg_gen_andi_i64(cb, cb, d_repl * 0x88888888u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
case 6: /* SBC / NBC */
- tcg_gen_andi_reg(cb, cb, d_repl * 0x80808080u);
+ tcg_gen_andi_i64(cb, cb, d_repl * 0x80808080u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
case 7: /* SHC / NHC */
- tcg_gen_andi_reg(cb, cb, d_repl * 0x80008000u);
+ tcg_gen_andi_i64(cb, cb, d_repl * 0x80008000u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
@@ -1041,55 +946,55 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_reg res,
return cond;
}
-static TCGv_reg get_carry(DisasContext *ctx, bool d,
- TCGv_reg cb, TCGv_reg cb_msb)
+static TCGv_i64 get_carry(DisasContext *ctx, bool d,
+ TCGv_i64 cb, TCGv_i64 cb_msb)
{
if (cond_need_ext(ctx, d)) {
- TCGv_reg t = tcg_temp_new();
- tcg_gen_extract_reg(t, cb, 32, 1);
+ TCGv_i64 t = tcg_temp_new();
+ tcg_gen_extract_i64(t, cb, 32, 1);
return t;
}
return cb_msb;
}
-static TCGv_reg get_psw_carry(DisasContext *ctx, bool d)
+static TCGv_i64 get_psw_carry(DisasContext *ctx, bool d)
{
return get_carry(ctx, d, cpu_psw_cb, cpu_psw_cb_msb);
}
/* Compute signed overflow for addition. */
-static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res,
- TCGv_reg in1, TCGv_reg in2)
+static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 res,
+ TCGv_i64 in1, TCGv_i64 in2)
{
- TCGv_reg sv = tcg_temp_new();
- TCGv_reg tmp = tcg_temp_new();
+ TCGv_i64 sv = tcg_temp_new();
+ TCGv_i64 tmp = tcg_temp_new();
- tcg_gen_xor_reg(sv, res, in1);
- tcg_gen_xor_reg(tmp, in1, in2);
- tcg_gen_andc_reg(sv, sv, tmp);
+ tcg_gen_xor_i64(sv, res, in1);
+ tcg_gen_xor_i64(tmp, in1, in2);
+ tcg_gen_andc_i64(sv, sv, tmp);
return sv;
}
/* Compute signed overflow for subtraction. */
-static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res,
- TCGv_reg in1, TCGv_reg in2)
+static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res,
+ TCGv_i64 in1, TCGv_i64 in2)
{
- TCGv_reg sv = tcg_temp_new();
- TCGv_reg tmp = tcg_temp_new();
+ TCGv_i64 sv = tcg_temp_new();
+ TCGv_i64 tmp = tcg_temp_new();
- tcg_gen_xor_reg(sv, res, in1);
- tcg_gen_xor_reg(tmp, in1, in2);
- tcg_gen_and_reg(sv, sv, tmp);
+ tcg_gen_xor_i64(sv, res, in1);
+ tcg_gen_xor_i64(tmp, in1, in2);
+ tcg_gen_and_i64(sv, sv, tmp);
return sv;
}
-static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
- TCGv_reg in2, unsigned shift, bool is_l,
+static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
+ TCGv_i64 in2, unsigned shift, bool is_l,
bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d)
{
- TCGv_reg dest, cb, cb_msb, cb_cond, sv, tmp;
+ TCGv_i64 dest, cb, cb_msb, cb_cond, sv, tmp;
unsigned c = cf >> 1;
DisasCond cond;
@@ -1100,29 +1005,29 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
if (shift) {
tmp = tcg_temp_new();
- tcg_gen_shli_reg(tmp, in1, shift);
+ tcg_gen_shli_i64(tmp, in1, shift);
in1 = tmp;
}
if (!is_l || cond_need_cb(c)) {
- TCGv_reg zero = tcg_constant_reg(0);
+ TCGv_i64 zero = tcg_constant_i64(0);
cb_msb = tcg_temp_new();
cb = tcg_temp_new();
- tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero);
+ tcg_gen_add2_i64(dest, cb_msb, in1, zero, in2, zero);
if (is_c) {
- tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb,
+ tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb,
get_psw_carry(ctx, d), zero);
}
- tcg_gen_xor_reg(cb, in1, in2);
- tcg_gen_xor_reg(cb, cb, dest);
+ tcg_gen_xor_i64(cb, in1, in2);
+ tcg_gen_xor_i64(cb, cb, dest);
if (cond_need_cb(c)) {
cb_cond = get_carry(ctx, d, cb, cb_msb);
}
} else {
- tcg_gen_add_reg(dest, in1, in2);
+ tcg_gen_add_i64(dest, in1, in2);
if (is_c) {
- tcg_gen_add_reg(dest, dest, get_psw_carry(ctx, d));
+ tcg_gen_add_i64(dest, dest, get_psw_carry(ctx, d));
}
}
@@ -1140,7 +1045,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
cond = do_cond(ctx, cf, d, dest, cb_cond, sv);
if (is_tc) {
tmp = tcg_temp_new();
- tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
+ tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1);
gen_helper_tcond(tcg_env, tmp);
}
@@ -1159,7 +1064,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a,
bool is_l, bool is_tsv, bool is_tc, bool is_c)
{
- TCGv_reg tcg_r1, tcg_r2;
+ TCGv_i64 tcg_r1, tcg_r2;
if (a->cf) {
nullify_over(ctx);
@@ -1174,23 +1079,23 @@ static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a,
static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a,
bool is_tsv, bool is_tc)
{
- TCGv_reg tcg_im, tcg_r2;
+ TCGv_i64 tcg_im, tcg_r2;
if (a->cf) {
nullify_over(ctx);
}
- tcg_im = tcg_constant_reg(a->i);
+ tcg_im = tcg_constant_i64(a->i);
tcg_r2 = load_gpr(ctx, a->r);
/* All ADDI conditions are 32-bit. */
do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf, false);
return nullify_end(ctx);
}
-static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
- TCGv_reg in2, bool is_tsv, bool is_b,
+static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
+ TCGv_i64 in2, bool is_tsv, bool is_b,
bool is_tc, unsigned cf, bool d)
{
- TCGv_reg dest, sv, cb, cb_msb, zero, tmp;
+ TCGv_i64 dest, sv, cb, cb_msb, zero, tmp;
unsigned c = cf >> 1;
DisasCond cond;
@@ -1198,23 +1103,23 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
cb = tcg_temp_new();
cb_msb = tcg_temp_new();
- zero = tcg_constant_reg(0);
+ zero = tcg_constant_i64(0);
if (is_b) {
/* DEST,C = IN1 + ~IN2 + C. */
- tcg_gen_not_reg(cb, in2);
- tcg_gen_add2_reg(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), zero);
- tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero);
- tcg_gen_xor_reg(cb, cb, in1);
- tcg_gen_xor_reg(cb, cb, dest);
+ tcg_gen_not_i64(cb, in2);
+ tcg_gen_add2_i64(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), zero);
+ tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, cb, zero);
+ tcg_gen_xor_i64(cb, cb, in1);
+ tcg_gen_xor_i64(cb, cb, dest);
} else {
/*
* DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer
* operations by seeding the high word with 1 and subtracting.
*/
- TCGv_reg one = tcg_constant_reg(1);
- tcg_gen_sub2_reg(dest, cb_msb, in1, one, in2, zero);
- tcg_gen_eqv_reg(cb, in1, in2);
- tcg_gen_xor_reg(cb, cb, dest);
+ TCGv_i64 one = tcg_constant_i64(1);
+ tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, zero);
+ tcg_gen_eqv_i64(cb, in1, in2);
+ tcg_gen_xor_i64(cb, cb, dest);
}
/* Compute signed overflow if required. */
@@ -1236,7 +1141,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
/* Emit any conditional trap before any writeback. */
if (is_tc) {
tmp = tcg_temp_new();
- tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
+ tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1);
gen_helper_tcond(tcg_env, tmp);
}
@@ -1253,7 +1158,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf_d *a,
bool is_tsv, bool is_b, bool is_tc)
{
- TCGv_reg tcg_r1, tcg_r2;
+ TCGv_i64 tcg_r1, tcg_r2;
if (a->cf) {
nullify_over(ctx);
@@ -1266,26 +1171,26 @@ static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf_d *a,
static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv)
{
- TCGv_reg tcg_im, tcg_r2;
+ TCGv_i64 tcg_im, tcg_r2;
if (a->cf) {
nullify_over(ctx);
}
- tcg_im = tcg_constant_reg(a->i);
+ tcg_im = tcg_constant_i64(a->i);
tcg_r2 = load_gpr(ctx, a->r);
/* All SUBI conditions are 32-bit. */
do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf, false);
return nullify_end(ctx);
}
-static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1,
- TCGv_reg in2, unsigned cf, bool d)
+static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
+ TCGv_i64 in2, unsigned cf, bool d)
{
- TCGv_reg dest, sv;
+ TCGv_i64 dest, sv;
DisasCond cond;
dest = tcg_temp_new();
- tcg_gen_sub_reg(dest, in1, in2);
+ tcg_gen_sub_i64(dest, in1, in2);
/* Compute signed overflow if required. */
sv = NULL;
@@ -1297,7 +1202,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1,
cond = do_sub_cond(ctx, cf, d, dest, in1, in2, sv);
/* Clear. */
- tcg_gen_movi_reg(dest, 0);
+ tcg_gen_movi_i64(dest, 0);
save_gpr(ctx, rt, dest);
/* Install the new nullification. */
@@ -1305,11 +1210,11 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1,
ctx->null_cond = cond;
}
-static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1,
- TCGv_reg in2, unsigned cf, bool d,
- void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
+static void do_log(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
+ TCGv_i64 in2, unsigned cf, bool d,
+ void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64))
{
- TCGv_reg dest = dest_gpr(ctx, rt);
+ TCGv_i64 dest = dest_gpr(ctx, rt);
/* Perform the operation, and writeback. */
fn(dest, in1, in2);
@@ -1323,9 +1228,9 @@ static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1,
}
static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a,
- void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
+ void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64))
{
- TCGv_reg tcg_r1, tcg_r2;
+ TCGv_i64 tcg_r1, tcg_r2;
if (a->cf) {
nullify_over(ctx);
@@ -1336,11 +1241,11 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a,
return nullify_end(ctx);
}
-static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1,
- TCGv_reg in2, unsigned cf, bool d, bool is_tc,
- void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
+static void do_unit(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
+ TCGv_i64 in2, unsigned cf, bool d, bool is_tc,
+ void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64))
{
- TCGv_reg dest;
+ TCGv_i64 dest;
DisasCond cond;
if (cf == 0) {
@@ -1355,8 +1260,8 @@ static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1,
cond = do_unit_cond(cf, d, dest, in1, in2);
if (is_tc) {
- TCGv_reg tmp = tcg_temp_new();
- tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1);
+ TCGv_i64 tmp = tcg_temp_new();
+ tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1);
gen_helper_tcond(tcg_env, tmp);
}
save_gpr(ctx, rt, dest);
@@ -1371,17 +1276,17 @@ static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1,
from the top 2 bits of the base register. There are a few system
instructions that have a 3-bit space specifier, for which SR0 is
not special. To handle this, pass ~SP. */
-static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base)
+static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_i64 base)
{
TCGv_ptr ptr;
- TCGv_reg tmp;
+ TCGv_i64 tmp;
TCGv_i64 spc;
if (sp != 0) {
if (sp < 0) {
sp = ~sp;
}
- spc = tcg_temp_new_tl();
+ spc = tcg_temp_new_i64();
load_spr(ctx, spc, sp);
return spc;
}
@@ -1391,12 +1296,12 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base)
ptr = tcg_temp_new_ptr();
tmp = tcg_temp_new();
- spc = tcg_temp_new_tl();
+ spc = tcg_temp_new_i64();
/* Extract top 2 bits of the address, shift left 3 for uint64_t index. */
- tcg_gen_shri_reg(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5);
- tcg_gen_andi_reg(tmp, tmp, 030);
- tcg_gen_trunc_reg_ptr(ptr, tmp);
+ tcg_gen_shri_i64(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5);
+ tcg_gen_andi_i64(tmp, tmp, 030);
+ tcg_gen_trunc_i64_ptr(ptr, tmp);
tcg_gen_add_ptr(ptr, ptr, tcg_env);
tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4]));
@@ -1405,28 +1310,28 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base)
}
#endif
-static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs,
+static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs,
unsigned rb, unsigned rx, int scale, int64_t disp,
unsigned sp, int modify, bool is_phys)
{
- TCGv_reg base = load_gpr(ctx, rb);
- TCGv_reg ofs;
- TCGv_tl addr;
+ TCGv_i64 base = load_gpr(ctx, rb);
+ TCGv_i64 ofs;
+ TCGv_i64 addr;
/* Note that RX is mutually exclusive with DISP. */
if (rx) {
ofs = tcg_temp_new();
- tcg_gen_shli_reg(ofs, cpu_gr[rx], scale);
- tcg_gen_add_reg(ofs, ofs, base);
+ tcg_gen_shli_i64(ofs, cpu_gr[rx], scale);
+ tcg_gen_add_i64(ofs, ofs, base);
} else if (disp || modify) {
ofs = tcg_temp_new();
- tcg_gen_addi_reg(ofs, base, disp);
+ tcg_gen_addi_i64(ofs, base, disp);
} else {
ofs = base;
}
*pofs = ofs;
- *pgva = addr = tcg_temp_new_tl();
+ *pgva = addr = tcg_temp_new_i64();
tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base);
tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx));
#ifndef CONFIG_USER_ONLY
@@ -1445,8 +1350,8 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
unsigned rx, int scale, int64_t disp,
unsigned sp, int modify, MemOp mop)
{
- TCGv_reg ofs;
- TCGv_tl addr;
+ TCGv_i64 ofs;
+ TCGv_i64 addr;
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
@@ -1463,8 +1368,8 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,
unsigned rx, int scale, int64_t disp,
unsigned sp, int modify, MemOp mop)
{
- TCGv_reg ofs;
- TCGv_tl addr;
+ TCGv_i64 ofs;
+ TCGv_i64 addr;
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
@@ -1481,8 +1386,8 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,
unsigned rx, int scale, int64_t disp,
unsigned sp, int modify, MemOp mop)
{
- TCGv_reg ofs;
- TCGv_tl addr;
+ TCGv_i64 ofs;
+ TCGv_i64 addr;
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
@@ -1499,8 +1404,8 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
unsigned rx, int scale, int64_t disp,
unsigned sp, int modify, MemOp mop)
{
- TCGv_reg ofs;
- TCGv_tl addr;
+ TCGv_i64 ofs;
+ TCGv_i64 addr;
/* Caller uses nullify_over/nullify_end. */
assert(ctx->null_cond.c == TCG_COND_NEVER);
@@ -1513,14 +1418,11 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
}
}
-#define do_load_reg do_load_64
-#define do_store_reg do_store_64
-
static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,
unsigned rx, int scale, int64_t disp,
unsigned sp, int modify, MemOp mop)
{
- TCGv_reg dest;
+ TCGv_i64 dest;
nullify_over(ctx);
@@ -1531,7 +1433,7 @@ static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,
/* Make sure if RT == RB, we see the result of the load. */
dest = tcg_temp_new();
}
- do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop);
+ do_load_64(ctx, dest, rb, rx, scale, disp, sp, modify, mop);
save_gpr(ctx, rt, dest);
return nullify_end(ctx);
@@ -1592,7 +1494,7 @@ static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb,
int modify, MemOp mop)
{
nullify_over(ctx);
- do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop);
+ do_store_64(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop);
return nullify_end(ctx);
}
@@ -1786,7 +1688,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n,
}
taken = gen_new_label();
- tcg_gen_brcond_reg(c, cond->a0, cond->a1, taken);
+ tcg_gen_brcond_i64(c, cond->a0, cond->a1, taken);
cond_free(cond);
/* Not taken: Condition not satisfied; nullify on backward branches. */
@@ -1803,7 +1705,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n,
if (ctx->iaoq_n == -1) {
/* The temporary iaoq_n_var died at the branch above.
Regenerate it here instead of saving it. */
- tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4);
+ tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4);
}
gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n);
}
@@ -1833,10 +1735,10 @@ static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n,
/* Emit an unconditional branch to an indirect target. This handles
nullification of the branch itself. */
-static bool do_ibranch(DisasContext *ctx, TCGv_reg dest,
+static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest,
unsigned link, bool is_n)
{
- TCGv_reg a0, a1, next, tmp;
+ TCGv_i64 a0, a1, next, tmp;
TCGCond c;
assert(ctx->null_lab == NULL);
@@ -1846,11 +1748,11 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg dest,
copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
}
next = tcg_temp_new();
- tcg_gen_mov_reg(next, dest);
+ tcg_gen_mov_i64(next, dest);
if (is_n) {
if (use_nullify_skip(ctx)) {
- tcg_gen_mov_reg(cpu_iaoq_f, next);
- tcg_gen_addi_reg(cpu_iaoq_b, next, 4);
+ tcg_gen_mov_i64(cpu_iaoq_f, next);
+ tcg_gen_addi_i64(cpu_iaoq_b, next, 4);
nullify_set(ctx, 0);
ctx->base.is_jmp = DISAS_IAQ_N_UPDATED;
return true;
@@ -1872,12 +1774,12 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg dest,
/* We do have to handle the non-local temporary, DEST, before
branching. Since IOAQ_F is not really live at this point, we
can simply store DEST optimistically. Similarly with IAOQ_B. */
- tcg_gen_mov_reg(cpu_iaoq_f, dest);
- tcg_gen_addi_reg(cpu_iaoq_b, dest, 4);
+ tcg_gen_mov_i64(cpu_iaoq_f, dest);
+ tcg_gen_addi_i64(cpu_iaoq_b, dest, 4);
nullify_over(ctx);
if (link != 0) {
- tcg_gen_movi_reg(cpu_gr[link], ctx->iaoq_n);
+ tcg_gen_movi_i64(cpu_gr[link], ctx->iaoq_n);
}
tcg_gen_lookup_and_goto_ptr();
return nullify_end(ctx);
@@ -1890,19 +1792,19 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg dest,
next = tcg_temp_new();
copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var);
- tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest);
+ tcg_gen_movcond_i64(c, next, a0, a1, tmp, dest);
ctx->iaoq_n = -1;
ctx->iaoq_n_var = next;
if (link != 0) {
- tcg_gen_movcond_reg(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp);
+ tcg_gen_movcond_i64(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp);
}
if (is_n) {
/* The branch nullifies the next insn, which means the state of N
after the branch is the inverse of the state of N that applied
to the branch. */
- tcg_gen_setcond_reg(tcg_invert_cond(c), cpu_psw_n, a0, a1);
+ tcg_gen_setcond_i64(tcg_invert_cond(c), cpu_psw_n, a0, a1);
cond_free(&ctx->null_cond);
ctx->null_cond = cond_make_n();
ctx->psw_n_nonzero = true;
@@ -1920,9 +1822,9 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg dest,
* IAOQ_Next{30..31} ← IAOQ_Front{30..31};
* which keeps the privilege level from being increased.
*/
-static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset)
+static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset)
{
- TCGv_reg dest;
+ TCGv_i64 dest;
switch (ctx->privilege) {
case 0:
/* Privilege 0 is maximum and is allowed to decrease. */
@@ -1930,13 +1832,13 @@ static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset)
case 3:
/* Privilege 3 is minimum and is never allowed to increase. */
dest = tcg_temp_new();
- tcg_gen_ori_reg(dest, offset, 3);
+ tcg_gen_ori_i64(dest, offset, 3);
break;
default:
dest = tcg_temp_new();
- tcg_gen_andi_reg(dest, offset, -4);
- tcg_gen_ori_reg(dest, dest, ctx->privilege);
- tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset);
+ tcg_gen_andi_i64(dest, offset, -4);
+ tcg_gen_ori_i64(dest, dest, ctx->privilege);
+ tcg_gen_movcond_i64(TCG_COND_GTU, dest, dest, offset, dest, offset);
break;
}
return dest;
@@ -1959,7 +1861,7 @@ static void do_page_zero(DisasContext *ctx)
case TCG_COND_NEVER:
break;
case TCG_COND_ALWAYS:
- tcg_gen_movi_reg(cpu_psw_n, 0);
+ tcg_gen_movi_i64(cpu_psw_n, 0);
goto do_sigill;
default:
/* Since this is always the first (and only) insn within the
@@ -1987,9 +1889,9 @@ static void do_page_zero(DisasContext *ctx)
break;
case 0xe0: /* SET_THREAD_POINTER */
- tcg_gen_st_reg(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27]));
- tcg_gen_ori_reg(cpu_iaoq_f, cpu_gr[31], 3);
- tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4);
+ tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27]));
+ tcg_gen_ori_i64(cpu_iaoq_f, cpu_gr[31], 3);
+ tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, 4);
ctx->base.is_jmp = DISAS_IAQ_N_UPDATED;
break;
@@ -2030,8 +1932,8 @@ static bool trans_sync(DisasContext *ctx, arg_sync *a)
static bool trans_mfia(DisasContext *ctx, arg_mfia *a)
{
unsigned rt = a->t;
- TCGv_reg tmp = dest_gpr(ctx, rt);
- tcg_gen_movi_reg(tmp, ctx->iaoq_f);
+ TCGv_i64 tmp = dest_gpr(ctx, rt);
+ tcg_gen_movi_i64(tmp, ctx->iaoq_f);
save_gpr(ctx, rt, tmp);
cond_free(&ctx->null_cond);
@@ -2043,7 +1945,7 @@ static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a)
unsigned rt = a->t;
unsigned rs = a->sp;
TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_reg t1 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
load_spr(ctx, t0, rs);
tcg_gen_shri_i64(t0, t0, 32);
@@ -2059,14 +1961,14 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a)
{
unsigned rt = a->t;
unsigned ctl = a->r;
- TCGv_reg tmp;
+ TCGv_i64 tmp;
switch (ctl) {
case CR_SAR:
if (a->e == 0) {
/* MFSAR without ,W masks low 5 bits. */
tmp = dest_gpr(ctx, rt);
- tcg_gen_andi_reg(tmp, cpu_sar, 31);
+ tcg_gen_andi_i64(tmp, cpu_sar, 31);
save_gpr(ctx, rt, tmp);
goto done;
}
@@ -2094,7 +1996,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a)
}
tmp = tcg_temp_new();
- tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
+ tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
save_gpr(ctx, rt, tmp);
done:
@@ -2130,13 +2032,13 @@ static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a)
static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
{
unsigned ctl = a->t;
- TCGv_reg reg;
- TCGv_reg tmp;
+ TCGv_i64 reg;
+ TCGv_i64 tmp;
if (ctl == CR_SAR) {
reg = load_gpr(ctx, a->r);
tmp = tcg_temp_new();
- tcg_gen_andi_reg(tmp, reg, ctx->is_pa20 ? 63 : 31);
+ tcg_gen_andi_i64(tmp, reg, ctx->is_pa20 ? 63 : 31);
save_or_nullify(ctx, cpu_sar, tmp);
cond_free(&ctx->null_cond);
@@ -2167,10 +2069,10 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
/* FIXME: Respect PSW_Q bit */
/* The write advances the queue and stores to the back element. */
tmp = tcg_temp_new();
- tcg_gen_ld_reg(tmp, tcg_env,
+ tcg_gen_ld_i64(tmp, tcg_env,
offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ]));
- tcg_gen_st_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
- tcg_gen_st_reg(reg, tcg_env,
+ tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
+ tcg_gen_st_i64(reg, tcg_env,
offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ]));
break;
@@ -2178,14 +2080,14 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
case CR_PID2:
case CR_PID3:
case CR_PID4:
- tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
+ tcg_gen_st_i64(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
#ifndef CONFIG_USER_ONLY
gen_helper_change_prot_id(tcg_env);
#endif
break;
default:
- tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
+ tcg_gen_st_i64(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
break;
}
return nullify_end(ctx);
@@ -2194,10 +2096,10 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a)
{
- TCGv_reg tmp = tcg_temp_new();
+ TCGv_i64 tmp = tcg_temp_new();
- tcg_gen_not_reg(tmp, load_gpr(ctx, a->r));
- tcg_gen_andi_reg(tmp, tmp, ctx->is_pa20 ? 63 : 31);
+ tcg_gen_not_i64(tmp, load_gpr(ctx, a->r));
+ tcg_gen_andi_i64(tmp, tmp, ctx->is_pa20 ? 63 : 31);
save_or_nullify(ctx, cpu_sar, tmp);
cond_free(&ctx->null_cond);
@@ -2206,11 +2108,11 @@ static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a)
static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a)
{
- TCGv_reg dest = dest_gpr(ctx, a->t);
+ TCGv_i64 dest = dest_gpr(ctx, a->t);
#ifdef CONFIG_USER_ONLY
/* We don't implement space registers in user mode. */
- tcg_gen_movi_reg(dest, 0);
+ tcg_gen_movi_i64(dest, 0);
#else
TCGv_i64 t0 = tcg_temp_new_i64();
@@ -2228,13 +2130,13 @@ static bool trans_rsm(DisasContext *ctx, arg_rsm *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
- TCGv_reg tmp;
+ TCGv_i64 tmp;
nullify_over(ctx);
tmp = tcg_temp_new();
- tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw));
- tcg_gen_andi_reg(tmp, tmp, ~a->i);
+ tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw));
+ tcg_gen_andi_i64(tmp, tmp, ~a->i);
gen_helper_swap_system_mask(tmp, tcg_env, tmp);
save_gpr(ctx, a->t, tmp);
@@ -2248,13 +2150,13 @@ static bool trans_ssm(DisasContext *ctx, arg_ssm *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
- TCGv_reg tmp;
+ TCGv_i64 tmp;
nullify_over(ctx);
tmp = tcg_temp_new();
- tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw));
- tcg_gen_ori_reg(tmp, tmp, a->i);
+ tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw));
+ tcg_gen_ori_i64(tmp, tmp, a->i);
gen_helper_swap_system_mask(tmp, tcg_env, tmp);
save_gpr(ctx, a->t, tmp);
@@ -2268,7 +2170,7 @@ static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
- TCGv_reg tmp, reg;
+ TCGv_i64 tmp, reg;
nullify_over(ctx);
reg = load_gpr(ctx, a->r);
@@ -2345,12 +2247,12 @@ static bool trans_getshadowregs(DisasContext *ctx, arg_getshadowregs *a)
static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a)
{
if (a->m) {
- TCGv_reg dest = dest_gpr(ctx, a->b);
- TCGv_reg src1 = load_gpr(ctx, a->b);
- TCGv_reg src2 = load_gpr(ctx, a->x);
+ TCGv_i64 dest = dest_gpr(ctx, a->b);
+ TCGv_i64 src1 = load_gpr(ctx, a->b);
+ TCGv_i64 src2 = load_gpr(ctx, a->x);
/* The only thing we need to do is the base register modification. */
- tcg_gen_add_reg(dest, src1, src2);
+ tcg_gen_add_i64(dest, src1, src2);
save_gpr(ctx, a->b, dest);
}
cond_free(&ctx->null_cond);
@@ -2359,9 +2261,9 @@ static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a)
static bool trans_probe(DisasContext *ctx, arg_probe *a)
{
- TCGv_reg dest, ofs;
+ TCGv_i64 dest, ofs;
TCGv_i32 level, want;
- TCGv_tl addr;
+ TCGv_i64 addr;
nullify_over(ctx);
@@ -2372,7 +2274,7 @@ static bool trans_probe(DisasContext *ctx, arg_probe *a)
level = tcg_constant_i32(a->ri);
} else {
level = tcg_temp_new_i32();
- tcg_gen_trunc_reg_i32(level, load_gpr(ctx, a->ri));
+ tcg_gen_extrl_i64_i32(level, load_gpr(ctx, a->ri));
tcg_gen_andi_i32(level, level, 3);
}
want = tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ);
@@ -2390,8 +2292,8 @@ static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a)
}
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
- TCGv_tl addr;
- TCGv_reg ofs, reg;
+ TCGv_i64 addr;
+ TCGv_i64 ofs, reg;
nullify_over(ctx);
@@ -2415,8 +2317,8 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
- TCGv_tl addr;
- TCGv_reg ofs;
+ TCGv_i64 addr;
+ TCGv_i64 ofs;
nullify_over(ctx);
@@ -2451,8 +2353,8 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
}
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
- TCGv_tl addr, atl, stl;
- TCGv_reg reg;
+ TCGv_i64 addr, atl, stl;
+ TCGv_i64 reg;
nullify_over(ctx);
@@ -2462,9 +2364,9 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
* return gen_illegal(ctx);
*/
- atl = tcg_temp_new_tl();
- stl = tcg_temp_new_tl();
- addr = tcg_temp_new_tl();
+ atl = tcg_temp_new_i64();
+ stl = tcg_temp_new_i64();
+ addr = tcg_temp_new_i64();
tcg_gen_ld32u_i64(stl, tcg_env,
a->data ? offsetof(CPUHPPAState, cr[CR_ISR])
@@ -2513,8 +2415,8 @@ static bool trans_lpa(DisasContext *ctx, arg_ldst *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
- TCGv_tl vaddr;
- TCGv_reg ofs, paddr;
+ TCGv_i64 vaddr;
+ TCGv_i64 ofs, paddr;
nullify_over(ctx);
@@ -2541,7 +2443,7 @@ static bool trans_lci(DisasContext *ctx, arg_lci *a)
physical address. Two addresses with the same CI have a coherent
view of the cache. Our implementation is to return 0 for all,
since the entire address space is coherent. */
- save_gpr(ctx, a->t, tcg_constant_reg(0));
+ save_gpr(ctx, a->t, tcg_constant_i64(0));
cond_free(&ctx->null_cond);
return true;
@@ -2604,12 +2506,12 @@ static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf_d *a)
static bool trans_andcm(DisasContext *ctx, arg_rrr_cf_d *a)
{
- return do_log_reg(ctx, a, tcg_gen_andc_reg);
+ return do_log_reg(ctx, a, tcg_gen_andc_i64);
}
static bool trans_and(DisasContext *ctx, arg_rrr_cf_d *a)
{
- return do_log_reg(ctx, a, tcg_gen_and_reg);
+ return do_log_reg(ctx, a, tcg_gen_and_i64);
}
static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a)
@@ -2625,8 +2527,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a)
}
if (r2 == 0) { /* COPY */
if (r1 == 0) {
- TCGv_reg dest = dest_gpr(ctx, rt);
- tcg_gen_movi_reg(dest, 0);
+ TCGv_i64 dest = dest_gpr(ctx, rt);
+ tcg_gen_movi_i64(dest, 0);
save_gpr(ctx, rt, dest);
} else {
save_gpr(ctx, rt, cpu_gr[r1]);
@@ -2661,17 +2563,17 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a)
}
#endif
}
- return do_log_reg(ctx, a, tcg_gen_or_reg);
+ return do_log_reg(ctx, a, tcg_gen_or_i64);
}
static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a)
{
- return do_log_reg(ctx, a, tcg_gen_xor_reg);
+ return do_log_reg(ctx, a, tcg_gen_xor_i64);
}
static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf_d *a)
{
- TCGv_reg tcg_r1, tcg_r2;
+ TCGv_i64 tcg_r1, tcg_r2;
if (a->cf) {
nullify_over(ctx);
@@ -2684,20 +2586,20 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf_d *a)
static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a)
{
- TCGv_reg tcg_r1, tcg_r2;
+ TCGv_i64 tcg_r1, tcg_r2;
if (a->cf) {
nullify_over(ctx);
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
- do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_reg);
+ do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_i64);
return nullify_end(ctx);
}
static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc)
{
- TCGv_reg tcg_r1, tcg_r2, tmp;
+ TCGv_i64 tcg_r1, tcg_r2, tmp;
if (a->cf) {
nullify_over(ctx);
@@ -2705,8 +2607,8 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc)
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
tmp = tcg_temp_new();
- tcg_gen_not_reg(tmp, tcg_r2);
- do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_reg);
+ tcg_gen_not_i64(tmp, tcg_r2);
+ do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_i64);
return nullify_end(ctx);
}
@@ -2722,19 +2624,19 @@ static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf_d *a)
static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i)
{
- TCGv_reg tmp;
+ TCGv_i64 tmp;
nullify_over(ctx);
tmp = tcg_temp_new();
- tcg_gen_shri_reg(tmp, cpu_psw_cb, 3);
+ tcg_gen_shri_i64(tmp, cpu_psw_cb, 3);
if (!is_i) {
- tcg_gen_not_reg(tmp, tmp);
+ tcg_gen_not_i64(tmp, tmp);
}
- tcg_gen_andi_reg(tmp, tmp, (uint64_t)0x1111111111111111ull);
- tcg_gen_muli_reg(tmp, tmp, 6);
+ tcg_gen_andi_i64(tmp, tmp, (uint64_t)0x1111111111111111ull);
+ tcg_gen_muli_i64(tmp, tmp, 6);
do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false,
- is_i ? tcg_gen_add_reg : tcg_gen_sub_reg);
+ is_i ? tcg_gen_add_i64 : tcg_gen_sub_i64);
return nullify_end(ctx);
}
@@ -2750,8 +2652,8 @@ static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf_d *a)
static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
{
- TCGv_reg dest, add1, add2, addc, zero, in1, in2;
- TCGv_reg cout;
+ TCGv_i64 dest, add1, add2, addc, zero, in1, in2;
+ TCGv_i64 cout;
nullify_over(ctx);
@@ -2762,11 +2664,11 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
add2 = tcg_temp_new();
addc = tcg_temp_new();
dest = tcg_temp_new();
- zero = tcg_constant_reg(0);
+ zero = tcg_constant_i64(0);
/* Form R1 << 1 | PSW[CB]{8}. */
- tcg_gen_add_reg(add1, in1, in1);
- tcg_gen_add_reg(add1, add1, get_psw_carry(ctx, false));
+ tcg_gen_add_i64(add1, in1, in1);
+ tcg_gen_add_i64(add1, add1, get_psw_carry(ctx, false));
/*
* Add or subtract R2, depending on PSW[V]. Proper computation of
@@ -2774,28 +2676,28 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
* the manual. By extracting and masking V, we can produce the
* proper inputs to the addition without movcond.
*/
- tcg_gen_sextract_reg(addc, cpu_psw_v, 31, 1);
- tcg_gen_xor_reg(add2, in2, addc);
- tcg_gen_andi_reg(addc, addc, 1);
+ tcg_gen_sextract_i64(addc, cpu_psw_v, 31, 1);
+ tcg_gen_xor_i64(add2, in2, addc);
+ tcg_gen_andi_i64(addc, addc, 1);
- tcg_gen_add2_reg(dest, cpu_psw_cb_msb, add1, zero, add2, zero);
- tcg_gen_add2_reg(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero);
+ tcg_gen_add2_i64(dest, cpu_psw_cb_msb, add1, zero, add2, zero);
+ tcg_gen_add2_i64(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero);
/* Write back the result register. */
save_gpr(ctx, a->t, dest);
/* Write back PSW[CB]. */
- tcg_gen_xor_reg(cpu_psw_cb, add1, add2);
- tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest);
+ tcg_gen_xor_i64(cpu_psw_cb, add1, add2);
+ tcg_gen_xor_i64(cpu_psw_cb, cpu_psw_cb, dest);
/* Write back PSW[V] for the division step. */
cout = get_psw_carry(ctx, false);
- tcg_gen_neg_reg(cpu_psw_v, cout);
- tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2);
+ tcg_gen_neg_i64(cpu_psw_v, cout);
+ tcg_gen_xor_i64(cpu_psw_v, cpu_psw_v, in2);
/* Install the new nullification. */
if (a->cf) {
- TCGv_reg sv = NULL;
+ TCGv_i64 sv = NULL;
if (cond_need_sv(a->cf >> 1)) {
/* ??? The lshift is supposed to contribute to overflow. */
sv = do_add_sv(ctx, dest, add1, add2);
@@ -2838,13 +2740,13 @@ static bool trans_subi_tsv(DisasContext *ctx, arg_rri_cf *a)
static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf_d *a)
{
- TCGv_reg tcg_im, tcg_r2;
+ TCGv_i64 tcg_im, tcg_r2;
if (a->cf) {
nullify_over(ctx);
}
- tcg_im = tcg_constant_reg(a->i);
+ tcg_im = tcg_constant_i64(a->i);
tcg_r2 = load_gpr(ctx, a->r);
do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf, a->d);
@@ -2872,8 +2774,8 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a)
static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
{
MemOp mop = MO_TE | MO_ALIGN | a->size;
- TCGv_reg zero, dest, ofs;
- TCGv_tl addr;
+ TCGv_i64 zero, dest, ofs;
+ TCGv_i64 addr;
if (!ctx->is_pa20 && a->size > MO_32) {
return gen_illegal(ctx);
@@ -2902,8 +2804,8 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
*/
gen_helper_ldc_check(addr);
- zero = tcg_constant_reg(0);
- tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop);
+ zero = tcg_constant_i64(0);
+ tcg_gen_atomic_xchg_i64(dest, addr, zero, ctx->mmu_idx, mop);
if (a->m) {
save_gpr(ctx, a->b, ofs);
@@ -2915,8 +2817,8 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
static bool trans_stby(DisasContext *ctx, arg_stby *a)
{
- TCGv_reg ofs, val;
- TCGv_tl addr;
+ TCGv_i64 ofs, val;
+ TCGv_i64 addr;
nullify_over(ctx);
@@ -2937,7 +2839,7 @@ static bool trans_stby(DisasContext *ctx, arg_stby *a)
}
}
if (a->m) {
- tcg_gen_andi_reg(ofs, ofs, ~3);
+ tcg_gen_andi_i64(ofs, ofs, ~3);
save_gpr(ctx, a->b, ofs);
}
@@ -2946,8 +2848,8 @@ static bool trans_stby(DisasContext *ctx, arg_stby *a)
static bool trans_stdby(DisasContext *ctx, arg_stby *a)
{
- TCGv_reg ofs, val;
- TCGv_tl addr;
+ TCGv_i64 ofs, val;
+ TCGv_i64 addr;
nullify_over(ctx);
@@ -2968,7 +2870,7 @@ static bool trans_stdby(DisasContext *ctx, arg_stby *a)
}
}
if (a->m) {
- tcg_gen_andi_reg(ofs, ofs, ~7);
+ tcg_gen_andi_i64(ofs, ofs, ~7);
save_gpr(ctx, a->b, ofs);
}
@@ -2999,9 +2901,9 @@ static bool trans_sta(DisasContext *ctx, arg_ldst *a)
static bool trans_ldil(DisasContext *ctx, arg_ldil *a)
{
- TCGv_reg tcg_rt = dest_gpr(ctx, a->t);
+ TCGv_i64 tcg_rt = dest_gpr(ctx, a->t);
- tcg_gen_movi_reg(tcg_rt, a->i);
+ tcg_gen_movi_i64(tcg_rt, a->i);
save_gpr(ctx, a->t, tcg_rt);
cond_free(&ctx->null_cond);
return true;
@@ -3009,10 +2911,10 @@ static bool trans_ldil(DisasContext *ctx, arg_ldil *a)
static bool trans_addil(DisasContext *ctx, arg_addil *a)
{
- TCGv_reg tcg_rt = load_gpr(ctx, a->r);
- TCGv_reg tcg_r1 = dest_gpr(ctx, 1);
+ TCGv_i64 tcg_rt = load_gpr(ctx, a->r);
+ TCGv_i64 tcg_r1 = dest_gpr(ctx, 1);
- tcg_gen_addi_reg(tcg_r1, tcg_rt, a->i);
+ tcg_gen_addi_i64(tcg_r1, tcg_rt, a->i);
save_gpr(ctx, 1, tcg_r1);
cond_free(&ctx->null_cond);
return true;
@@ -3020,30 +2922,30 @@ static bool trans_addil(DisasContext *ctx, arg_addil *a)
static bool trans_ldo(DisasContext *ctx, arg_ldo *a)
{
- TCGv_reg tcg_rt = dest_gpr(ctx, a->t);
+ TCGv_i64 tcg_rt = dest_gpr(ctx, a->t);
/* Special case rb == 0, for the LDI pseudo-op.
The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */
if (a->b == 0) {
- tcg_gen_movi_reg(tcg_rt, a->i);
+ tcg_gen_movi_i64(tcg_rt, a->i);
} else {
- tcg_gen_addi_reg(tcg_rt, cpu_gr[a->b], a->i);
+ tcg_gen_addi_i64(tcg_rt, cpu_gr[a->b], a->i);
}
save_gpr(ctx, a->t, tcg_rt);
cond_free(&ctx->null_cond);
return true;
}
-static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1,
+static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_i64 in1,
unsigned c, unsigned f, bool d, unsigned n, int disp)
{
- TCGv_reg dest, in2, sv;
+ TCGv_i64 dest, in2, sv;
DisasCond cond;
in2 = load_gpr(ctx, r);
dest = tcg_temp_new();
- tcg_gen_sub_reg(dest, in1, in2);
+ tcg_gen_sub_i64(dest, in1, in2);
sv = NULL;
if (cond_need_sv(c)) {
@@ -3070,14 +2972,14 @@ static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a)
return false;
}
nullify_over(ctx);
- return do_cmpb(ctx, a->r, tcg_constant_reg(a->i),
+ return do_cmpb(ctx, a->r, tcg_constant_i64(a->i),
a->c, a->f, a->d, a->n, a->disp);
}
-static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1,
+static bool do_addb(DisasContext *ctx, unsigned r, TCGv_i64 in1,
unsigned c, unsigned f, unsigned n, int disp)
{
- TCGv_reg dest, in2, sv, cb_cond;
+ TCGv_i64 dest, in2, sv, cb_cond;
DisasCond cond;
bool d = false;
@@ -3098,16 +3000,16 @@ static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1,
cb_cond = NULL;
if (cond_need_cb(c)) {
- TCGv_reg cb = tcg_temp_new();
- TCGv_reg cb_msb = tcg_temp_new();
+ TCGv_i64 cb = tcg_temp_new();
+ TCGv_i64 cb_msb = tcg_temp_new();
- tcg_gen_movi_reg(cb_msb, 0);
- tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb);
- tcg_gen_xor_reg(cb, in1, in2);
- tcg_gen_xor_reg(cb, cb, dest);
+ tcg_gen_movi_i64(cb_msb, 0);
+ tcg_gen_add2_i64(dest, cb_msb, in1, cb_msb, in2, cb_msb);
+ tcg_gen_xor_i64(cb, in1, in2);
+ tcg_gen_xor_i64(cb, cb, dest);
cb_cond = get_carry(ctx, d, cb, cb_msb);
} else {
- tcg_gen_add_reg(dest, in1, in2);
+ tcg_gen_add_i64(dest, in1, in2);
}
if (cond_need_sv(c)) {
sv = do_add_sv(ctx, dest, in1, in2);
@@ -3127,12 +3029,12 @@ static bool trans_addb(DisasContext *ctx, arg_addb *a)
static bool trans_addbi(DisasContext *ctx, arg_addbi *a)
{
nullify_over(ctx);
- return do_addb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a->disp);
+ return do_addb(ctx, a->r, tcg_constant_i64(a->i), a->c, a->f, a->n, a->disp);
}
static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
{
- TCGv_reg tmp, tcg_r;
+ TCGv_i64 tmp, tcg_r;
DisasCond cond;
nullify_over(ctx);
@@ -3141,10 +3043,10 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
tcg_r = load_gpr(ctx, a->r);
if (cond_need_ext(ctx, a->d)) {
/* Force shift into [32,63] */
- tcg_gen_ori_reg(tmp, cpu_sar, 32);
- tcg_gen_shl_reg(tmp, tcg_r, tmp);
+ tcg_gen_ori_i64(tmp, cpu_sar, 32);
+ tcg_gen_shl_i64(tmp, tcg_r, tmp);
} else {
- tcg_gen_shl_reg(tmp, tcg_r, cpu_sar);
+ tcg_gen_shl_i64(tmp, tcg_r, cpu_sar);
}
cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
@@ -3153,7 +3055,7 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
{
- TCGv_reg tmp, tcg_r;
+ TCGv_i64 tmp, tcg_r;
DisasCond cond;
int p;
@@ -3162,7 +3064,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
p = a->p | (cond_need_ext(ctx, a->d) ? 32 : 0);
- tcg_gen_shli_reg(tmp, tcg_r, p);
+ tcg_gen_shli_i64(tmp, tcg_r, p);
cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
return do_cbranch(ctx, a->disp, a->n, &cond);
@@ -3170,16 +3072,16 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
static bool trans_movb(DisasContext *ctx, arg_movb *a)
{
- TCGv_reg dest;
+ TCGv_i64 dest;
DisasCond cond;
nullify_over(ctx);
dest = dest_gpr(ctx, a->r2);
if (a->r1 == 0) {
- tcg_gen_movi_reg(dest, 0);
+ tcg_gen_movi_i64(dest, 0);
} else {
- tcg_gen_mov_reg(dest, cpu_gr[a->r1]);
+ tcg_gen_mov_i64(dest, cpu_gr[a->r1]);
}
/* All MOVB conditions are 32-bit. */
@@ -3189,13 +3091,13 @@ static bool trans_movb(DisasContext *ctx, arg_movb *a)
static bool trans_movbi(DisasContext *ctx, arg_movbi *a)
{
- TCGv_reg dest;
+ TCGv_i64 dest;
DisasCond cond;
nullify_over(ctx);
dest = dest_gpr(ctx, a->r);
- tcg_gen_movi_reg(dest, a->i);
+ tcg_gen_movi_i64(dest, a->i);
/* All MOVBI conditions are 32-bit. */
cond = do_sed_cond(ctx, a->c, false, dest);
@@ -3204,7 +3106,7 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi *a)
static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a)
{
- TCGv_reg dest, tmp;
+ TCGv_i64 dest, tmp;
if (!ctx->is_pa20 && a->d) {
return false;
@@ -3216,40 +3118,40 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a)
dest = dest_gpr(ctx, a->t);
if (a->r1 == 0) {
if (a->d) {
- tcg_gen_shr_reg(dest, dest, cpu_sar);
+ tcg_gen_shr_i64(dest, dest, cpu_sar);
} else {
- tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2));
+ tcg_gen_ext32u_i64(dest, load_gpr(ctx, a->r2));
tmp = tcg_temp_new();
- tcg_gen_andi_reg(tmp, cpu_sar, 31);
- tcg_gen_shr_reg(dest, dest, tmp);
+ tcg_gen_andi_i64(tmp, cpu_sar, 31);
+ tcg_gen_shr_i64(dest, dest, tmp);
}
} else if (a->r1 == a->r2) {
if (a->d) {
- tcg_gen_rotr_reg(dest, load_gpr(ctx, a->r2), cpu_sar);
+ tcg_gen_rotr_i64(dest, load_gpr(ctx, a->r2), cpu_sar);
} else {
TCGv_i32 t32 = tcg_temp_new_i32();
TCGv_i32 s32 = tcg_temp_new_i32();
- tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2));
- tcg_gen_trunc_reg_i32(s32, cpu_sar);
+ tcg_gen_extrl_i64_i32(t32, load_gpr(ctx, a->r2));
+ tcg_gen_extrl_i64_i32(s32, cpu_sar);
tcg_gen_andi_i32(s32, s32, 31);
tcg_gen_rotr_i32(t32, t32, s32);
- tcg_gen_extu_i32_reg(dest, t32);
+ tcg_gen_extu_i32_i64(dest, t32);
}
} else if (a->d) {
- TCGv_reg t = tcg_temp_new();
- TCGv_reg n = tcg_temp_new();
+ TCGv_i64 t = tcg_temp_new();
+ TCGv_i64 n = tcg_temp_new();
- tcg_gen_xori_reg(n, cpu_sar, 63);
- tcg_gen_shl_reg(t, load_gpr(ctx, a->r2), n);
- tcg_gen_shli_reg(t, t, 1);
- tcg_gen_shr_reg(dest, load_gpr(ctx, a->r1), cpu_sar);
- tcg_gen_or_reg(dest, dest, t);
+ tcg_gen_xori_i64(n, cpu_sar, 63);
+ tcg_gen_shl_i64(t, load_gpr(ctx, a->r2), n);
+ tcg_gen_shli_i64(t, t, 1);
+ tcg_gen_shr_i64(dest, load_gpr(ctx, a->r1), cpu_sar);
+ tcg_gen_or_i64(dest, dest, t);
} else {
TCGv_i64 t = tcg_temp_new_i64();
TCGv_i64 s = tcg_temp_new_i64();
- tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1));
+ tcg_gen_concat32_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1));
tcg_gen_extu_reg_i64(s, cpu_sar);
tcg_gen_andi_i64(s, s, 31);
tcg_gen_shr_i64(t, t, s);
@@ -3268,7 +3170,7 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a)
static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a)
{
unsigned width, sa;
- TCGv_reg dest, t2;
+ TCGv_i64 dest, t2;
if (!ctx->is_pa20 && a->d) {
return false;
@@ -3283,19 +3185,19 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a)
dest = dest_gpr(ctx, a->t);
t2 = load_gpr(ctx, a->r2);
if (a->r1 == 0) {
- tcg_gen_extract_reg(dest, t2, sa, width - sa);
+ tcg_gen_extract_i64(dest, t2, sa, width - sa);
} else if (width == TARGET_LONG_BITS) {
- tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa);
+ tcg_gen_extract2_i64(dest, t2, cpu_gr[a->r1], sa);
} else {
assert(!a->d);
if (a->r1 == a->r2) {
TCGv_i32 t32 = tcg_temp_new_i32();
- tcg_gen_trunc_reg_i32(t32, t2);
+ tcg_gen_extrl_i64_i32(t32, t2);
tcg_gen_rotri_i32(t32, t32, sa);
- tcg_gen_extu_i32_reg(dest, t32);
+ tcg_gen_extu_i32_i64(dest, t32);
} else {
TCGv_i64 t64 = tcg_temp_new_i64();
- tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]);
+ tcg_gen_concat32_i64(t64, t2, cpu_gr[a->r1]);
tcg_gen_shri_i64(t64, t64, sa);
tcg_gen_trunc_i64_reg(dest, t64);
}
@@ -3313,7 +3215,7 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a)
static bool trans_extr_sar(DisasContext *ctx, arg_extr_sar *a)
{
unsigned widthm1 = a->d ? 63 : 31;
- TCGv_reg dest, src, tmp;
+ TCGv_i64 dest, src, tmp;
if (!ctx->is_pa20 && a->d) {
return false;
@@ -3327,15 +3229,15 @@ static bool trans_extr_sar(DisasContext *ctx, arg_extr_sar *a)
tmp = tcg_temp_new();
/* Recall that SAR is using big-endian bit numbering. */
- tcg_gen_andi_reg(tmp, cpu_sar, widthm1);
- tcg_gen_xori_reg(tmp, tmp, widthm1);
+ tcg_gen_andi_i64(tmp, cpu_sar, widthm1);
+ tcg_gen_xori_i64(tmp, tmp, widthm1);
if (a->se) {
- tcg_gen_sar_reg(dest, src, tmp);
- tcg_gen_sextract_reg(dest, dest, 0, a->len);
+ tcg_gen_sar_i64(dest, src, tmp);
+ tcg_gen_sextract_i64(dest, dest, 0, a->len);
} else {
- tcg_gen_shr_reg(dest, src, tmp);
- tcg_gen_extract_reg(dest, dest, 0, a->len);
+ tcg_gen_shr_i64(dest, src, tmp);
+ tcg_gen_extract_i64(dest, dest, 0, a->len);
}
save_gpr(ctx, a->t, dest);
@@ -3350,7 +3252,7 @@ static bool trans_extr_sar(DisasContext *ctx, arg_extr_sar *a)
static bool trans_extr_imm(DisasContext *ctx, arg_extr_imm *a)
{
unsigned len, cpos, width;
- TCGv_reg dest, src;
+ TCGv_i64 dest, src;
if (!ctx->is_pa20 && a->d) {
return false;
@@ -3369,9 +3271,9 @@ static bool trans_extr_imm(DisasContext *ctx, arg_extr_imm *a)
dest = dest_gpr(ctx, a->t);
src = load_gpr(ctx, a->r);
if (a->se) {
- tcg_gen_sextract_reg(dest, src, cpos, len);
+ tcg_gen_sextract_i64(dest, src, cpos, len);
} else {
- tcg_gen_extract_reg(dest, src, cpos, len);
+ tcg_gen_extract_i64(dest, src, cpos, len);
}
save_gpr(ctx, a->t, dest);
@@ -3387,7 +3289,7 @@ static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a)
{
unsigned len, width;
uint64_t mask0, mask1;
- TCGv_reg dest;
+ TCGv_i64 dest;
if (!ctx->is_pa20 && a->d) {
return false;
@@ -3407,11 +3309,11 @@ static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a)
mask1 = deposit64(-1, a->cpos, len, a->i);
if (a->nz) {
- TCGv_reg src = load_gpr(ctx, a->t);
- tcg_gen_andi_reg(dest, src, mask1);
- tcg_gen_ori_reg(dest, dest, mask0);
+ TCGv_i64 src = load_gpr(ctx, a->t);
+ tcg_gen_andi_i64(dest, src, mask1);
+ tcg_gen_ori_i64(dest, dest, mask0);
} else {
- tcg_gen_movi_reg(dest, mask0);
+ tcg_gen_movi_i64(dest, mask0);
}
save_gpr(ctx, a->t, dest);
@@ -3427,7 +3329,7 @@ static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a)
{
unsigned rs = a->nz ? a->t : 0;
unsigned len, width;
- TCGv_reg dest, val;
+ TCGv_i64 dest, val;
if (!ctx->is_pa20 && a->d) {
return false;
@@ -3445,9 +3347,9 @@ static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a)
dest = dest_gpr(ctx, a->t);
val = load_gpr(ctx, a->r);
if (rs == 0) {
- tcg_gen_deposit_z_reg(dest, val, a->cpos, len);
+ tcg_gen_deposit_z_i64(dest, val, a->cpos, len);
} else {
- tcg_gen_deposit_reg(dest, cpu_gr[rs], val, a->cpos, len);
+ tcg_gen_deposit_i64(dest, cpu_gr[rs], val, a->cpos, len);
}
save_gpr(ctx, a->t, dest);
@@ -3460,11 +3362,11 @@ static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a)
}
static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c,
- bool d, bool nz, unsigned len, TCGv_reg val)
+ bool d, bool nz, unsigned len, TCGv_i64 val)
{
unsigned rs = nz ? rt : 0;
unsigned widthm1 = d ? 63 : 31;
- TCGv_reg mask, tmp, shift, dest;
+ TCGv_i64 mask, tmp, shift, dest;
uint64_t msb = 1ULL << (len - 1);
dest = dest_gpr(ctx, rt);
@@ -3472,19 +3374,19 @@ static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c,
tmp = tcg_temp_new();
/* Convert big-endian bit numbering in SAR to left-shift. */
- tcg_gen_andi_reg(shift, cpu_sar, widthm1);
- tcg_gen_xori_reg(shift, shift, widthm1);
+ tcg_gen_andi_i64(shift, cpu_sar, widthm1);
+ tcg_gen_xori_i64(shift, shift, widthm1);
mask = tcg_temp_new();
- tcg_gen_movi_reg(mask, msb + (msb - 1));
- tcg_gen_and_reg(tmp, val, mask);
+ tcg_gen_movi_i64(mask, msb + (msb - 1));
+ tcg_gen_and_i64(tmp, val, mask);
if (rs) {
- tcg_gen_shl_reg(mask, mask, shift);
- tcg_gen_shl_reg(tmp, tmp, shift);
- tcg_gen_andc_reg(dest, cpu_gr[rs], mask);
- tcg_gen_or_reg(dest, dest, tmp);
+ tcg_gen_shl_i64(mask, mask, shift);
+ tcg_gen_shl_i64(tmp, tmp, shift);
+ tcg_gen_andc_i64(dest, cpu_gr[rs], mask);
+ tcg_gen_or_i64(dest, dest, tmp);
} else {
- tcg_gen_shl_reg(dest, tmp, shift);
+ tcg_gen_shl_i64(dest, tmp, shift);
}
save_gpr(ctx, rt, dest);
@@ -3517,12 +3419,12 @@ static bool trans_depi_sar(DisasContext *ctx, arg_depi_sar *a)
nullify_over(ctx);
}
return do_dep_sar(ctx, a->t, a->c, a->d, a->nz, a->len,
- tcg_constant_reg(a->i));
+ tcg_constant_i64(a->i));
}
static bool trans_be(DisasContext *ctx, arg_be *a)
{
- TCGv_reg tmp;
+ TCGv_i64 tmp;
#ifdef CONFIG_USER_ONLY
/* ??? It seems like there should be a good way of using
@@ -3541,7 +3443,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a)
#endif
tmp = tcg_temp_new();
- tcg_gen_addi_reg(tmp, load_gpr(ctx, a->b), a->disp);
+ tcg_gen_addi_i64(tmp, load_gpr(ctx, a->b), a->disp);
tmp = do_ibranch_priv(ctx, tmp);
#ifdef CONFIG_USER_ONLY
@@ -3555,8 +3457,8 @@ static bool trans_be(DisasContext *ctx, arg_be *a)
tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f);
}
if (a->n && use_nullify_skip(ctx)) {
- tcg_gen_mov_reg(cpu_iaoq_f, tmp);
- tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4);
+ tcg_gen_mov_i64(cpu_iaoq_f, tmp);
+ tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, 4);
tcg_gen_mov_i64(cpu_iasq_f, new_spc);
tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f);
} else {
@@ -3564,7 +3466,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a)
if (ctx->iaoq_b == -1) {
tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b);
}
- tcg_gen_mov_reg(cpu_iaoq_b, tmp);
+ tcg_gen_mov_i64(cpu_iaoq_b, tmp);
tcg_gen_mov_i64(cpu_iasq_b, new_spc);
nullify_set(ctx, a->n);
}
@@ -3623,11 +3525,11 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a)
#endif
if (a->l) {
- TCGv_reg tmp = dest_gpr(ctx, a->l);
+ TCGv_i64 tmp = dest_gpr(ctx, a->l);
if (ctx->privilege < 3) {
- tcg_gen_andi_reg(tmp, tmp, -4);
+ tcg_gen_andi_i64(tmp, tmp, -4);
}
- tcg_gen_ori_reg(tmp, tmp, ctx->privilege);
+ tcg_gen_ori_i64(tmp, tmp, ctx->privilege);
save_gpr(ctx, a->l, tmp);
}
@@ -3637,9 +3539,9 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a)
static bool trans_blr(DisasContext *ctx, arg_blr *a)
{
if (a->x) {
- TCGv_reg tmp = tcg_temp_new();
- tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3);
- tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8);
+ TCGv_i64 tmp = tcg_temp_new();
+ tcg_gen_shli_i64(tmp, load_gpr(ctx, a->x), 3);
+ tcg_gen_addi_i64(tmp, tmp, ctx->iaoq_f + 8);
/* The computation here never changes privilege level. */
return do_ibranch(ctx, tmp, a->l, a->n);
} else {
@@ -3650,14 +3552,14 @@ static bool trans_blr(DisasContext *ctx, arg_blr *a)
static bool trans_bv(DisasContext *ctx, arg_bv *a)
{
- TCGv_reg dest;
+ TCGv_i64 dest;
if (a->x == 0) {
dest = load_gpr(ctx, a->b);
} else {
dest = tcg_temp_new();
- tcg_gen_shli_reg(dest, load_gpr(ctx, a->x), 3);
- tcg_gen_add_reg(dest, dest, load_gpr(ctx, a->b));
+ tcg_gen_shli_i64(dest, load_gpr(ctx, a->x), 3);
+ tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b));
}
dest = do_ibranch_priv(ctx, dest);
return do_ibranch(ctx, dest, 0, a->n);
@@ -3665,7 +3567,7 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a)
static bool trans_bve(DisasContext *ctx, arg_bve *a)
{
- TCGv_reg dest;
+ TCGv_i64 dest;
#ifdef CONFIG_USER_ONLY
dest = do_ibranch_priv(ctx, load_gpr(ctx, a->b));
@@ -3988,12 +3890,12 @@ static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a)
static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
{
- TCGv_reg t;
+ TCGv_i64 t;
nullify_over(ctx);
t = tcg_temp_new();
- tcg_gen_ld32u_reg(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow));
+ tcg_gen_ld32u_i64(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow));
if (a->y == 1) {
int mask;
@@ -4001,7 +3903,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
switch (a->c) {
case 0: /* simple */
- tcg_gen_andi_reg(t, t, 0x4000000);
+ tcg_gen_andi_i64(t, t, 0x4000000);
ctx->null_cond = cond_make_0(TCG_COND_NE, t);
goto done;
case 2: /* rej */
@@ -4030,17 +3932,17 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
return true;
}
if (inv) {
- TCGv_reg c = tcg_constant_reg(mask);
- tcg_gen_or_reg(t, t, c);
+ TCGv_i64 c = tcg_constant_i64(mask);
+ tcg_gen_or_i64(t, t, c);
ctx->null_cond = cond_make(TCG_COND_EQ, t, c);
} else {
- tcg_gen_andi_reg(t, t, mask);
+ tcg_gen_andi_i64(t, t, mask);
ctx->null_cond = cond_make_0(TCG_COND_EQ, t);
}
} else {
unsigned cbit = (a->y ^ 1) - 1;
- tcg_gen_extract_reg(t, t, 21 - cbit, 1);
+ tcg_gen_extract_i64(t, t, 21 - cbit, 1);
ctx->null_cond = cond_make_0(TCG_COND_NE, t);
}
@@ -4295,7 +4197,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
if (ctx->iaoq_b == -1) {
ctx->iaoq_n = -1;
ctx->iaoq_n_var = tcg_temp_new();
- tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4);
+ tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4);
} else {
ctx->iaoq_n = ctx->iaoq_b + 4;
ctx->iaoq_n_var = NULL;
@@ -4341,7 +4243,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
case DISAS_IAQ_N_STALE:
case DISAS_IAQ_N_STALE_EXIT:
if (ctx->iaoq_f == -1) {
- tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b);
+ tcg_gen_mov_i64(cpu_iaoq_f, cpu_iaoq_b);
copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var);
#ifndef CONFIG_USER_ONLY
tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b);
@@ -4351,7 +4253,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
? DISAS_EXIT
: DISAS_IAQ_N_UPDATED);
} else if (ctx->iaoq_b == -1) {
- tcg_gen_mov_reg(cpu_iaoq_b, ctx->iaoq_n_var);
+ tcg_gen_mov_i64(cpu_iaoq_b, ctx->iaoq_n_var);
}
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 48/61] target/hppa: Remove remaining TARGET_REGISTER_BITS redirections
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (46 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 47/61] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 49/61] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new Richard Henderson
` (12 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
The conversions to/from i64 can be eliminated entirely,
folding computation into adjacent operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 46 ++++++++++++-----------------------------
1 file changed, 13 insertions(+), 33 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 682cb518d6..c782c57149 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -33,15 +33,6 @@
#undef HELPER_H
-/* Since we have a distinction between register size and address size,
- we need to redefine all of these. */
-
-#define tcg_gen_extu_reg_tl tcg_gen_mov_i64
-#define tcg_gen_trunc_i64_reg tcg_gen_mov_i64
-#define tcg_gen_extu_reg_i64 tcg_gen_mov_i64
-#define tcg_gen_ext_reg_i64 tcg_gen_mov_i64
-
-
typedef struct DisasCond {
TCGCond c;
TCGv_i64 a0, a1;
@@ -1332,8 +1323,7 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs,
*pofs = ofs;
*pgva = addr = tcg_temp_new_i64();
- tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base);
- tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx));
+ tcg_gen_andi_tl(addr, modify <= 0 ? ofs : base, gva_offset_mask(ctx));
#ifndef CONFIG_USER_ONLY
if (!is_phys) {
tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base));
@@ -1945,13 +1935,11 @@ static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a)
unsigned rt = a->t;
unsigned rs = a->sp;
TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new();
load_spr(ctx, t0, rs);
tcg_gen_shri_i64(t0, t0, 32);
- tcg_gen_trunc_i64_reg(t1, t0);
- save_gpr(ctx, rt, t1);
+ save_gpr(ctx, rt, t0);
cond_free(&ctx->null_cond);
return true;
@@ -2008,22 +1996,21 @@ static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a)
{
unsigned rr = a->r;
unsigned rs = a->sp;
- TCGv_i64 t64;
+ TCGv_i64 tmp;
if (rs >= 5) {
CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG);
}
nullify_over(ctx);
- t64 = tcg_temp_new_i64();
- tcg_gen_extu_reg_i64(t64, load_gpr(ctx, rr));
- tcg_gen_shli_i64(t64, t64, 32);
+ tmp = tcg_temp_new_i64();
+ tcg_gen_shli_i64(tmp, load_gpr(ctx, rr), 32);
if (rs >= 4) {
- tcg_gen_st_i64(t64, tcg_env, offsetof(CPUHPPAState, sr[rs]));
+ tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUHPPAState, sr[rs]));
ctx->tb_flags &= ~TB_FLAG_SR_SAME;
} else {
- tcg_gen_mov_i64(cpu_sr[rs], t64);
+ tcg_gen_mov_i64(cpu_sr[rs], tmp);
}
return nullify_end(ctx);
@@ -2114,11 +2101,8 @@ static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a)
/* We don't implement space registers in user mode. */
tcg_gen_movi_i64(dest, 0);
#else
- TCGv_i64 t0 = tcg_temp_new_i64();
-
- tcg_gen_mov_i64(t0, space_select(ctx, a->sp, load_gpr(ctx, a->b)));
- tcg_gen_shri_i64(t0, t0, 32);
- tcg_gen_trunc_i64_reg(dest, t0);
+ tcg_gen_mov_i64(dest, space_select(ctx, a->sp, load_gpr(ctx, a->b)));
+ tcg_gen_shri_i64(dest, dest, 32);
#endif
save_gpr(ctx, a->t, dest);
@@ -3152,10 +3136,8 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a)
TCGv_i64 s = tcg_temp_new_i64();
tcg_gen_concat32_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1));
- tcg_gen_extu_reg_i64(s, cpu_sar);
- tcg_gen_andi_i64(s, s, 31);
- tcg_gen_shr_i64(t, t, s);
- tcg_gen_trunc_i64_reg(dest, t);
+ tcg_gen_andi_i64(s, cpu_sar, 31);
+ tcg_gen_shr_i64(dest, t, s);
}
save_gpr(ctx, a->t, dest);
@@ -3196,10 +3178,8 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a)
tcg_gen_rotri_i32(t32, t32, sa);
tcg_gen_extu_i32_i64(dest, t32);
} else {
- TCGv_i64 t64 = tcg_temp_new_i64();
- tcg_gen_concat32_i64(t64, t2, cpu_gr[a->r1]);
- tcg_gen_shri_i64(t64, t64, sa);
- tcg_gen_trunc_i64_reg(dest, t64);
+ tcg_gen_concat32_i64(dest, t2, cpu_gr[a->r1]);
+ tcg_gen_extract_i64(dest, dest, sa, 32);
}
}
save_gpr(ctx, a->t, dest);
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 49/61] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (47 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 48/61] target/hppa: Remove remaining " Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 50/61] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 Richard Henderson
` (11 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 158 ++++++++++++++++++++--------------------
1 file changed, 80 insertions(+), 78 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index c782c57149..4a2bfb7757 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -32,6 +32,8 @@
#include "exec/helper-info.c.inc"
#undef HELPER_H
+/* Choose to use explicit sizes within this file. */
+#undef tcg_temp_new
typedef struct DisasCond {
TCGCond c;
@@ -269,15 +271,15 @@ static DisasCond cond_make_0_tmp(TCGCond c, TCGv_i64 a0)
static DisasCond cond_make_0(TCGCond c, TCGv_i64 a0)
{
- TCGv_i64 tmp = tcg_temp_new();
+ TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_mov_i64(tmp, a0);
return cond_make_0_tmp(c, tmp);
}
static DisasCond cond_make(TCGCond c, TCGv_i64 a0, TCGv_i64 a1)
{
- TCGv_i64 t0 = tcg_temp_new();
- TCGv_i64 t1 = tcg_temp_new();
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
tcg_gen_mov_i64(t0, a0);
tcg_gen_mov_i64(t1, a1);
@@ -302,7 +304,7 @@ static void cond_free(DisasCond *cond)
static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg)
{
if (reg == 0) {
- TCGv_i64 t = tcg_temp_new();
+ TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_movi_i64(t, 0);
return t;
} else {
@@ -313,7 +315,7 @@ static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg)
static TCGv_i64 dest_gpr(DisasContext *ctx, unsigned reg)
{
if (reg == 0 || ctx->null_cond.c != TCG_COND_NEVER) {
- return tcg_temp_new();
+ return tcg_temp_new_i64();
} else {
return cpu_gr[reg];
}
@@ -437,7 +439,7 @@ static void nullify_over(DisasContext *ctx)
/* If we're using PSW[N], copy it to a temp because... */
if (ctx->null_cond.a0 == cpu_psw_n) {
- ctx->null_cond.a0 = tcg_temp_new();
+ ctx->null_cond.a0 = tcg_temp_new_i64();
tcg_gen_mov_i64(ctx->null_cond.a0, cpu_psw_n);
}
/* ... we clear it before branching over the implementation,
@@ -644,14 +646,14 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
break;
case 1: /* = / <> (Z / !Z) */
if (cond_need_ext(ctx, d)) {
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_ext32u_i64(tmp, res);
res = tmp;
}
cond = cond_make_0(TCG_COND_EQ, res);
break;
case 2: /* < / >= (N ^ V / !(N ^ V) */
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_xor_i64(tmp, res, sv);
if (cond_need_ext(ctx, d)) {
tcg_gen_ext32s_i64(tmp, tmp);
@@ -668,7 +670,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
* !(~(res ^ sv) >> 31) | !res
* !(~(res ^ sv) >> 31 & res)
*/
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_eqv_i64(tmp, res, sv);
if (cond_need_ext(ctx, d)) {
tcg_gen_sextract_i64(tmp, tmp, 31, 1);
@@ -685,7 +687,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
cond = cond_make_0(TCG_COND_EQ, cb_msb);
break;
case 5: /* ZNV / VNZ (!C | Z / C & !Z) */
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_neg_i64(tmp, cb_msb);
tcg_gen_and_i64(tmp, tmp, res);
if (cond_need_ext(ctx, d)) {
@@ -695,14 +697,14 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
break;
case 6: /* SV / NSV (V / !V) */
if (cond_need_ext(ctx, d)) {
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_ext32s_i64(tmp, sv);
sv = tmp;
}
cond = cond_make_0(TCG_COND_LT, sv);
break;
case 7: /* OD / EV */
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_andi_i64(tmp, res, 1);
cond = cond_make_0_tmp(TCG_COND_NE, tmp);
break;
@@ -756,8 +758,8 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d,
tc = tcg_invert_cond(tc);
}
if (cond_need_ext(ctx, d)) {
- TCGv_i64 t1 = tcg_temp_new();
- TCGv_i64 t2 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
if (ext_uns) {
tcg_gen_ext32u_i64(t1, in1);
@@ -833,7 +835,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d,
}
if (cond_need_ext(ctx, d)) {
- TCGv_i64 tmp = tcg_temp_new();
+ TCGv_i64 tmp = tcg_temp_new_i64();
if (ext_uns) {
tcg_gen_ext32u_i64(tmp, res);
@@ -878,8 +880,8 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res,
* do our normal thing and compute carry-in of bit B+1 since that
* leaves us with carry bits spread across two words.
*/
- cb = tcg_temp_new();
- tmp = tcg_temp_new();
+ cb = tcg_temp_new_i64();
+ tmp = tcg_temp_new_i64();
tcg_gen_or_i64(cb, in1, in2);
tcg_gen_and_i64(tmp, in1, in2);
tcg_gen_andc_i64(cb, cb, res);
@@ -897,7 +899,7 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res,
/* See hasless(v,1) from
* https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
*/
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_subi_i64(tmp, res, d_repl * 0x01010101u);
tcg_gen_andc_i64(tmp, tmp, res);
tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80808080u);
@@ -905,7 +907,7 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res,
break;
case 3: /* SHZ / NHZ */
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_subi_i64(tmp, res, d_repl * 0x00010001u);
tcg_gen_andc_i64(tmp, tmp, res);
tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80008000u);
@@ -941,7 +943,7 @@ static TCGv_i64 get_carry(DisasContext *ctx, bool d,
TCGv_i64 cb, TCGv_i64 cb_msb)
{
if (cond_need_ext(ctx, d)) {
- TCGv_i64 t = tcg_temp_new();
+ TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_extract_i64(t, cb, 32, 1);
return t;
}
@@ -957,8 +959,8 @@ static TCGv_i64 get_psw_carry(DisasContext *ctx, bool d)
static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 res,
TCGv_i64 in1, TCGv_i64 in2)
{
- TCGv_i64 sv = tcg_temp_new();
- TCGv_i64 tmp = tcg_temp_new();
+ TCGv_i64 sv = tcg_temp_new_i64();
+ TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_xor_i64(sv, res, in1);
tcg_gen_xor_i64(tmp, in1, in2);
@@ -971,8 +973,8 @@ static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 res,
static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res,
TCGv_i64 in1, TCGv_i64 in2)
{
- TCGv_i64 sv = tcg_temp_new();
- TCGv_i64 tmp = tcg_temp_new();
+ TCGv_i64 sv = tcg_temp_new_i64();
+ TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_xor_i64(sv, res, in1);
tcg_gen_xor_i64(tmp, in1, in2);
@@ -989,21 +991,21 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
unsigned c = cf >> 1;
DisasCond cond;
- dest = tcg_temp_new();
+ dest = tcg_temp_new_i64();
cb = NULL;
cb_msb = NULL;
cb_cond = NULL;
if (shift) {
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_shli_i64(tmp, in1, shift);
in1 = tmp;
}
if (!is_l || cond_need_cb(c)) {
TCGv_i64 zero = tcg_constant_i64(0);
- cb_msb = tcg_temp_new();
- cb = tcg_temp_new();
+ cb_msb = tcg_temp_new_i64();
+ cb = tcg_temp_new_i64();
tcg_gen_add2_i64(dest, cb_msb, in1, zero, in2, zero);
if (is_c) {
@@ -1035,7 +1037,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
/* Emit any conditional trap before any writeback. */
cond = do_cond(ctx, cf, d, dest, cb_cond, sv);
if (is_tc) {
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1);
gen_helper_tcond(tcg_env, tmp);
}
@@ -1090,9 +1092,9 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
unsigned c = cf >> 1;
DisasCond cond;
- dest = tcg_temp_new();
- cb = tcg_temp_new();
- cb_msb = tcg_temp_new();
+ dest = tcg_temp_new_i64();
+ cb = tcg_temp_new_i64();
+ cb_msb = tcg_temp_new_i64();
zero = tcg_constant_i64(0);
if (is_b) {
@@ -1131,7 +1133,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
/* Emit any conditional trap before any writeback. */
if (is_tc) {
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1);
gen_helper_tcond(tcg_env, tmp);
}
@@ -1180,7 +1182,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
TCGv_i64 dest, sv;
DisasCond cond;
- dest = tcg_temp_new();
+ dest = tcg_temp_new_i64();
tcg_gen_sub_i64(dest, in1, in2);
/* Compute signed overflow if required. */
@@ -1245,13 +1247,13 @@ static void do_unit(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
save_gpr(ctx, rt, dest);
cond_free(&ctx->null_cond);
} else {
- dest = tcg_temp_new();
+ dest = tcg_temp_new_i64();
fn(dest, in1, in2);
cond = do_unit_cond(cf, d, dest, in1, in2);
if (is_tc) {
- TCGv_i64 tmp = tcg_temp_new();
+ TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1);
gen_helper_tcond(tcg_env, tmp);
}
@@ -1286,7 +1288,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_i64 base)
}
ptr = tcg_temp_new_ptr();
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
spc = tcg_temp_new_i64();
/* Extract top 2 bits of the address, shift left 3 for uint64_t index. */
@@ -1311,11 +1313,11 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs,
/* Note that RX is mutually exclusive with DISP. */
if (rx) {
- ofs = tcg_temp_new();
+ ofs = tcg_temp_new_i64();
tcg_gen_shli_i64(ofs, cpu_gr[rx], scale);
tcg_gen_add_i64(ofs, ofs, base);
} else if (disp || modify) {
- ofs = tcg_temp_new();
+ ofs = tcg_temp_new_i64();
tcg_gen_addi_i64(ofs, base, disp);
} else {
ofs = base;
@@ -1421,7 +1423,7 @@ static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,
dest = dest_gpr(ctx, rt);
} else {
/* Make sure if RT == RB, we see the result of the load. */
- dest = tcg_temp_new();
+ dest = tcg_temp_new_i64();
}
do_load_64(ctx, dest, rb, rx, scale, disp, sp, modify, mop);
save_gpr(ctx, rt, dest);
@@ -1737,7 +1739,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest,
if (link != 0) {
copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var);
}
- next = tcg_temp_new();
+ next = tcg_temp_new_i64();
tcg_gen_mov_i64(next, dest);
if (is_n) {
if (use_nullify_skip(ctx)) {
@@ -1778,8 +1780,8 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest,
a0 = ctx->null_cond.a0;
a1 = ctx->null_cond.a1;
- tmp = tcg_temp_new();
- next = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
+ next = tcg_temp_new_i64();
copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var);
tcg_gen_movcond_i64(c, next, a0, a1, tmp, dest);
@@ -1821,11 +1823,11 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset)
return offset;
case 3:
/* Privilege 3 is minimum and is never allowed to increase. */
- dest = tcg_temp_new();
+ dest = tcg_temp_new_i64();
tcg_gen_ori_i64(dest, offset, 3);
break;
default:
- dest = tcg_temp_new();
+ dest = tcg_temp_new_i64();
tcg_gen_andi_i64(dest, offset, -4);
tcg_gen_ori_i64(dest, dest, ctx->privilege);
tcg_gen_movcond_i64(TCG_COND_GTU, dest, dest, offset, dest, offset);
@@ -1983,7 +1985,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a)
break;
}
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
save_gpr(ctx, rt, tmp);
@@ -2024,7 +2026,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
if (ctl == CR_SAR) {
reg = load_gpr(ctx, a->r);
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_andi_i64(tmp, reg, ctx->is_pa20 ? 63 : 31);
save_or_nullify(ctx, cpu_sar, tmp);
@@ -2055,7 +2057,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
case CR_IIAOQ:
/* FIXME: Respect PSW_Q bit */
/* The write advances the queue and stores to the back element. */
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, tcg_env,
offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ]));
tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl]));
@@ -2083,7 +2085,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a)
{
- TCGv_i64 tmp = tcg_temp_new();
+ TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_not_i64(tmp, load_gpr(ctx, a->r));
tcg_gen_andi_i64(tmp, tmp, ctx->is_pa20 ? 63 : 31);
@@ -2118,7 +2120,7 @@ static bool trans_rsm(DisasContext *ctx, arg_rsm *a)
nullify_over(ctx);
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw));
tcg_gen_andi_i64(tmp, tmp, ~a->i);
gen_helper_swap_system_mask(tmp, tcg_env, tmp);
@@ -2138,7 +2140,7 @@ static bool trans_ssm(DisasContext *ctx, arg_ssm *a)
nullify_over(ctx);
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw));
tcg_gen_ori_i64(tmp, tmp, a->i);
gen_helper_swap_system_mask(tmp, tcg_env, tmp);
@@ -2158,7 +2160,7 @@ static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a)
nullify_over(ctx);
reg = load_gpr(ctx, a->r);
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
gen_helper_swap_system_mask(tmp, tcg_env, reg);
/* Exit the TB to recognize new interrupts. */
@@ -2406,7 +2408,7 @@ static bool trans_lpa(DisasContext *ctx, arg_ldst *a)
form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false);
- paddr = tcg_temp_new();
+ paddr = tcg_temp_new_i64();
gen_helper_lpa(paddr, tcg_env, vaddr);
/* Note that physical address result overrides base modification. */
@@ -2590,7 +2592,7 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc)
}
tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2);
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_not_i64(tmp, tcg_r2);
do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_i64);
return nullify_end(ctx);
@@ -2612,7 +2614,7 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i)
nullify_over(ctx);
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_shri_i64(tmp, cpu_psw_cb, 3);
if (!is_i) {
tcg_gen_not_i64(tmp, tmp);
@@ -2644,10 +2646,10 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
in1 = load_gpr(ctx, a->r1);
in2 = load_gpr(ctx, a->r2);
- add1 = tcg_temp_new();
- add2 = tcg_temp_new();
- addc = tcg_temp_new();
- dest = tcg_temp_new();
+ add1 = tcg_temp_new_i64();
+ add2 = tcg_temp_new_i64();
+ addc = tcg_temp_new_i64();
+ dest = tcg_temp_new_i64();
zero = tcg_constant_i64(0);
/* Form R1 << 1 | PSW[CB]{8}. */
@@ -2770,7 +2772,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
if (a->m) {
/* Base register modification. Make sure if RT == RB,
we see the result of the load. */
- dest = tcg_temp_new();
+ dest = tcg_temp_new_i64();
} else {
dest = dest_gpr(ctx, a->t);
}
@@ -2927,7 +2929,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_i64 in1,
DisasCond cond;
in2 = load_gpr(ctx, r);
- dest = tcg_temp_new();
+ dest = tcg_temp_new_i64();
tcg_gen_sub_i64(dest, in1, in2);
@@ -2979,13 +2981,13 @@ static bool do_addb(DisasContext *ctx, unsigned r, TCGv_i64 in1,
}
in2 = load_gpr(ctx, r);
- dest = tcg_temp_new();
+ dest = tcg_temp_new_i64();
sv = NULL;
cb_cond = NULL;
if (cond_need_cb(c)) {
- TCGv_i64 cb = tcg_temp_new();
- TCGv_i64 cb_msb = tcg_temp_new();
+ TCGv_i64 cb = tcg_temp_new_i64();
+ TCGv_i64 cb_msb = tcg_temp_new_i64();
tcg_gen_movi_i64(cb_msb, 0);
tcg_gen_add2_i64(dest, cb_msb, in1, cb_msb, in2, cb_msb);
@@ -3023,7 +3025,7 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
nullify_over(ctx);
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_r = load_gpr(ctx, a->r);
if (cond_need_ext(ctx, a->d)) {
/* Force shift into [32,63] */
@@ -3045,7 +3047,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
nullify_over(ctx);
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_r = load_gpr(ctx, a->r);
p = a->p | (cond_need_ext(ctx, a->d) ? 32 : 0);
tcg_gen_shli_i64(tmp, tcg_r, p);
@@ -3105,7 +3107,7 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a)
tcg_gen_shr_i64(dest, dest, cpu_sar);
} else {
tcg_gen_ext32u_i64(dest, load_gpr(ctx, a->r2));
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_andi_i64(tmp, cpu_sar, 31);
tcg_gen_shr_i64(dest, dest, tmp);
}
@@ -3123,8 +3125,8 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a)
tcg_gen_extu_i32_i64(dest, t32);
}
} else if (a->d) {
- TCGv_i64 t = tcg_temp_new();
- TCGv_i64 n = tcg_temp_new();
+ TCGv_i64 t = tcg_temp_new_i64();
+ TCGv_i64 n = tcg_temp_new_i64();
tcg_gen_xori_i64(n, cpu_sar, 63);
tcg_gen_shl_i64(t, load_gpr(ctx, a->r2), n);
@@ -3206,7 +3208,7 @@ static bool trans_extr_sar(DisasContext *ctx, arg_extr_sar *a)
dest = dest_gpr(ctx, a->t);
src = load_gpr(ctx, a->r);
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
/* Recall that SAR is using big-endian bit numbering. */
tcg_gen_andi_i64(tmp, cpu_sar, widthm1);
@@ -3350,14 +3352,14 @@ static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c,
uint64_t msb = 1ULL << (len - 1);
dest = dest_gpr(ctx, rt);
- shift = tcg_temp_new();
- tmp = tcg_temp_new();
+ shift = tcg_temp_new_i64();
+ tmp = tcg_temp_new_i64();
/* Convert big-endian bit numbering in SAR to left-shift. */
tcg_gen_andi_i64(shift, cpu_sar, widthm1);
tcg_gen_xori_i64(shift, shift, widthm1);
- mask = tcg_temp_new();
+ mask = tcg_temp_new_i64();
tcg_gen_movi_i64(mask, msb + (msb - 1));
tcg_gen_and_i64(tmp, val, mask);
if (rs) {
@@ -3422,7 +3424,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a)
nullify_over(ctx);
#endif
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i64();
tcg_gen_addi_i64(tmp, load_gpr(ctx, a->b), a->disp);
tmp = do_ibranch_priv(ctx, tmp);
@@ -3519,7 +3521,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a)
static bool trans_blr(DisasContext *ctx, arg_blr *a)
{
if (a->x) {
- TCGv_i64 tmp = tcg_temp_new();
+ TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_shli_i64(tmp, load_gpr(ctx, a->x), 3);
tcg_gen_addi_i64(tmp, tmp, ctx->iaoq_f + 8);
/* The computation here never changes privilege level. */
@@ -3537,7 +3539,7 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a)
if (a->x == 0) {
dest = load_gpr(ctx, a->b);
} else {
- dest = tcg_temp_new();
+ dest = tcg_temp_new_i64();
tcg_gen_shli_i64(dest, load_gpr(ctx, a->x), 3);
tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b));
}
@@ -3874,7 +3876,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest *a)
nullify_over(ctx);
- t = tcg_temp_new();
+ t = tcg_temp_new_i64();
tcg_gen_ld32u_i64(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow));
if (a->y == 1) {
@@ -4176,7 +4178,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
This will be overwritten by a branch. */
if (ctx->iaoq_b == -1) {
ctx->iaoq_n = -1;
- ctx->iaoq_n_var = tcg_temp_new();
+ ctx->iaoq_n_var = tcg_temp_new_i64();
tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4);
} else {
ctx->iaoq_n = ctx->iaoq_b + 4;
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 50/61] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (48 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 49/61] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 51/61] target/hppa: Implement HADD Richard Henderson
` (10 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4a2bfb7757..366a8f1acc 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1325,10 +1325,10 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs,
*pofs = ofs;
*pgva = addr = tcg_temp_new_i64();
- tcg_gen_andi_tl(addr, modify <= 0 ? ofs : base, gva_offset_mask(ctx));
+ tcg_gen_andi_i64(addr, modify <= 0 ? ofs : base, gva_offset_mask(ctx));
#ifndef CONFIG_USER_ONLY
if (!is_phys) {
- tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base));
+ tcg_gen_or_i64(addr, addr, space_select(ctx, sp, base));
}
#endif
}
@@ -2361,7 +2361,7 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
a->data ? offsetof(CPUHPPAState, cr[CR_IOR])
: offsetof(CPUHPPAState, cr[CR_IIAOQ]));
tcg_gen_shli_i64(stl, stl, 32);
- tcg_gen_or_tl(addr, atl, stl);
+ tcg_gen_or_i64(addr, atl, stl);
reg = load_gpr(ctx, a->r);
if (a->addr) {
@@ -2911,7 +2911,7 @@ static bool trans_ldo(DisasContext *ctx, arg_ldo *a)
TCGv_i64 tcg_rt = dest_gpr(ctx, a->t);
/* Special case rb == 0, for the LDI pseudo-op.
- The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */
+ The COPY pseudo-op is handled for free within tcg_gen_addi_i64. */
if (a->b == 0) {
tcg_gen_movi_i64(tcg_rt, a->i);
} else {
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 51/61] target/hppa: Implement HADD
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (49 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 50/61] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 52/61] target/hppa: Implement HSUB Richard Henderson
` (9 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/helper.h | 3 +++
target/hppa/insns.decode | 8 +++++++-
target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++++++
target/hppa/translate.c | 37 +++++++++++++++++++++++++++++++++++++
4 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index 4b2c66316f..ff2695797e 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -14,6 +14,9 @@ DEF_HELPER_FLAGS_3(stdby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tl)
DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl)
+DEF_HELPER_FLAGS_2(hadd_ss, TCG_CALL_NO_RWG, i64, i64, i64)
+DEF_HELPER_FLAGS_2(hadd_us, TCG_CALL_NO_RWG, i64, i64, i64)
+
DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tl, env, tl, i32, i32)
DEF_HELPER_FLAGS_1(loaded_fr0, TCG_CALL_NO_RWG, void, env)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index db1b9f750f..88248ed3e2 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -65,6 +65,7 @@
&ldst t b x disp sp m scale size
&rr_cf_d t r cf d
+&rrr t r1 r2
&rrr_cf t r1 r2 cf
&rrr_cf_d t r1 r2 cf d
&rrr_cf_d_sh t r1 r2 cf d sh
@@ -81,6 +82,7 @@
####
@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d
+@rrr ...... r2:5 r1:5 .... ....... t:5 &rrr
@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d
@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh
@@ -208,6 +210,10 @@ subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf
cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d
+hadd 000010 ..... ..... 00000011 11 0 ..... @rrr
+hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr
+hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr
+
####
# Index Mem
####
@@ -429,7 +435,7 @@ fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32
@f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \
&fclass3 r1=%ra64 r2=%rb64 t=%rt64
-@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5
+@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 &fclass3
# Floating point class 0
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index 0bccca1e11..a230a3a0c3 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -377,3 +377,35 @@ target_ulong HELPER(read_interval_timer)(void)
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 2;
#endif
}
+
+uint64_t HELPER(hadd_ss)(uint64_t r1, uint64_t r2)
+{
+ uint64_t ret = 0;
+
+ for (int i = 0; i < 64; i += 16) {
+ int f1 = sextract64(r1, i, 16);
+ int f2 = sextract64(r2, i, 16);
+ int fr = f1 + f2;
+
+ fr = MIN(fr, INT16_MAX);
+ fr = MAX(fr, INT16_MIN);
+ ret = deposit64(ret, i, 16, fr);
+ }
+ return ret;
+}
+
+uint64_t HELPER(hadd_us)(uint64_t r1, uint64_t r2)
+{
+ uint64_t ret = 0;
+
+ for (int i = 0; i < 64; i += 16) {
+ int f1 = extract64(r1, i, 16);
+ int f2 = sextract64(r2, i, 16);
+ int fr = f1 + f2;
+
+ fr = MIN(fr, UINT16_MAX);
+ fr = MAX(fr, 0);
+ ret = deposit64(ret, i, 16, fr);
+ }
+ return ret;
+}
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 366a8f1acc..bbf216fcde 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -23,6 +23,7 @@
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
#include "exec/translator.h"
@@ -2739,6 +2740,42 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf_d *a)
return nullify_end(ctx);
}
+static bool do_multimedia(DisasContext *ctx, arg_rrr *a,
+ void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64))
+{
+ TCGv_i64 r1, r2, dest;
+
+ if (!ctx->is_pa20) {
+ return false;
+ }
+
+ nullify_over(ctx);
+
+ r1 = load_gpr(ctx, a->r1);
+ r2 = load_gpr(ctx, a->r2);
+ dest = dest_gpr(ctx, a->t);
+
+ fn(dest, r1, r2);
+ save_gpr(ctx, a->t, dest);
+
+ return nullify_end(ctx);
+}
+
+static bool trans_hadd(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, tcg_gen_vec_add16_i64);
+}
+
+static bool trans_hadd_ss(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_helper_hadd_ss);
+}
+
+static bool trans_hadd_us(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_helper_hadd_us);
+}
+
static bool trans_ld(DisasContext *ctx, arg_ldst *a)
{
if (!ctx->is_pa20 && a->size > MO_32) {
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 52/61] target/hppa: Implement HSUB
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (50 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 51/61] target/hppa: Implement HADD Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 53/61] target/hppa: Implement HAVG Richard Henderson
` (8 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/helper.h | 2 ++
target/hppa/insns.decode | 4 ++++
target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++++++
target/hppa/translate.c | 15 +++++++++++++++
4 files changed, 53 insertions(+)
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index ff2695797e..99486f4cf8 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -16,6 +16,8 @@ DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl)
DEF_HELPER_FLAGS_2(hadd_ss, TCG_CALL_NO_RWG, i64, i64, i64)
DEF_HELPER_FLAGS_2(hadd_us, TCG_CALL_NO_RWG, i64, i64, i64)
+DEF_HELPER_FLAGS_2(hsub_ss, TCG_CALL_NO_RWG, i64, i64, i64)
+DEF_HELPER_FLAGS_2(hsub_us, TCG_CALL_NO_RWG, i64, i64, i64)
DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tl, env, tl, i32, i32)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 88248ed3e2..1830b06c76 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -214,6 +214,10 @@ hadd 000010 ..... ..... 00000011 11 0 ..... @rrr
hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr
hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr
+hsub 000010 ..... ..... 00000001 11 0 ..... @rrr
+hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr
+hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr
+
####
# Index Mem
####
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index a230a3a0c3..ece523bea0 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -409,3 +409,35 @@ uint64_t HELPER(hadd_us)(uint64_t r1, uint64_t r2)
}
return ret;
}
+
+uint64_t HELPER(hsub_ss)(uint64_t r1, uint64_t r2)
+{
+ uint64_t ret = 0;
+
+ for (int i = 0; i < 64; i += 16) {
+ int f1 = sextract64(r1, i, 16);
+ int f2 = sextract64(r2, i, 16);
+ int fr = f1 - f2;
+
+ fr = MIN(fr, INT16_MAX);
+ fr = MAX(fr, INT16_MIN);
+ ret = deposit64(ret, i, 16, fr);
+ }
+ return ret;
+}
+
+uint64_t HELPER(hsub_us)(uint64_t r1, uint64_t r2)
+{
+ uint64_t ret = 0;
+
+ for (int i = 0; i < 64; i += 16) {
+ int f1 = extract64(r1, i, 16);
+ int f2 = sextract64(r2, i, 16);
+ int fr = f1 - f2;
+
+ fr = MIN(fr, UINT16_MAX);
+ fr = MAX(fr, 0);
+ ret = deposit64(ret, i, 16, fr);
+ }
+ return ret;
+}
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index bbf216fcde..97d27cb2a9 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2776,6 +2776,21 @@ static bool trans_hadd_us(DisasContext *ctx, arg_rrr *a)
return do_multimedia(ctx, a, gen_helper_hadd_us);
}
+static bool trans_hsub(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64);
+}
+
+static bool trans_hsub_ss(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_helper_hsub_ss);
+}
+
+static bool trans_hsub_us(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_helper_hsub_us);
+}
+
static bool trans_ld(DisasContext *ctx, arg_ldst *a)
{
if (!ctx->is_pa20 && a->size > MO_32) {
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 53/61] target/hppa: Implement HAVG
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (51 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 52/61] target/hppa: Implement HSUB Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 54/61] target/hppa: Implement HSHL, HSHR Richard Henderson
` (7 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/helper.h | 1 +
target/hppa/insns.decode | 2 ++
target/hppa/op_helper.c | 14 ++++++++++++++
target/hppa/translate.c | 5 +++++
4 files changed, 22 insertions(+)
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index 99486f4cf8..1feb2fdfc4 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -16,6 +16,7 @@ DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl)
DEF_HELPER_FLAGS_2(hadd_ss, TCG_CALL_NO_RWG, i64, i64, i64)
DEF_HELPER_FLAGS_2(hadd_us, TCG_CALL_NO_RWG, i64, i64, i64)
+DEF_HELPER_FLAGS_2(havg, TCG_CALL_NO_RWG, i64, i64, i64)
DEF_HELPER_FLAGS_2(hsub_ss, TCG_CALL_NO_RWG, i64, i64, i64)
DEF_HELPER_FLAGS_2(hsub_us, TCG_CALL_NO_RWG, i64, i64, i64)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 1830b06c76..fb0f9d6dbd 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -214,6 +214,8 @@ hadd 000010 ..... ..... 00000011 11 0 ..... @rrr
hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr
hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr
+havg 000010 ..... ..... 00000010 11 0 ..... @rrr
+
hsub 000010 ..... ..... 00000001 11 0 ..... @rrr
hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr
hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index ece523bea0..cba610ac75 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -410,6 +410,20 @@ uint64_t HELPER(hadd_us)(uint64_t r1, uint64_t r2)
return ret;
}
+uint64_t HELPER(havg)(uint64_t r1, uint64_t r2)
+{
+ uint64_t ret = 0;
+
+ for (int i = 0; i < 64; i += 16) {
+ int f1 = extract64(r1, i, 16);
+ int f2 = extract64(r2, i, 16);
+ int fr = f1 + f2;
+
+ ret = deposit64(ret, i, 16, (fr >> 1) | (fr & 1));
+ }
+ return ret;
+}
+
uint64_t HELPER(hsub_ss)(uint64_t r1, uint64_t r2)
{
uint64_t ret = 0;
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 97d27cb2a9..b3335ba595 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2776,6 +2776,11 @@ static bool trans_hadd_us(DisasContext *ctx, arg_rrr *a)
return do_multimedia(ctx, a, gen_helper_hadd_us);
}
+static bool trans_havg(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_helper_havg);
+}
+
static bool trans_hsub(DisasContext *ctx, arg_rrr *a)
{
return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64);
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 54/61] target/hppa: Implement HSHL, HSHR
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (52 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 53/61] target/hppa: Implement HAVG Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 55/61] target/hppa: Implement HSHLADD, HSHRADD Richard Henderson
` (6 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 5 +++++
target/hppa/translate.c | 35 +++++++++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index fb0f9d6dbd..f0c4866ca2 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -69,6 +69,7 @@
&rrr_cf t r1 r2 cf
&rrr_cf_d t r1 r2 cf d
&rrr_cf_d_sh t r1 r2 cf d sh
+&rri t r i
&rri_cf t r i cf
&rri_cf_d t r i cf d
@@ -216,6 +217,10 @@ hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr
havg 000010 ..... ..... 00000010 11 0 ..... @rrr
+hshl 111110 00000 r:5 100010 i:4 0 t:5 &rri
+hshr_s 111110 r:5 00000 110011 i:4 0 t:5 &rri
+hshr_u 111110 r:5 00000 110010 i:4 0 t:5 &rri
+
hsub 000010 ..... ..... 00000001 11 0 ..... @rrr
hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr
hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index b3335ba595..b912673531 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2761,6 +2761,26 @@ static bool do_multimedia(DisasContext *ctx, arg_rrr *a,
return nullify_end(ctx);
}
+static bool do_multimedia_sh(DisasContext *ctx, arg_rri *a,
+ void (*fn)(TCGv_i64, TCGv_i64, int64_t))
+{
+ TCGv_i64 r, dest;
+
+ if (!ctx->is_pa20) {
+ return false;
+ }
+
+ nullify_over(ctx);
+
+ r = load_gpr(ctx, a->r);
+ dest = dest_gpr(ctx, a->t);
+
+ fn(dest, r, a->i);
+ save_gpr(ctx, a->t, dest);
+
+ return nullify_end(ctx);
+}
+
static bool trans_hadd(DisasContext *ctx, arg_rrr *a)
{
return do_multimedia(ctx, a, tcg_gen_vec_add16_i64);
@@ -2781,6 +2801,21 @@ static bool trans_havg(DisasContext *ctx, arg_rrr *a)
return do_multimedia(ctx, a, gen_helper_havg);
}
+static bool trans_hshl(DisasContext *ctx, arg_rri *a)
+{
+ return do_multimedia_sh(ctx, a, tcg_gen_vec_shl16i_i64);
+}
+
+static bool trans_hshr_s(DisasContext *ctx, arg_rri *a)
+{
+ return do_multimedia_sh(ctx, a, tcg_gen_vec_sar16i_i64);
+}
+
+static bool trans_hshr_u(DisasContext *ctx, arg_rri *a)
+{
+ return do_multimedia_sh(ctx, a, tcg_gen_vec_shr16i_i64);
+}
+
static bool trans_hsub(DisasContext *ctx, arg_rrr *a)
{
return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64);
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 55/61] target/hppa: Implement HSHLADD, HSHRADD
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (53 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 54/61] target/hppa: Implement HSHL, HSHR Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 56/61] target/hppa: Implement MIXH, MIXW Richard Henderson
` (5 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/helper.h | 2 ++
target/hppa/insns.decode | 12 ++++++++++--
target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++++++
target/hppa/translate.c | 32 ++++++++++++++++++++++++++++++++
4 files changed, 76 insertions(+), 2 deletions(-)
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index 1feb2fdfc4..c4c3093a83 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -17,6 +17,8 @@ DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl)
DEF_HELPER_FLAGS_2(hadd_ss, TCG_CALL_NO_RWG, i64, i64, i64)
DEF_HELPER_FLAGS_2(hadd_us, TCG_CALL_NO_RWG, i64, i64, i64)
DEF_HELPER_FLAGS_2(havg, TCG_CALL_NO_RWG, i64, i64, i64)
+DEF_HELPER_FLAGS_3(hshladd, TCG_CALL_NO_RWG, i64, i64, i64, i32)
+DEF_HELPER_FLAGS_3(hshradd, TCG_CALL_NO_RWG, i64, i64, i64, i32)
DEF_HELPER_FLAGS_2(hsub_ss, TCG_CALL_NO_RWG, i64, i64, i64)
DEF_HELPER_FLAGS_2(hsub_us, TCG_CALL_NO_RWG, i64, i64, i64)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index f0c4866ca2..d7befbf73d 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -68,6 +68,7 @@
&rrr t r1 r2
&rrr_cf t r1 r2 cf
&rrr_cf_d t r1 r2 cf d
+&rrr_sh t r1 r2 sh
&rrr_cf_d_sh t r1 r2 cf d sh
&rri t r i
&rri_cf t r i cf
@@ -86,6 +87,7 @@
@rrr ...... r2:5 r1:5 .... ....... t:5 &rrr
@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d
+@rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh
@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh
@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0
@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11
@@ -187,14 +189,20 @@ dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d
add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh
add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh
add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh
-add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0
+{
+ add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0
+ hshladd 000010 ..... ..... 0000 0111.. 0 ..... @rrr_sh
+}
add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0
sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d
sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d
sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d
sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d
-sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d
+{
+ sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d
+ hshradd 000010 ..... ..... 0000 0101.. 0 ..... @rrr_sh
+}
sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d
ldil 001000 t:5 ..................... i=%assemble_21
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index cba610ac75..9d8e728460 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -455,3 +455,35 @@ uint64_t HELPER(hsub_us)(uint64_t r1, uint64_t r2)
}
return ret;
}
+
+uint64_t HELPER(hshladd)(uint64_t r1, uint64_t r2, uint32_t sh)
+{
+ uint64_t ret = 0;
+
+ for (int i = 0; i < 64; i += 16) {
+ int f1 = sextract64(r1, i, 16);
+ int f2 = sextract64(r2, i, 16);
+ int fr = (f1 << sh) + f2;
+
+ fr = MIN(fr, INT16_MAX);
+ fr = MAX(fr, INT16_MIN);
+ ret = deposit64(ret, i, 16, fr);
+ }
+ return ret;
+}
+
+uint64_t HELPER(hshradd)(uint64_t r1, uint64_t r2, uint32_t sh)
+{
+ uint64_t ret = 0;
+
+ for (int i = 0; i < 64; i += 16) {
+ int f1 = sextract64(r1, i, 16);
+ int f2 = sextract64(r2, i, 16);
+ int fr = (f1 >> sh) + f2;
+
+ fr = MIN(fr, INT16_MAX);
+ fr = MAX(fr, INT16_MIN);
+ ret = deposit64(ret, i, 16, fr);
+ }
+ return ret;
+}
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index b912673531..b0aefecd2e 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2781,6 +2781,28 @@ static bool do_multimedia_sh(DisasContext *ctx, arg_rri *a,
return nullify_end(ctx);
}
+static bool do_multimedia_shadd(DisasContext *ctx, arg_rrr_sh *a,
+ void (*fn)(TCGv_i64, TCGv_i64,
+ TCGv_i64, TCGv_i32))
+{
+ TCGv_i64 r1, r2, dest;
+
+ if (!ctx->is_pa20) {
+ return false;
+ }
+
+ nullify_over(ctx);
+
+ r1 = load_gpr(ctx, a->r1);
+ r2 = load_gpr(ctx, a->r2);
+ dest = dest_gpr(ctx, a->t);
+
+ fn(dest, r1, r2, tcg_constant_i32(a->sh));
+ save_gpr(ctx, a->t, dest);
+
+ return nullify_end(ctx);
+}
+
static bool trans_hadd(DisasContext *ctx, arg_rrr *a)
{
return do_multimedia(ctx, a, tcg_gen_vec_add16_i64);
@@ -2816,6 +2838,16 @@ static bool trans_hshr_u(DisasContext *ctx, arg_rri *a)
return do_multimedia_sh(ctx, a, tcg_gen_vec_shr16i_i64);
}
+static bool trans_hshladd(DisasContext *ctx, arg_rrr_sh *a)
+{
+ return do_multimedia_shadd(ctx, a, gen_helper_hshladd);
+}
+
+static bool trans_hshradd(DisasContext *ctx, arg_rrr_sh *a)
+{
+ return do_multimedia_shadd(ctx, a, gen_helper_hshradd);
+}
+
static bool trans_hsub(DisasContext *ctx, arg_rrr *a)
{
return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64);
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 56/61] target/hppa: Implement MIXH, MIXW
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (54 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 55/61] target/hppa: Implement HSHLADD, HSHRADD Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 57/61] target/hppa: Implement PERMH Richard Henderson
` (4 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 5 ++++
target/hppa/translate.c | 55 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 60 insertions(+)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index d7befbf73d..323e9275bf 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -233,6 +233,11 @@ hsub 000010 ..... ..... 00000001 11 0 ..... @rrr
hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr
hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr
+mixh_l 111110 ..... ..... 1 00 00100000 ..... @rrr
+mixh_r 111110 ..... ..... 1 10 00100000 ..... @rrr
+mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr
+mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr
+
####
# Index Mem
####
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index b0aefecd2e..bd8a858da6 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2863,6 +2863,61 @@ static bool trans_hsub_us(DisasContext *ctx, arg_rrr *a)
return do_multimedia(ctx, a, gen_helper_hsub_us);
}
+static void gen_mixh_l(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2)
+{
+ uint64_t mask = 0xffff0000ffff0000ull;
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(tmp, r2, mask);
+ tcg_gen_andi_i64(dst, r1, mask);
+ tcg_gen_shri_i64(tmp, tmp, 16);
+ tcg_gen_or_i64(dst, dst, tmp);
+}
+
+static bool trans_mixh_l(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_mixh_l);
+}
+
+static void gen_mixh_r(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2)
+{
+ uint64_t mask = 0x0000ffff0000ffffull;
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(tmp, r1, mask);
+ tcg_gen_andi_i64(dst, r2, mask);
+ tcg_gen_shli_i64(tmp, tmp, 16);
+ tcg_gen_or_i64(dst, dst, tmp);
+}
+
+static bool trans_mixh_r(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_mixh_r);
+}
+
+static void gen_mixw_l(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2)
+{
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ tcg_gen_shri_i64(tmp, r2, 32);
+ tcg_gen_deposit_i64(dst, r1, tmp, 0, 32);
+}
+
+static bool trans_mixw_l(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_mixw_l);
+}
+
+static void gen_mixw_r(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2)
+{
+ tcg_gen_deposit_i64(dst, r2, r1, 32, 32);
+}
+
+static bool trans_mixw_r(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_mixw_r);
+}
+
static bool trans_ld(DisasContext *ctx, arg_ldst *a)
{
if (!ctx->is_pa20 && a->size > MO_32) {
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 57/61] target/hppa: Implement PERMH
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (55 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 56/61] target/hppa: Implement MIXH, MIXW Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 58/61] target/hppa: Fix interruption based on default PSW Richard Henderson
` (3 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 2 ++
target/hppa/translate.c | 29 +++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 323e9275bf..c8f4317576 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -238,6 +238,8 @@ mixh_r 111110 ..... ..... 1 10 00100000 ..... @rrr
mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr
mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr
+permh 111110 r1:5 r2:5 0 c0:2 0 c1:2 c2:2 c3:2 0 t:5
+
####
# Index Mem
####
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index bd8a858da6..40b5a3d8c3 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2918,6 +2918,35 @@ static bool trans_mixw_r(DisasContext *ctx, arg_rrr *a)
return do_multimedia(ctx, a, gen_mixw_r);
}
+static bool trans_permh(DisasContext *ctx, arg_permh *a)
+{
+ TCGv_i64 r, t0, t1, t2, t3;
+
+ if (!ctx->is_pa20) {
+ return false;
+ }
+
+ nullify_over(ctx);
+
+ r = load_gpr(ctx, a->r1);
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ t2 = tcg_temp_new_i64();
+ t3 = tcg_temp_new_i64();
+
+ tcg_gen_extract_i64(t0, r, (3 - a->c0) * 16, 16);
+ tcg_gen_extract_i64(t1, r, (3 - a->c1) * 16, 16);
+ tcg_gen_extract_i64(t2, r, (3 - a->c2) * 16, 16);
+ tcg_gen_extract_i64(t3, r, (3 - a->c3) * 16, 16);
+
+ tcg_gen_deposit_i64(t0, t1, t0, 16, 48);
+ tcg_gen_deposit_i64(t2, t3, t2, 16, 48);
+ tcg_gen_deposit_i64(t0, t2, t0, 32, 32);
+
+ save_gpr(ctx, a->t, t0);
+ return nullify_end(ctx);
+}
+
static bool trans_ld(DisasContext *ctx, arg_ldst *a)
{
if (!ctx->is_pa20 && a->size > MO_32) {
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 58/61] target/hppa: Fix interruption based on default PSW
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (56 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 57/61] target/hppa: Implement PERMH Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 59/61] target/hppa: Precompute zero into DisasContext Richard Henderson
` (2 subsequent siblings)
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
From: Helge Deller <deller@gmx.de>
The default PSW is set by the operating system with the PDC_PSW firmware
call. Use that setting to decide if wide mode is to be enabled for
interruptions and EIRR usage.
Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu.h | 2 ++
target/hppa/int_helper.c | 17 +++++++++++++----
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 5ce05046c0..5c7fddbc2b 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -124,6 +124,8 @@
#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
#define CR_RC 0
+#define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */
+#define PDC_PSW_WIDE_BIT 2
#define CR_PID1 8
#define CR_PID2 9
#define CR_PID3 12
diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c
index f355c4c76b..021f410bef 100644
--- a/target/hppa/int_helper.c
+++ b/target/hppa/int_helper.c
@@ -52,9 +52,16 @@ static void io_eir_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
HPPACPU *cpu = opaque;
- int le_bit = ~data & 31;
+ int widthm1 = 31;
+ int le_bit;
- cpu->env.cr[CR_EIRR] |= (target_ulong)1 << le_bit;
+ /* The default PSW.W controls the width of EIRR. */
+ if (cpu->is_pa20 && cpu->env.cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT) {
+ widthm1 = 63;
+ }
+ le_bit = ~data & widthm1;
+
+ cpu->env.cr[CR_EIRR] |= 1ull << le_bit;
eval_interrupt(cpu);
}
@@ -104,8 +111,10 @@ void hppa_cpu_do_interrupt(CPUState *cs)
/* step 1 */
env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env);
- /* step 2 -- note PSW_W == 0 for !HPPA64. */
- cpu_hppa_put_psw(env, PSW_W | (i == EXCP_HPMC ? PSW_M : 0));
+ /* step 2 -- Note PSW_W is masked out again for pa1.x */
+ cpu_hppa_put_psw(env,
+ (env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT ? PSW_W : 0) |
+ (i == EXCP_HPMC ? PSW_M : 0));
/* step 3 */
env->cr[CR_IIASQ] = iasq_f >> 32;
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 59/61] target/hppa: Precompute zero into DisasContext
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (57 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 58/61] target/hppa: Fix interruption based on default PSW Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 60/61] target/hppa: Return zero for r0 from load_gpr Richard Henderson
2023-10-18 21:51 ` [PATCH 61/61] target/hppa: Simplify trans_dep*_imm Richard Henderson
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Reduce the number of times we look for the constant 0.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 34 ++++++++++++++++++----------------
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 40b5a3d8c3..9a9876c529 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -53,6 +53,8 @@ typedef struct DisasContext {
DisasCond null_cond;
TCGLabel *null_lab;
+ TCGv_i64 zero;
+
uint32_t insn;
uint32_t tb_flags;
int mmu_idx;
@@ -1004,14 +1006,13 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
}
if (!is_l || cond_need_cb(c)) {
- TCGv_i64 zero = tcg_constant_i64(0);
cb_msb = tcg_temp_new_i64();
cb = tcg_temp_new_i64();
- tcg_gen_add2_i64(dest, cb_msb, in1, zero, in2, zero);
+ tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero);
if (is_c) {
tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb,
- get_psw_carry(ctx, d), zero);
+ get_psw_carry(ctx, d), ctx->zero);
}
tcg_gen_xor_i64(cb, in1, in2);
tcg_gen_xor_i64(cb, cb, dest);
@@ -1089,7 +1090,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
TCGv_i64 in2, bool is_tsv, bool is_b,
bool is_tc, unsigned cf, bool d)
{
- TCGv_i64 dest, sv, cb, cb_msb, zero, tmp;
+ TCGv_i64 dest, sv, cb, cb_msb, tmp;
unsigned c = cf >> 1;
DisasCond cond;
@@ -1097,12 +1098,12 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
cb = tcg_temp_new_i64();
cb_msb = tcg_temp_new_i64();
- zero = tcg_constant_i64(0);
if (is_b) {
/* DEST,C = IN1 + ~IN2 + C. */
tcg_gen_not_i64(cb, in2);
- tcg_gen_add2_i64(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), zero);
- tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, cb, zero);
+ tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero,
+ get_psw_carry(ctx, d), ctx->zero);
+ tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, cb, ctx->zero);
tcg_gen_xor_i64(cb, cb, in1);
tcg_gen_xor_i64(cb, cb, dest);
} else {
@@ -1111,7 +1112,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
* operations by seeding the high word with 1 and subtracting.
*/
TCGv_i64 one = tcg_constant_i64(1);
- tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, zero);
+ tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, ctx->zero);
tcg_gen_eqv_i64(cb, in1, in2);
tcg_gen_xor_i64(cb, cb, dest);
}
@@ -2430,7 +2431,7 @@ static bool trans_lci(DisasContext *ctx, arg_lci *a)
physical address. Two addresses with the same CI have a coherent
view of the cache. Our implementation is to return 0 for all,
since the entire address space is coherent. */
- save_gpr(ctx, a->t, tcg_constant_i64(0));
+ save_gpr(ctx, a->t, ctx->zero);
cond_free(&ctx->null_cond);
return true;
@@ -2639,7 +2640,7 @@ static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf_d *a)
static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
{
- TCGv_i64 dest, add1, add2, addc, zero, in1, in2;
+ TCGv_i64 dest, add1, add2, addc, in1, in2;
TCGv_i64 cout;
nullify_over(ctx);
@@ -2651,7 +2652,6 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
add2 = tcg_temp_new_i64();
addc = tcg_temp_new_i64();
dest = tcg_temp_new_i64();
- zero = tcg_constant_i64(0);
/* Form R1 << 1 | PSW[CB]{8}. */
tcg_gen_add_i64(add1, in1, in1);
@@ -2667,8 +2667,9 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
tcg_gen_xor_i64(add2, in2, addc);
tcg_gen_andi_i64(addc, addc, 1);
- tcg_gen_add2_i64(dest, cpu_psw_cb_msb, add1, zero, add2, zero);
- tcg_gen_add2_i64(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero);
+ tcg_gen_add2_i64(dest, cpu_psw_cb_msb, add1, ctx->zero, add2, ctx->zero);
+ tcg_gen_add2_i64(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb,
+ addc, ctx->zero);
/* Write back the result register. */
save_gpr(ctx, a->t, dest);
@@ -2968,7 +2969,7 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a)
static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
{
MemOp mop = MO_TE | MO_ALIGN | a->size;
- TCGv_i64 zero, dest, ofs;
+ TCGv_i64 dest, ofs;
TCGv_i64 addr;
if (!ctx->is_pa20 && a->size > MO_32) {
@@ -2998,8 +2999,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
*/
gen_helper_ldc_check(addr);
- zero = tcg_constant_i64(0);
- tcg_gen_atomic_xchg_i64(dest, addr, zero, ctx->mmu_idx, mop);
+ tcg_gen_atomic_xchg_i64(dest, addr, ctx->zero, ctx->mmu_idx, mop);
if (a->m) {
save_gpr(ctx, a->b, ofs);
@@ -4337,6 +4337,8 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->iaoq_n = -1;
ctx->iaoq_n_var = NULL;
+ ctx->zero = tcg_constant_i64(0);
+
/* Bound the number of instructions by those left on the page. */
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 60/61] target/hppa: Return zero for r0 from load_gpr
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (58 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 59/61] target/hppa: Precompute zero into DisasContext Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
2023-10-18 21:51 ` [PATCH 61/61] target/hppa: Simplify trans_dep*_imm Richard Henderson
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 9a9876c529..a9e0e1706f 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -307,9 +307,7 @@ static void cond_free(DisasCond *cond)
static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg)
{
if (reg == 0) {
- TCGv_i64 t = tcg_temp_new_i64();
- tcg_gen_movi_i64(t, 0);
- return t;
+ return ctx->zero;
} else {
return cpu_gr[reg];
}
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread* [PATCH 61/61] target/hppa: Simplify trans_dep*_imm
2023-10-18 21:50 [PATCH 00/61] target/hppa: Implement hppa64-cpu Richard Henderson
` (59 preceding siblings ...)
2023-10-18 21:51 ` [PATCH 60/61] target/hppa: Return zero for r0 from load_gpr Richard Henderson
@ 2023-10-18 21:51 ` Richard Henderson
60 siblings, 0 replies; 67+ messages in thread
From: Richard Henderson @ 2023-10-18 21:51 UTC (permalink / raw)
To: qemu-devel; +Cc: deller
All of the special cases here are now handled during
generic expansion.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 80 +++++++++++++----------------------------
1 file changed, 25 insertions(+), 55 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index a9e0e1706f..e8ce41b5a7 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3473,80 +3473,50 @@ static bool trans_extr_imm(DisasContext *ctx, arg_extr_imm *a)
return nullify_end(ctx);
}
-static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a)
+static bool do_dep_imm(DisasContext *ctx, unsigned rt, unsigned c,
+ bool d, unsigned len, unsigned cpos,
+ TCGv_i64 src, TCGv_i64 val)
{
- unsigned len, width;
- uint64_t mask0, mask1;
+ unsigned width = d ? 64 : 32;
TCGv_i64 dest;
- if (!ctx->is_pa20 && a->d) {
- return false;
+ if (cpos + len > width) {
+ len = width - cpos;
}
- if (a->c) {
+
+ if (c) {
nullify_over(ctx);
}
- len = a->len;
- width = a->d ? 64 : 32;
- if (a->cpos + len > width) {
- len = width - a->cpos;
- }
+ dest = dest_gpr(ctx, rt);
+ tcg_gen_deposit_i64(dest, src, val, cpos, len);
+ save_gpr(ctx, rt, dest);
- dest = dest_gpr(ctx, a->t);
- mask0 = deposit64(0, a->cpos, len, a->i);
- mask1 = deposit64(-1, a->cpos, len, a->i);
-
- if (a->nz) {
- TCGv_i64 src = load_gpr(ctx, a->t);
- tcg_gen_andi_i64(dest, src, mask1);
- tcg_gen_ori_i64(dest, dest, mask0);
- } else {
- tcg_gen_movi_i64(dest, mask0);
- }
- save_gpr(ctx, a->t, dest);
-
- /* Install the new nullification. */
cond_free(&ctx->null_cond);
- if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest);
+ if (c) {
+ ctx->null_cond = do_sed_cond(ctx, c, d, dest);
}
return nullify_end(ctx);
}
-static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a)
+static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a)
{
- unsigned rs = a->nz ? a->t : 0;
- unsigned len, width;
- TCGv_i64 dest, val;
-
if (!ctx->is_pa20 && a->d) {
return false;
}
- if (a->c) {
- nullify_over(ctx);
- }
+ return do_dep_imm(ctx, a->t, a->c, a->d, a->len, a->cpos,
+ a->nz ? load_gpr(ctx, a->t) : ctx->zero,
+ tcg_constant_i64(a->i));
+}
- len = a->len;
- width = a->d ? 64 : 32;
- if (a->cpos + len > width) {
- len = width - a->cpos;
+static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a)
+{
+ if (!ctx->is_pa20 && a->d) {
+ return false;
}
-
- dest = dest_gpr(ctx, a->t);
- val = load_gpr(ctx, a->r);
- if (rs == 0) {
- tcg_gen_deposit_z_i64(dest, val, a->cpos, len);
- } else {
- tcg_gen_deposit_i64(dest, cpu_gr[rs], val, a->cpos, len);
- }
- save_gpr(ctx, a->t, dest);
-
- /* Install the new nullification. */
- cond_free(&ctx->null_cond);
- if (a->c) {
- ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest);
- }
- return nullify_end(ctx);
+ return do_dep_imm(ctx, a->t, a->c, a->d, a->len, a->cpos,
+ a->nz ? load_gpr(ctx, a->t) : ctx->zero,
+ load_gpr(ctx, a->r));
}
static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c,
--
2.34.1
^ permalink raw reply related [flat|nested] 67+ messages in thread