* [PATCH 00/19] cpus: Step toward removing global 'first_cpu'
@ 2023-10-20 16:36 Philippe Mathieu-Daudé
2023-10-20 16:36 ` [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type Philippe Mathieu-Daudé
` (19 more replies)
0 siblings, 20 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé
Heterogeneous machines have different type of CPU.
In that context, both 'first_cpu' and qemu_get_cpu(index)
don't make much sense.
This series first add a 'filter CPU type' argument to
qemu_get_cpu(), so the behavior respects what we currently
expect, then replace 'first_cpu' by a qemu_get_cpu(0) call.
Testing pass, but I'm still unsure about performance impact.
With this series applied, what is left is:
[OK]
- hw/core/generic-loader.c:127: s->cpu = qemu_get_cpu(s->cpu_num, NULL);
- linux-user/syscall.c:8990: if (CPU_NEXT(first_cpu)) {
- monitor/hmp-cmds-target.c:106: cs = vcpu >= 0 ? qemu_get_cpu(vcpu, NULL) : mon_get_cpu(mon);
- stats/stats-hmp-cmds.c:150: CPUState *cpu = qemu_get_cpu(cpu_index, NULL);
- system/cpus.c:754: cpu = qemu_get_cpu(cpu_index, NULL);
[likely OK, we don't support heterogeneous accelerators]
- accel/kvm/kvm-all.c:3581: kvm_arch_on_sigbus_vcpu(first_cpu, code, addr);
- accel/kvm/kvm-all.c:4255: if (first_cpu) {
- accel/kvm/kvm-all.c:4258: query_stats_schema_vcpu(first_cpu, &stats_args);
[need some toughts...]
- accel/tcg/tcg-accel-ops-rr.c:114: qemu_cond_wait_iothread(first_cpu->halt_cond);
- accel/tcg/tcg-accel-ops-rr.c:200: while (first_cpu->stopped) {
- accel/tcg/tcg-accel-ops-rr.c:201: qemu_cond_wait_iothread(first_cpu->halt_cond);
- accel/tcg/tcg-accel-ops-rr.c:212: cpu = first_cpu;
- accel/tcg/tcg-accel-ops-rr.c:242: cpu = first_cpu;
- accel/tcg/tcg-accel-ops-rr.c:336: cpu->thread_id = first_cpu->thread_id;
- accel/tcg/tcg-accel-ops-rr.c:92: if (!rr_kick_vcpu_timer && CPU_NEXT(first_cpu)) {
- dump/win_dump.c:115: if (cpu_memory_rw_debug(first_cpu,
- dump/win_dump.c:128: if (cpu_read_ptr(x64, first_cpu,
- dump/win_dump.c:135: if (cpu_memory_rw_debug(first_cpu, KiBugcheckData,
- dump/win_dump.c:210: if (cpu_memory_rw_debug(first_cpu,
- dump/win_dump.c:258: if (cpu_read_ptr(x64, first_cpu,
- dump/win_dump.c:265: if (cpu_memory_rw_debug(first_cpu,
- dump/win_dump.c:286: if (cpu_read_ptr(x64, first_cpu,
- dump/win_dump.c:294: if (cpu_read_ptr(x64, first_cpu,
- dump/win_dump.c:378: if (cpu_memory_rw_debug(first_cpu, Context,
- dump/win_dump.c:384: if (cpu_memory_rw_debug(first_cpu, Context,
- dump/win_dump.c:400: if (cpu_memory_rw_debug(first_cpu, saved_ctx[i].addr,
- dump/win_dump.c:410: X86CPU *first_x86_cpu = X86_CPU(first_cpu);
- gdbstub/gdbstub.c:1521: cc = CPU_GET_CLASS(first_cpu);
- gdbstub/gdbstub.c:298: CPUState *cpu = first_cpu;
- gdbstub/system.c:338: if (!first_cpu) {
- hw/acpi/cpu.c:138: if (!cdev->cpu || cdev->cpu == first_cpu) {
- hw/acpi/cpu.c:150: if (!cdev->cpu || cdev->cpu == first_cpu) {
- hw/acpi/cpu.c:671: if (CPU(arch_ids->cpus[i].cpu) != first_cpu) {
- hw/core/generic-loader.c:134: s->cpu = first_cpu;
- monitor/hmp-cmds-target.c:39: cpu = qemu_get_cpu(cpu_index, NULL);
- monitor/hmp-cmds-target.c:62: if (!first_cpu) {
- monitor/hmp-cmds-target.c:65: monitor_set_cpu(mon, first_cpu->cpu_index);
- monitor/hmp-cmds-target.c:66: cpu = first_cpu;
- replay/replay-events.c:130: qemu_cpu_kick(first_cpu);
- system/cpu-timers.c:254: } else if (first_cpu) {
- system/cpu-timers.c:263: async_run_on_cpu(first_cpu, do_nothing, RUN_ON_CPU_NULL);
- system/memory_mapping.c:315: first_paging_enabled_cpu = find_paging_enabled_cpu(first_cpu);
- system/qtest.c:548: address_space_write(first_cpu->as, ...
- system/qtest.c:553: address_space_write(first_cpu->as, ...
- system/qtest.c:558: address_space_write(first_cpu->as, ...
- system/qtest.c:563: address_space_write(first_cpu->as, ...
- system/qtest.c:582: address_space_read(first_cpu->as, ...
- system/qtest.c:587: address_space_read(first_cpu->as, ...
- system/qtest.c:592: address_space_read(first_cpu->as, ...
- system/qtest.c:596: address_space_read(first_cpu->as, ...
- system/qtest.c:617: address_space_read(first_cpu->as, ...
- system/qtest.c:643: address_space_read(first_cpu->as, ...
- system/qtest.c:678: address_space_write(first_cpu->as, ...
- system/qtest.c:701: address_space_write(first_cpu->as, ...
- system/qtest.c:735: address_space_write(first_cpu->as, ...
- tests/qtest/fuzz/generic_fuzz.c:241: mr1 = address_space_translate(first_cpu->as,
- tests/qtest/fuzz/qtest_wrappers.c:110: address_space_read(first_cpu->as, ...
- tests/qtest/fuzz/qtest_wrappers.c:122: address_space_read(first_cpu->as, ...
- tests/qtest/fuzz/qtest_wrappers.c:134: address_space_read(first_cpu->as, ...
- tests/qtest/fuzz/qtest_wrappers.c:146: address_space_read(first_cpu->as, ...
- tests/qtest/fuzz/qtest_wrappers.c:157: address_space_write(first_cpu->as, ...
- tests/qtest/fuzz/qtest_wrappers.c:167: address_space_write(first_cpu->as, ...
- tests/qtest/fuzz/qtest_wrappers.c:177: address_space_write(first_cpu->as, ...
- tests/qtest/fuzz/qtest_wrappers.c:187: address_space_write(first_cpu->as, ...
- tests/qtest/fuzz/qtest_wrappers.c:197: address_space_read(first_cpu->as, ...
- tests/qtest/fuzz/qtest_wrappers.c:207: address_space_read(first_cpu->as, ...
- tests/qtest/fuzz/qtest_wrappers.c:218: address_space_write(first_cpu->as, ...
- tests/qtest/fuzz/qtest_wrappers.c:229: address_space_write(first_cpu->as, ...
- tests/qtest/fuzz/qtest_wrappers.c:242: address_space_write(first_cpu->as, ...
Regards,
Phil.
Based-on: <20231013140116.255-1-philmd@linaro.org>
"target: Make 'cpu-qom.h' really target agnostic" v2
Philippe Mathieu-Daudé (19):
cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type
cpus: Filter for target specific CPU (generic)
cpus: Filter for target specific CPU (arm)
cpus: Filter for target specific CPU (loongarch)
cpus: Filter for target specific CPU (mips)
cpus: Filter for target specific CPU (s390x)
cpus: Filter for target specific CPU (riscv)
cpus: Filter for target specific CPU (ppc)
cpus: Filter for target specific CPU (x86)
cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_ARM_CPU)
cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_POWERPC_CPU)
cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_MIPS_CPU)
cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_M68K_CPU)
cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_S390X_CPU)
cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RISCV_CPU)
cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_TRICORE_CPU)
cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_SUPERH_CPU)
cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RX_CPU)
cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_X86_CPU)
include/hw/core/cpu.h | 3 ++-
target/mips/internal.h | 2 +-
cpu-common.c | 5 ++++-
hw/arm/aspeed.c | 5 +++--
hw/arm/bananapi_m2u.c | 3 ++-
hw/arm/boot.c | 14 +++++++-------
hw/arm/exynos4_boards.c | 6 ++++--
hw/arm/fsl-imx7.c | 2 +-
hw/arm/highbank.c | 3 ++-
hw/arm/microbit.c | 3 ++-
hw/arm/mps2-tz.c | 3 ++-
hw/arm/mps2.c | 3 ++-
hw/arm/msf2-som.c | 3 ++-
hw/arm/musca.c | 3 ++-
hw/arm/netduino2.c | 3 ++-
hw/arm/netduinoplus2.c | 2 +-
hw/arm/olimex-stm32-h405.c | 2 +-
hw/arm/orangepi.c | 3 ++-
hw/arm/pxa2xx_gpio.c | 2 +-
hw/arm/realview.c | 5 +++--
hw/arm/sbsa-ref.c | 7 ++++---
hw/arm/stellaris.c | 3 ++-
hw/arm/stm32vldiscovery.c | 2 +-
hw/arm/vexpress.c | 5 +++--
hw/arm/virt-acpi-build.c | 2 +-
hw/arm/virt.c | 25 ++++++++++++++-----------
hw/arm/xilinx_zynq.c | 3 ++-
hw/arm/xlnx-versal-virt.c | 2 +-
hw/core/generic-loader.c | 2 +-
hw/cpu/a15mpcore.c | 4 ++--
hw/cpu/a9mpcore.c | 2 +-
hw/hyperv/hyperv.c | 2 +-
hw/i386/kvm/clock.c | 4 ++--
hw/i386/kvm/xen_evtchn.c | 8 ++++----
hw/i386/kvmvapic.c | 3 ++-
hw/i386/microvm.c | 2 +-
hw/i386/pc.c | 7 ++++---
hw/i386/pc_piix.c | 3 ++-
hw/i386/x86.c | 2 +-
hw/intc/arm_gicv3_common.c | 3 ++-
hw/intc/arm_gicv3_cpuif.c | 2 +-
hw/intc/arm_gicv3_kvm.c | 2 +-
hw/intc/m68k_irqc.c | 2 +-
hw/intc/mips_gic.c | 2 +-
hw/intc/riscv_aclint.c | 2 +-
hw/intc/sh_intc.c | 6 ++++--
hw/intc/sifive_plic.c | 4 ++--
hw/isa/lpc_ich9.c | 2 +-
hw/loongarch/virt.c | 10 +++++-----
hw/m68k/mcf5206.c | 2 +-
hw/mips/bootloader.c | 3 ++-
hw/mips/cps.c | 5 +++--
hw/mips/loongson3_bootp.c | 2 +-
hw/mips/loongson3_virt.c | 7 ++++---
hw/mips/malta.c | 2 +-
hw/misc/mips_cpc.c | 4 ++--
hw/ppc/e500.c | 4 ++--
hw/ppc/ppc.c | 4 ++--
hw/ppc/ppce500_spin.c | 2 +-
hw/ppc/prep_systemio.c | 2 +-
hw/ppc/spapr.c | 11 ++++++-----
hw/ppc/spapr_caps.c | 10 +++++-----
hw/ppc/spapr_rtas.c | 2 +-
hw/ppc/spapr_vof.c | 2 +-
hw/ppc/vof.c | 3 ++-
hw/riscv/boot.c | 4 ++--
hw/riscv/opentitan.c | 4 ++--
hw/rx/rx-gdbsim.c | 4 ++--
hw/s390x/ipl.c | 4 ++--
hw/s390x/s390-virtio-ccw.c | 2 +-
hw/tricore/triboard.c | 2 +-
monitor/hmp-cmds-target.c | 4 ++--
stats/stats-hmp-cmds.c | 2 +-
system/cpus.c | 2 +-
target/arm/arch_dump.c | 6 +++---
target/i386/arch_dump.c | 6 +++---
target/i386/kvm/kvm.c | 6 +++---
target/i386/kvm/xen-emu.c | 15 ++++++++-------
target/i386/monitor.c | 2 +-
target/i386/tcg/sysemu/fpu_helper.c | 4 ++--
target/mips/cpu.c | 2 +-
target/mips/tcg/sysemu/cp0_helper.c | 10 +++++-----
target/mips/tcg/sysemu/tlb_helper.c | 2 +-
target/ppc/arch_dump.c | 4 ++--
target/riscv/arch_dump.c | 4 ++--
target/s390x/cpu_models.c | 10 +++++-----
86 files changed, 199 insertions(+), 163 deletions(-)
--
2.41.0
^ permalink raw reply [flat|nested] 27+ messages in thread
* [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 17:14 ` Peter Maydell
` (2 more replies)
2023-10-20 16:36 ` [PATCH 02/19] cpus: Filter for target specific CPU (generic) Philippe Mathieu-Daudé
` (18 subsequent siblings)
19 siblings, 3 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Andrey Smirnov, Radoslaw Biernacki, Leif Lindholm,
Marcin Juszkiewicz, Shannon Zhao, Igor Mammedov, Ani Sinha,
Alistair Francis, David Woodhouse, Paul Durrant, Marcel Apfelbaum,
Palmer Dabbelt, Bin Meng, Weiwei Li, Daniel Henrique Barboza,
Liu Zhiwei, Song Gao, Thomas Huth, Christian Borntraeger,
Halil Pasic, Eric Farman, David Hildenbrand, Ilya Leoshkevich,
Yanan Wang, Dr. David Alan Gilbert, Marcelo Tosatti,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo, kvm
Heterogeneous machines have different type of CPU.
qemu_get_cpu() returning unfiltered CPUs doesn't make
sense anymore. Add a 'type' argument to filter CPU by
QOM type.
Type in "hw/core/cpu.h" and implementation in cpu-common.c
modified manually, then convert all call sites by passing
a NULL argument using the following coccinelle script:
@@
expression index;
@@
- qemu_get_cpu(index)
+ qemu_get_cpu(index, NULL)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
RFC: Is this hot path code? What is the cost of this QOM cast check?
---
include/hw/core/cpu.h | 3 ++-
cpu-common.c | 5 ++++-
hw/arm/boot.c | 2 +-
hw/arm/fsl-imx7.c | 2 +-
hw/arm/pxa2xx_gpio.c | 2 +-
hw/arm/sbsa-ref.c | 4 ++--
hw/arm/vexpress.c | 2 +-
hw/arm/virt-acpi-build.c | 2 +-
hw/arm/virt.c | 8 ++++----
hw/arm/xlnx-versal-virt.c | 2 +-
hw/core/generic-loader.c | 2 +-
hw/cpu/a15mpcore.c | 4 ++--
hw/cpu/a9mpcore.c | 2 +-
hw/hyperv/hyperv.c | 2 +-
hw/i386/kvm/xen_evtchn.c | 8 ++++----
hw/intc/arm_gicv3_common.c | 2 +-
hw/intc/arm_gicv3_cpuif.c | 2 +-
hw/intc/arm_gicv3_kvm.c | 2 +-
hw/intc/riscv_aclint.c | 2 +-
hw/intc/sifive_plic.c | 4 ++--
hw/loongarch/virt.c | 10 +++++-----
hw/m68k/mcf5206.c | 2 +-
hw/ppc/e500.c | 2 +-
hw/ppc/ppce500_spin.c | 2 +-
hw/riscv/boot.c | 2 +-
hw/riscv/opentitan.c | 4 ++--
hw/s390x/ipl.c | 2 +-
hw/s390x/s390-virtio-ccw.c | 2 +-
monitor/hmp-cmds-target.c | 4 ++--
stats/stats-hmp-cmds.c | 2 +-
system/cpus.c | 2 +-
target/i386/kvm/xen-emu.c | 15 ++++++++-------
target/i386/monitor.c | 2 +-
target/mips/cpu.c | 2 +-
target/mips/tcg/sysemu/cp0_helper.c | 2 +-
target/s390x/cpu_models.c | 10 +++++-----
36 files changed, 66 insertions(+), 61 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 12205b7882..2a6008dd96 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -903,12 +903,13 @@ static inline bool cpu_in_exclusive_context(const CPUState *cpu)
/**
* qemu_get_cpu:
* @index: The CPUState@cpu_index value of the CPU to obtain.
+ * @type: The QOM type to filter for, including its derivatives.
*
* Gets a CPU matching @index.
*
* Returns: The CPU or %NULL if there is no matching CPU.
*/
-CPUState *qemu_get_cpu(int index);
+CPUState *qemu_get_cpu(int index, const char *type);
/**
* cpu_exists:
diff --git a/cpu-common.c b/cpu-common.c
index c81fd72d16..e0d7f7e7e7 100644
--- a/cpu-common.c
+++ b/cpu-common.c
@@ -107,11 +107,14 @@ void cpu_list_remove(CPUState *cpu)
cpu_list_generation_id++;
}
-CPUState *qemu_get_cpu(int index)
+CPUState *qemu_get_cpu(int index, const char *type)
{
CPUState *cpu;
CPU_FOREACH(cpu) {
+ if (type && !object_dynamic_cast(OBJECT(cpu), type)) {
+ continue;
+ }
if (cpu->cpu_index == index) {
return cpu;
}
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 24fa169060..e260168cf5 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -438,7 +438,7 @@ static void fdt_add_psci_node(void *fdt)
uint32_t cpu_off_fn;
uint32_t cpu_on_fn;
uint32_t migrate_fn;
- ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0, NULL));
const char *psci_method;
int64_t psci_conduit;
int rc;
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index 474cfdc87c..1c1585f3e1 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -212,7 +212,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
for (i = 0; i < smp_cpus; i++) {
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
- DeviceState *d = DEVICE(qemu_get_cpu(i));
+ DeviceState *d = DEVICE(qemu_get_cpu(i, NULL));
irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
sysbus_connect_irq(sbd, i, irq);
diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c
index e7c3d99224..0a698171ab 100644
--- a/hw/arm/pxa2xx_gpio.c
+++ b/hw/arm/pxa2xx_gpio.c
@@ -303,7 +303,7 @@ static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
{
PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
- s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
+ s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu, NULL));
qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
qdev_init_gpio_out(dev, s->handler, s->lines);
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 3c7dfcd6dc..3571d5038f 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -275,7 +275,7 @@ static void create_fdt(SBSAMachineState *sms)
for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
- ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu, NULL));
CPUState *cs = CPU(armcpu);
uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu);
@@ -478,7 +478,7 @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
* and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
*/
for (i = 0; i < smp_cpus; i++) {
- DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
+ DeviceState *cpudev = DEVICE(qemu_get_cpu(i, NULL));
int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
int irq;
/*
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 8ff37f52ca..0590332fe5 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -257,7 +257,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type,
/* Connect the CPUs to the GIC */
for (n = 0; n < smp_cpus; n++) {
- DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
+ DeviceState *cpudev = DEVICE(qemu_get_cpu(n, NULL));
sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
sysbus_connect_irq(busdev, n + smp_cpus,
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 6b674231c2..fd6c239c31 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -727,7 +727,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
build_append_int_noprefix(table_data, 0, 3); /* Reserved */
for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
- ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i, NULL));
uint64_t physical_base_address = 0, gich = 0, gicv = 0;
uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0;
uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 15e74249f9..a8f9d88519 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -355,7 +355,7 @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
qemu_fdt_add_subnode(ms->fdt, "/timer");
- armcpu = ARM_CPU(qemu_get_cpu(0));
+ armcpu = ARM_CPU(qemu_get_cpu(0, NULL));
if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
@@ -394,7 +394,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
* at least one of them has Aff3 populated, we set #address-cells to 2.
*/
for (cpu = 0; cpu < smp_cpus; cpu++) {
- ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu, NULL));
if (armcpu->mp_affinity & ARM_AFF3_MASK) {
addr_cells = 2;
@@ -408,7 +408,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
- ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu, NULL));
CPUState *cs = CPU(armcpu);
qemu_fdt_add_subnode(ms->fdt, nodename);
@@ -799,7 +799,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
* and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
*/
for (i = 0; i < smp_cpus; i++) {
- DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
+ DeviceState *cpudev = DEVICE(qemu_get_cpu(i, NULL));
int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
/* Mapping from the output timer irq lines from the CPU to the
* GIC PPI inputs we use for the virt board.
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 88c561ff63..419ee3b882 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -103,7 +103,7 @@ static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit)
for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) {
char *name = g_strdup_printf("/cpus/cpu@%d", i);
- ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i, NULL));
qemu_fdt_add_subnode(s->fdt, name);
qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity);
diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
index d4b5c501d8..98830ebd5b 100644
--- a/hw/core/generic-loader.c
+++ b/hw/core/generic-loader.c
@@ -124,7 +124,7 @@ static void generic_loader_realize(DeviceState *dev, Error **errp)
qemu_register_reset(generic_loader_reset, dev);
if (s->cpu_num != CPU_NONE) {
- s->cpu = qemu_get_cpu(s->cpu_num);
+ s->cpu = qemu_get_cpu(s->cpu_num, NULL);
if (!s->cpu) {
error_setg(errp, "Specified boot CPU#%d is nonexistent",
s->cpu_num);
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index bfd8aa5644..8c9098d5d3 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -65,7 +65,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
/* Make the GIC's TZ support match the CPUs. We assume that
* either all the CPUs have TZ, or none do.
*/
- cpuobj = OBJECT(qemu_get_cpu(0));
+ cpuobj = OBJECT(qemu_get_cpu(0, NULL));
has_el3 = object_property_find(cpuobj, "has_el3") &&
object_property_get_bool(cpuobj, "has_el3", &error_abort);
qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
@@ -90,7 +90,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
* appropriate GIC PPI inputs
*/
for (i = 0; i < s->num_cpu; i++) {
- DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
+ DeviceState *cpudev = DEVICE(qemu_get_cpu(i, NULL));
int ppibase = s->num_irq - 32 + i * 32;
int irq;
/* Mapping from the output timer irq lines from the CPU to the
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index d03f57e579..62b7fb3836 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -56,7 +56,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
CPUState *cpu0;
Object *cpuobj;
- cpu0 = qemu_get_cpu(0);
+ cpu0 = qemu_get_cpu(0, NULL);
cpuobj = OBJECT(cpu0);
if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) {
/* We might allow Cortex-A5 once we model it */
diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c
index 57b402b956..a43f29ad8d 100644
--- a/hw/hyperv/hyperv.c
+++ b/hw/hyperv/hyperv.c
@@ -226,7 +226,7 @@ struct HvSintRoute {
static CPUState *hyperv_find_vcpu(uint32_t vp_index)
{
- CPUState *cs = qemu_get_cpu(vp_index);
+ CPUState *cs = qemu_get_cpu(vp_index, NULL);
assert(hyperv_vp_index(cs) == vp_index);
return cs;
}
diff --git a/hw/i386/kvm/xen_evtchn.c b/hw/i386/kvm/xen_evtchn.c
index a731738411..de3650ba3b 100644
--- a/hw/i386/kvm/xen_evtchn.c
+++ b/hw/i386/kvm/xen_evtchn.c
@@ -542,7 +542,7 @@ static void deassign_kernel_port(evtchn_port_t port)
static int assign_kernel_port(uint16_t type, evtchn_port_t port,
uint32_t vcpu_id)
{
- CPUState *cpu = qemu_get_cpu(vcpu_id);
+ CPUState *cpu = qemu_get_cpu(vcpu_id, NULL);
struct kvm_xen_hvm_attr ha;
if (!cpu) {
@@ -589,7 +589,7 @@ static bool valid_port(evtchn_port_t port)
static bool valid_vcpu(uint32_t vcpu)
{
- return !!qemu_get_cpu(vcpu);
+ return !!qemu_get_cpu(vcpu, NULL);
}
static void unbind_backend_ports(XenEvtchnState *s)
@@ -917,7 +917,7 @@ static int set_port_pending(XenEvtchnState *s, evtchn_port_t port)
if (s->evtchn_in_kernel) {
XenEvtchnPort *p = &s->port_table[port];
- CPUState *cpu = qemu_get_cpu(p->vcpu);
+ CPUState *cpu = qemu_get_cpu(p->vcpu, NULL);
struct kvm_irq_routing_xen_evtchn evt;
if (!cpu) {
@@ -1779,7 +1779,7 @@ int xen_evtchn_translate_pirq_msi(struct kvm_irq_routing_entry *route,
return -EINVAL;
}
- cpu = qemu_get_cpu(s->port_table[port].vcpu);
+ cpu = qemu_get_cpu(s->port_table[port].vcpu, NULL);
if (!cpu) {
return -EINVAL;
}
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 2ebf880ead..cdf21dfc11 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -392,7 +392,7 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
s->cpu = g_new0(GICv3CPUState, s->num_cpu);
for (i = 0; i < s->num_cpu; i++) {
- CPUState *cpu = qemu_get_cpu(i);
+ CPUState *cpu = qemu_get_cpu(i, NULL);
uint64_t cpu_affid;
s->cpu[i].cpu = cpu;
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index d07b13eb27..f765b3d4b5 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -2795,7 +2795,7 @@ void gicv3_init_cpuif(GICv3State *s)
int i;
for (i = 0; i < s->num_cpu; i++) {
- ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i, NULL));
GICv3CPUState *cs = &s->cpu[i];
/*
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index 72ad916d3d..d1ff9886aa 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -808,7 +808,7 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
for (i = 0; i < s->num_cpu; i++) {
- ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i, NULL));
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
}
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index ab1a0b4b3a..a97c0449ec 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -483,7 +483,7 @@ static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp)
/* Claim software interrupt bits */
for (i = 0; i < swi->num_harts; i++) {
- RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i));
+ RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i, NULL));
/* We don't claim mip.SSIP because it is writable by software */
if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) {
error_report("MSIP already claimed");
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 5522ede2cf..a32e7f1924 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -392,7 +392,7 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
* hardware controlled when a PLIC is attached.
*/
for (i = 0; i < s->num_harts; i++) {
- RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
+ RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i, NULL));
if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
error_setg(errp, "SEIP already claimed");
return;
@@ -499,7 +499,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
for (i = 0; i < plic->num_addrs; i++) {
int cpu_num = plic->addr_config[i].hartid;
- CPUState *cpu = qemu_get_cpu(cpu_num);
+ CPUState *cpu = qemu_get_cpu(cpu_num, NULL);
if (plic->addr_config[i].mode == PLICMode_M) {
qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 2952fe452e..e888aea892 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -170,7 +170,7 @@ static void fdt_add_cpu_nodes(const LoongArchMachineState *lams)
/* cpu nodes */
for (num = smp_cpus - 1; num >= 0; num--) {
char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
- LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));
+ LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num, NULL));
CPUState *cs = CPU(cpu);
qemu_fdt_add_subnode(ms->fdt, nodename);
@@ -560,7 +560,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
* +--------+ +---------+ +---------+
*/
for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
- cpu_state = qemu_get_cpu(cpu);
+ cpu_state = qemu_get_cpu(cpu, NULL);
cpudev = DEVICE(cpu_state);
lacpu = LOONGARCH_CPU(cpu_state);
env = &(lacpu->env);
@@ -594,7 +594,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
* cpu_pin[9:2] <= intc_pin[7:0]
*/
for (cpu = 0; cpu < MIN(ms->smp.cpus, EXTIOI_CPUS); cpu++) {
- cpudev = DEVICE(qemu_get_cpu(cpu));
+ cpudev = DEVICE(qemu_get_cpu(cpu, NULL));
for (pin = 0; pin < LS3A_INTC_IP; pin++) {
qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
qdev_get_gpio_in(cpudev, pin + 2));
@@ -726,7 +726,7 @@ static void loongarch_direct_kernel_boot(LoongArchMachineState *lams,
kernel_addr = load_kernel_info(loaderparams);
if (!machine->firmware) {
for (i = 0; i < machine->smp.cpus; i++) {
- lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
+ lacpu = LOONGARCH_CPU(qemu_get_cpu(i, NULL));
lacpu->env.load_elf = true;
lacpu->env.elf_address = kernel_addr;
}
@@ -859,7 +859,7 @@ static void loongarch_init(MachineState *machine)
fdt_add_flash_node(lams);
/* register reset function */
for (i = 0; i < machine->smp.cpus; i++) {
- lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
+ lacpu = LOONGARCH_CPU(qemu_get_cpu(i, NULL));
qemu_register_reset(reset_load_elf, lacpu);
}
/* Initialize the IO interrupt subsystem */
diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c
index 2ab1b4f059..a0851f58a9 100644
--- a/hw/m68k/mcf5206.c
+++ b/hw/m68k/mcf5206.c
@@ -601,7 +601,7 @@ static void mcf5206_mbar_realize(DeviceState *dev, Error **errp)
s->timer[1] = m5206_timer_init(s->pic[10]);
s->uart[0] = mcf_uart_init(s->pic[12], serial_hd(0));
s->uart[1] = mcf_uart_init(s->pic[13], serial_hd(1));
- s->cpu = M68K_CPU(qemu_get_cpu(0));
+ s->cpu = M68K_CPU(qemu_get_cpu(0, NULL));
}
static void mcf5206_mbar_class_init(ObjectClass *oc, void *data)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index e04114fb3c..380bbe1fe6 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -495,7 +495,7 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
char *cpu_name;
uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20);
- cpu = qemu_get_cpu(i);
+ cpu = qemu_get_cpu(i, NULL);
if (cpu == NULL) {
continue;
}
diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c
index bbce63e8a4..3b113fbbdb 100644
--- a/hw/ppc/ppce500_spin.c
+++ b/hw/ppc/ppce500_spin.c
@@ -125,7 +125,7 @@ static void spin_write(void *opaque, hwaddr addr, uint64_t value,
SpinInfo *curspin = &s->spin[env_idx];
uint8_t *curspin_p = (uint8_t*)curspin;
- cpu = qemu_get_cpu(env_idx);
+ cpu = qemu_get_cpu(env_idx, NULL);
if (cpu == NULL) {
/* Unknown CPU */
return;
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 52bf8e67de..ea733b3df1 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -49,7 +49,7 @@ char *riscv_plic_hart_config_string(int hart_count)
int i;
for (i = 0; i < hart_count; i++) {
- CPUState *cs = qemu_get_cpu(i);
+ CPUState *cs = qemu_get_cpu(i, NULL);
CPURISCVState *env = &RISCV_CPU(cs)->env;
if (kvm_enabled()) {
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 436503f1ba..e98361de19 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -190,7 +190,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
for (i = 0; i < ms->smp.cpus; i++) {
- CPUState *cpu = qemu_get_cpu(i);
+ CPUState *cpu = qemu_get_cpu(i, NULL);
qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
@@ -223,7 +223,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
0, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_TIMER_TIMEREXPIRED0_0));
qdev_connect_gpio_out(DEVICE(&s->timer), 0,
- qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
+ qdev_get_gpio_in(DEVICE(qemu_get_cpu(0, NULL)),
IRQ_M_TIMER));
/* SPI-Hosts */
diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c
index 515dcf51b5..14cd0a1f7b 100644
--- a/hw/s390x/ipl.c
+++ b/hw/s390x/ipl.c
@@ -671,7 +671,7 @@ void s390_ipl_get_reset_request(CPUState **cs, enum s390_reset *reset_type)
{
S390IPLState *ipl = get_ipl_device();
- *cs = qemu_get_cpu(ipl->reset_cpu_index);
+ *cs = qemu_get_cpu(ipl->reset_cpu_index, NULL);
if (!*cs) {
/* use any CPU */
*cs = first_cpu;
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index 2d75f2131f..7628b746a8 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++ b/hw/s390x/s390-virtio-ccw.c
@@ -583,7 +583,7 @@ static HotplugHandler *s390_get_hotplug_handler(MachineState *machine,
static void s390_nmi(NMIState *n, int cpu_index, Error **errp)
{
- CPUState *cs = qemu_get_cpu(cpu_index);
+ CPUState *cs = qemu_get_cpu(cpu_index, NULL);
s390_cpu_restart(S390_CPU(cs));
}
diff --git a/monitor/hmp-cmds-target.c b/monitor/hmp-cmds-target.c
index d9fbcac08d..e501b997f8 100644
--- a/monitor/hmp-cmds-target.c
+++ b/monitor/hmp-cmds-target.c
@@ -36,7 +36,7 @@ int monitor_set_cpu(Monitor *mon, int cpu_index)
{
CPUState *cpu;
- cpu = qemu_get_cpu(cpu_index);
+ cpu = qemu_get_cpu(cpu_index, NULL);
if (cpu == NULL) {
return -1;
}
@@ -103,7 +103,7 @@ void hmp_info_registers(Monitor *mon, const QDict *qdict)
cpu_dump_state(cs, NULL, CPU_DUMP_FPU);
}
} else {
- cs = vcpu >= 0 ? qemu_get_cpu(vcpu) : mon_get_cpu(mon);
+ cs = vcpu >= 0 ? qemu_get_cpu(vcpu, NULL) : mon_get_cpu(mon);
if (!cs) {
if (vcpu >= 0) {
diff --git a/stats/stats-hmp-cmds.c b/stats/stats-hmp-cmds.c
index 1f91bf8bd5..0e58336c7f 100644
--- a/stats/stats-hmp-cmds.c
+++ b/stats/stats-hmp-cmds.c
@@ -147,7 +147,7 @@ static StatsFilter *stats_filter(StatsTarget target, const char *names,
case STATS_TARGET_VCPU:
{
strList *vcpu_list = NULL;
- CPUState *cpu = qemu_get_cpu(cpu_index);
+ CPUState *cpu = qemu_get_cpu(cpu_index, NULL);
char *canonical_path = object_get_canonical_path(OBJECT(cpu));
QAPI_LIST_PREPEND(vcpu_list, canonical_path);
diff --git a/system/cpus.c b/system/cpus.c
index 0848e0dbdb..3e7c80e91b 100644
--- a/system/cpus.c
+++ b/system/cpus.c
@@ -751,7 +751,7 @@ void qmp_memsave(int64_t addr, int64_t size, const char *filename,
cpu_index = 0;
}
- cpu = qemu_get_cpu(cpu_index);
+ cpu = qemu_get_cpu(cpu_index, NULL);
if (cpu == NULL) {
error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "cpu-index",
"a CPU number");
diff --git a/target/i386/kvm/xen-emu.c b/target/i386/kvm/xen-emu.c
index 76348f9d5d..f289af906c 100644
--- a/target/i386/kvm/xen-emu.c
+++ b/target/i386/kvm/xen-emu.c
@@ -384,7 +384,7 @@ static void do_set_vcpu_info_gpa(CPUState *cs, run_on_cpu_data data)
void *kvm_xen_get_vcpu_info_hva(uint32_t vcpu_id)
{
- CPUState *cs = qemu_get_cpu(vcpu_id);
+ CPUState *cs = qemu_get_cpu(vcpu_id, NULL);
if (!cs) {
return NULL;
}
@@ -418,7 +418,7 @@ void kvm_xen_maybe_deassert_callback(CPUState *cs)
void kvm_xen_set_callback_asserted(void)
{
- CPUState *cs = qemu_get_cpu(0);
+ CPUState *cs = qemu_get_cpu(0, NULL);
if (cs) {
X86_CPU(cs)->env.xen_callback_asserted = true;
@@ -427,7 +427,7 @@ void kvm_xen_set_callback_asserted(void)
void kvm_xen_inject_vcpu_callback_vector(uint32_t vcpu_id, int type)
{
- CPUState *cs = qemu_get_cpu(vcpu_id);
+ CPUState *cs = qemu_get_cpu(vcpu_id, NULL);
uint8_t vector;
if (!cs) {
@@ -491,7 +491,7 @@ static void do_set_vcpu_timer_virq(CPUState *cs, run_on_cpu_data data)
int kvm_xen_set_vcpu_virq(uint32_t vcpu_id, uint16_t virq, uint16_t port)
{
- CPUState *cs = qemu_get_cpu(vcpu_id);
+ CPUState *cs = qemu_get_cpu(vcpu_id, NULL);
if (!cs) {
return -ENOENT;
@@ -588,7 +588,7 @@ static int xen_set_shared_info(uint64_t gfn)
trace_kvm_xen_set_shared_info(gfn);
for (i = 0; i < XEN_LEGACY_MAX_VCPUS; i++) {
- CPUState *cpu = qemu_get_cpu(i);
+ CPUState *cpu = qemu_get_cpu(i, NULL);
if (cpu) {
async_run_on_cpu(cpu, do_set_vcpu_info_default_gpa,
RUN_ON_CPU_HOST_ULONG(gpa));
@@ -834,7 +834,7 @@ static int kvm_xen_hcall_evtchn_upcall_vector(struct kvm_xen_exit *exit,
return -EINVAL;
}
- target_cs = qemu_get_cpu(up.vcpu);
+ target_cs = qemu_get_cpu(up.vcpu, NULL);
if (!target_cs) {
return -EINVAL;
}
@@ -1160,7 +1160,8 @@ static bool kvm_xen_hcall_vcpu_op(struct kvm_xen_exit *exit, X86CPU *cpu,
int cmd, int vcpu_id, uint64_t arg)
{
CPUState *cs = CPU(cpu);
- CPUState *dest = cs->cpu_index == vcpu_id ? cs : qemu_get_cpu(vcpu_id);
+ CPUState *dest = cs->cpu_index == vcpu_id ? cs : qemu_get_cpu(vcpu_id,
+ NULL);
int err;
if (!dest) {
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
index 6512846327..aca7be61dd 100644
--- a/target/i386/monitor.c
+++ b/target/i386/monitor.c
@@ -592,7 +592,7 @@ void hmp_mce(Monitor *mon, const QDict *qdict)
if (qdict_get_try_bool(qdict, "broadcast", false)) {
flags |= MCE_INJECT_BROADCAST;
}
- cs = qemu_get_cpu(cpu_index);
+ cs = qemu_get_cpu(cpu_index, NULL);
if (cs != NULL) {
cpu = X86_CPU(cs);
cpu_x86_inject_mce(mon, cpu, bank, status, mcg_status, addr, misc,
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 83ee54f766..17e9e06a15 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -117,7 +117,7 @@ static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
void cpu_set_exception_base(int vp_index, target_ulong address)
{
- MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
+ MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index, NULL));
vp->env.exception_base = address;
}
diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c
index 5da1124589..fcaba37c40 100644
--- a/target/mips/tcg/sysemu/cp0_helper.c
+++ b/target/mips/tcg/sysemu/cp0_helper.c
@@ -126,7 +126,7 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
cs = env_cpu(env);
vpe_idx = tc_idx / cs->nr_threads;
*tc = tc_idx % cs->nr_threads;
- other_cs = qemu_get_cpu(vpe_idx);
+ other_cs = qemu_get_cpu(vpe_idx, NULL);
if (other_cs == NULL) {
return env;
}
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index b1e77b3a2b..4a44ee56a9 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -150,7 +150,7 @@ uint32_t s390_get_hmfai(void)
static S390CPU *cpu;
if (!cpu) {
- cpu = S390_CPU(qemu_get_cpu(0));
+ cpu = S390_CPU(qemu_get_cpu(0, NULL));
}
if (!cpu || !cpu->model) {
@@ -164,7 +164,7 @@ uint8_t s390_get_mha_pow(void)
static S390CPU *cpu;
if (!cpu) {
- cpu = S390_CPU(qemu_get_cpu(0));
+ cpu = S390_CPU(qemu_get_cpu(0, NULL));
}
if (!cpu || !cpu->model) {
@@ -179,7 +179,7 @@ uint32_t s390_get_ibc_val(void)
static S390CPU *cpu;
if (!cpu) {
- cpu = S390_CPU(qemu_get_cpu(0));
+ cpu = S390_CPU(qemu_get_cpu(0, NULL));
}
if (!cpu || !cpu->model) {
@@ -199,7 +199,7 @@ void s390_get_feat_block(S390FeatType type, uint8_t *data)
static S390CPU *cpu;
if (!cpu) {
- cpu = S390_CPU(qemu_get_cpu(0));
+ cpu = S390_CPU(qemu_get_cpu(0, NULL));
}
if (!cpu || !cpu->model) {
@@ -213,7 +213,7 @@ bool s390_has_feat(S390Feat feat)
static S390CPU *cpu;
if (!cpu) {
- cpu = S390_CPU(qemu_get_cpu(0));
+ cpu = S390_CPU(qemu_get_cpu(0, NULL));
}
if (!cpu || !cpu->model) {
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 02/19] cpus: Filter for target specific CPU (generic)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
2023-10-20 16:36 ` [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 03/19] cpus: Filter for target specific CPU (arm) Philippe Mathieu-Daudé
` (17 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Radoslaw Biernacki, Leif Lindholm, Marcin Juszkiewicz,
Igor Mammedov, Ani Sinha, Shannon Zhao, Alistair Francis,
Palmer Dabbelt, Bin Meng, Weiwei Li, Daniel Henrique Barboza,
Liu Zhiwei, Song Gao, Thomas Huth, Aurelien Jarno, Jiaxun Yang,
Aleksandar Rikalo, David Hildenbrand, Ilya Leoshkevich
When the CPUState is casted to a specific target, enforce
that target CPU type as qemu_get_cpu() filter.
Mechanical change using the following coccinelle script:
@@
expression index;
@@
(
- ARM_CPU(qemu_get_cpu(index, NULL))
+ ARM_CPU(qemu_get_cpu(index, TYPE_ARM_CPU))
|
- LOONGARCH_CPU(qemu_get_cpu(index, NULL))
+ LOONGARCH_CPU(qemu_get_cpu(index, TYPE_LOONGARCH_CPU))
|
- M68K_CPU(qemu_get_cpu(index, NULL))
+ M68K_CPU(qemu_get_cpu(index, TYPE_M68K_CPU))
|
- MIPS_CPU(qemu_get_cpu(index, NULL))
+ MIPS_CPU(qemu_get_cpu(index, TYPE_MIPS_CPU))
|
- RISCV_CPU(qemu_get_cpu(index, NULL))
+ RISCV_CPU(qemu_get_cpu(index, TYPE_RISCV_CPU))
|
- S390_CPU(qemu_get_cpu(index, NULL))
+ S390_CPU(qemu_get_cpu(index, TYPE_S390_CPU))
)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/boot.c | 2 +-
hw/arm/pxa2xx_gpio.c | 2 +-
hw/arm/sbsa-ref.c | 2 +-
hw/arm/virt-acpi-build.c | 2 +-
hw/arm/virt.c | 6 +++---
hw/arm/xlnx-versal-virt.c | 2 +-
hw/intc/arm_gicv3_cpuif.c | 2 +-
hw/intc/arm_gicv3_kvm.c | 2 +-
hw/intc/riscv_aclint.c | 2 +-
hw/intc/sifive_plic.c | 2 +-
hw/loongarch/virt.c | 6 +++---
hw/m68k/mcf5206.c | 2 +-
target/mips/cpu.c | 2 +-
target/s390x/cpu_models.c | 10 +++++-----
14 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index e260168cf5..f7def3a60c 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -438,7 +438,7 @@ static void fdt_add_psci_node(void *fdt)
uint32_t cpu_off_fn;
uint32_t cpu_on_fn;
uint32_t migrate_fn;
- ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0, NULL));
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU));
const char *psci_method;
int64_t psci_conduit;
int rc;
diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c
index 0a698171ab..9795451f19 100644
--- a/hw/arm/pxa2xx_gpio.c
+++ b/hw/arm/pxa2xx_gpio.c
@@ -303,7 +303,7 @@ static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
{
PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
- s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu, NULL));
+ s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu, TYPE_ARM_CPU));
qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
qdev_init_gpio_out(dev, s->handler, s->lines);
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 3571d5038f..f6f64099c3 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -275,7 +275,7 @@ static void create_fdt(SBSAMachineState *sms)
for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
- ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu, NULL));
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu, TYPE_ARM_CPU));
CPUState *cs = CPU(armcpu);
uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu);
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index fd6c239c31..0d09007d9b 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -727,7 +727,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
build_append_int_noprefix(table_data, 0, 3); /* Reserved */
for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
- ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i, NULL));
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i, TYPE_ARM_CPU));
uint64_t physical_base_address = 0, gich = 0, gicv = 0;
uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0;
uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a8f9d88519..be31ef5718 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -355,7 +355,7 @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
qemu_fdt_add_subnode(ms->fdt, "/timer");
- armcpu = ARM_CPU(qemu_get_cpu(0, NULL));
+ armcpu = ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU));
if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
@@ -394,7 +394,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
* at least one of them has Aff3 populated, we set #address-cells to 2.
*/
for (cpu = 0; cpu < smp_cpus; cpu++) {
- ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu, NULL));
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu, TYPE_ARM_CPU));
if (armcpu->mp_affinity & ARM_AFF3_MASK) {
addr_cells = 2;
@@ -408,7 +408,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
- ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu, NULL));
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu, TYPE_ARM_CPU));
CPUState *cs = CPU(armcpu);
qemu_fdt_add_subnode(ms->fdt, nodename);
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 419ee3b882..2646b63b79 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -103,7 +103,7 @@ static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit)
for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) {
char *name = g_strdup_printf("/cpus/cpu@%d", i);
- ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i, NULL));
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i, TYPE_ARM_CPU));
qemu_fdt_add_subnode(s->fdt, name);
qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity);
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index f765b3d4b5..3b11b33b3e 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -2795,7 +2795,7 @@ void gicv3_init_cpuif(GICv3State *s)
int i;
for (i = 0; i < s->num_cpu; i++) {
- ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i, NULL));
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i, TYPE_ARM_CPU));
GICv3CPUState *cs = &s->cpu[i];
/*
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index d1ff9886aa..440a84f0fe 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -808,7 +808,7 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
for (i = 0; i < s->num_cpu; i++) {
- ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i, NULL));
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i, TYPE_ARM_CPU));
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
}
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index a97c0449ec..7e57c03ef7 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -483,7 +483,7 @@ static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp)
/* Claim software interrupt bits */
for (i = 0; i < swi->num_harts; i++) {
- RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i, NULL));
+ RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i, TYPE_RISCV_CPU));
/* We don't claim mip.SSIP because it is writable by software */
if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) {
error_report("MSIP already claimed");
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index a32e7f1924..3e2534ac04 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -392,7 +392,7 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
* hardware controlled when a PLIC is attached.
*/
for (i = 0; i < s->num_harts; i++) {
- RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i, NULL));
+ RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i, TYPE_RISCV_CPU));
if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
error_setg(errp, "SEIP already claimed");
return;
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index e888aea892..902e32a3e3 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -170,7 +170,7 @@ static void fdt_add_cpu_nodes(const LoongArchMachineState *lams)
/* cpu nodes */
for (num = smp_cpus - 1; num >= 0; num--) {
char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
- LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num, NULL));
+ LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num, TYPE_LOONGARCH_CPU));
CPUState *cs = CPU(cpu);
qemu_fdt_add_subnode(ms->fdt, nodename);
@@ -726,7 +726,7 @@ static void loongarch_direct_kernel_boot(LoongArchMachineState *lams,
kernel_addr = load_kernel_info(loaderparams);
if (!machine->firmware) {
for (i = 0; i < machine->smp.cpus; i++) {
- lacpu = LOONGARCH_CPU(qemu_get_cpu(i, NULL));
+ lacpu = LOONGARCH_CPU(qemu_get_cpu(i, TYPE_LOONGARCH_CPU));
lacpu->env.load_elf = true;
lacpu->env.elf_address = kernel_addr;
}
@@ -859,7 +859,7 @@ static void loongarch_init(MachineState *machine)
fdt_add_flash_node(lams);
/* register reset function */
for (i = 0; i < machine->smp.cpus; i++) {
- lacpu = LOONGARCH_CPU(qemu_get_cpu(i, NULL));
+ lacpu = LOONGARCH_CPU(qemu_get_cpu(i, TYPE_LOONGARCH_CPU));
qemu_register_reset(reset_load_elf, lacpu);
}
/* Initialize the IO interrupt subsystem */
diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c
index a0851f58a9..d409c25ee6 100644
--- a/hw/m68k/mcf5206.c
+++ b/hw/m68k/mcf5206.c
@@ -601,7 +601,7 @@ static void mcf5206_mbar_realize(DeviceState *dev, Error **errp)
s->timer[1] = m5206_timer_init(s->pic[10]);
s->uart[0] = mcf_uart_init(s->pic[12], serial_hd(0));
s->uart[1] = mcf_uart_init(s->pic[13], serial_hd(1));
- s->cpu = M68K_CPU(qemu_get_cpu(0, NULL));
+ s->cpu = M68K_CPU(qemu_get_cpu(0, TYPE_M68K_CPU));
}
static void mcf5206_mbar_class_init(ObjectClass *oc, void *data)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 17e9e06a15..3ba329fa61 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -117,7 +117,7 @@ static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
void cpu_set_exception_base(int vp_index, target_ulong address)
{
- MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index, NULL));
+ MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index, TYPE_MIPS_CPU));
vp->env.exception_base = address;
}
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index 4a44ee56a9..7d1f5df114 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -150,7 +150,7 @@ uint32_t s390_get_hmfai(void)
static S390CPU *cpu;
if (!cpu) {
- cpu = S390_CPU(qemu_get_cpu(0, NULL));
+ cpu = S390_CPU(qemu_get_cpu(0, TYPE_S390_CPU));
}
if (!cpu || !cpu->model) {
@@ -164,7 +164,7 @@ uint8_t s390_get_mha_pow(void)
static S390CPU *cpu;
if (!cpu) {
- cpu = S390_CPU(qemu_get_cpu(0, NULL));
+ cpu = S390_CPU(qemu_get_cpu(0, TYPE_S390_CPU));
}
if (!cpu || !cpu->model) {
@@ -179,7 +179,7 @@ uint32_t s390_get_ibc_val(void)
static S390CPU *cpu;
if (!cpu) {
- cpu = S390_CPU(qemu_get_cpu(0, NULL));
+ cpu = S390_CPU(qemu_get_cpu(0, TYPE_S390_CPU));
}
if (!cpu || !cpu->model) {
@@ -199,7 +199,7 @@ void s390_get_feat_block(S390FeatType type, uint8_t *data)
static S390CPU *cpu;
if (!cpu) {
- cpu = S390_CPU(qemu_get_cpu(0, NULL));
+ cpu = S390_CPU(qemu_get_cpu(0, TYPE_S390_CPU));
}
if (!cpu || !cpu->model) {
@@ -213,7 +213,7 @@ bool s390_has_feat(S390Feat feat)
static S390CPU *cpu;
if (!cpu) {
- cpu = S390_CPU(qemu_get_cpu(0, NULL));
+ cpu = S390_CPU(qemu_get_cpu(0, TYPE_S390_CPU));
}
if (!cpu || !cpu->model) {
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 03/19] cpus: Filter for target specific CPU (arm)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
2023-10-20 16:36 ` [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 02/19] cpus: Filter for target specific CPU (generic) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 04/19] cpus: Filter for target specific CPU (loongarch) Philippe Mathieu-Daudé
` (16 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Andrey Smirnov, Radoslaw Biernacki, Leif Lindholm,
Marcin Juszkiewicz
Enforce qemu_get_cpu() to return ARM CPUs in ARM specific files.
Mechanical change using the following coccinelle script:
@@ expression index; @@
- qemu_get_cpu(index, NULL)
+ qemu_get_cpu(index, TYPE_ARM_CPU)
and manually including "target/arm/cpu-qom.h" in
hw/intc/arm_gicv3_common.c.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/fsl-imx7.c | 2 +-
hw/arm/sbsa-ref.c | 2 +-
hw/arm/vexpress.c | 2 +-
hw/arm/virt.c | 2 +-
hw/cpu/a15mpcore.c | 4 ++--
hw/cpu/a9mpcore.c | 2 +-
hw/intc/arm_gicv3_common.c | 3 ++-
7 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index 1c1585f3e1..7a62e9f5cf 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -212,7 +212,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
for (i = 0; i < smp_cpus; i++) {
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
- DeviceState *d = DEVICE(qemu_get_cpu(i, NULL));
+ DeviceState *d = DEVICE(qemu_get_cpu(i, TYPE_ARM_CPU));
irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
sysbus_connect_irq(sbd, i, irq);
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index f6f64099c3..a85004809f 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -478,7 +478,7 @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
* and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
*/
for (i = 0; i < smp_cpus; i++) {
- DeviceState *cpudev = DEVICE(qemu_get_cpu(i, NULL));
+ DeviceState *cpudev = DEVICE(qemu_get_cpu(i, TYPE_ARM_CPU));
int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
int irq;
/*
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 0590332fe5..e20d865d5a 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -257,7 +257,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type,
/* Connect the CPUs to the GIC */
for (n = 0; n < smp_cpus; n++) {
- DeviceState *cpudev = DEVICE(qemu_get_cpu(n, NULL));
+ DeviceState *cpudev = DEVICE(qemu_get_cpu(n, TYPE_ARM_CPU));
sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
sysbus_connect_irq(busdev, n + smp_cpus,
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index be31ef5718..da5b738f0a 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -799,7 +799,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
* and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
*/
for (i = 0; i < smp_cpus; i++) {
- DeviceState *cpudev = DEVICE(qemu_get_cpu(i, NULL));
+ DeviceState *cpudev = DEVICE(qemu_get_cpu(i, TYPE_ARM_CPU));
int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
/* Mapping from the output timer irq lines from the CPU to the
* GIC PPI inputs we use for the virt board.
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index 8c9098d5d3..7ec5b27207 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -65,7 +65,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
/* Make the GIC's TZ support match the CPUs. We assume that
* either all the CPUs have TZ, or none do.
*/
- cpuobj = OBJECT(qemu_get_cpu(0, NULL));
+ cpuobj = OBJECT(qemu_get_cpu(0, TYPE_ARM_CPU));
has_el3 = object_property_find(cpuobj, "has_el3") &&
object_property_get_bool(cpuobj, "has_el3", &error_abort);
qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
@@ -90,7 +90,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
* appropriate GIC PPI inputs
*/
for (i = 0; i < s->num_cpu; i++) {
- DeviceState *cpudev = DEVICE(qemu_get_cpu(i, NULL));
+ DeviceState *cpudev = DEVICE(qemu_get_cpu(i, TYPE_ARM_CPU));
int ppibase = s->num_irq - 32 + i * 32;
int irq;
/* Mapping from the output timer irq lines from the CPU to the
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 62b7fb3836..a9919ac78a 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -56,7 +56,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
CPUState *cpu0;
Object *cpuobj;
- cpu0 = qemu_get_cpu(0, NULL);
+ cpu0 = qemu_get_cpu(0, TYPE_ARM_CPU);
cpuobj = OBJECT(cpu0);
if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) {
/* We might allow Cortex-A5 once we model it */
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index cdf21dfc11..e7ad5aa202 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -31,6 +31,7 @@
#include "migration/vmstate.h"
#include "gicv3_internal.h"
#include "hw/arm/linux-boot-if.h"
+#include "target/arm/cpu-qom.h"
#include "sysemu/kvm.h"
@@ -392,7 +393,7 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
s->cpu = g_new0(GICv3CPUState, s->num_cpu);
for (i = 0; i < s->num_cpu; i++) {
- CPUState *cpu = qemu_get_cpu(i, NULL);
+ CPUState *cpu = qemu_get_cpu(i, TYPE_ARM_CPU);
uint64_t cpu_affid;
s->cpu[i].cpu = cpu;
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 04/19] cpus: Filter for target specific CPU (loongarch)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 03/19] cpus: Filter for target specific CPU (arm) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 05/19] cpus: Filter for target specific CPU (mips) Philippe Mathieu-Daudé
` (15 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé, Song Gao
Enforce qemu_get_cpu() to return LoongArch CPUs in LoongArch
specific files.
Mechanical change using the following coccinelle script:
@@ expression index; @@
- qemu_get_cpu(index, NULL)
+ qemu_get_cpu(index, TYPE_LOONGARCH_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/loongarch/virt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 902e32a3e3..83ca7d6b98 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -560,7 +560,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
* +--------+ +---------+ +---------+
*/
for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
- cpu_state = qemu_get_cpu(cpu, NULL);
+ cpu_state = qemu_get_cpu(cpu, TYPE_LOONGARCH_CPU);
cpudev = DEVICE(cpu_state);
lacpu = LOONGARCH_CPU(cpu_state);
env = &(lacpu->env);
@@ -594,7 +594,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
* cpu_pin[9:2] <= intc_pin[7:0]
*/
for (cpu = 0; cpu < MIN(ms->smp.cpus, EXTIOI_CPUS); cpu++) {
- cpudev = DEVICE(qemu_get_cpu(cpu, NULL));
+ cpudev = DEVICE(qemu_get_cpu(cpu, TYPE_LOONGARCH_CPU));
for (pin = 0; pin < LS3A_INTC_IP; pin++) {
qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
qdev_get_gpio_in(cpudev, pin + 2));
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 05/19] cpus: Filter for target specific CPU (mips)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 04/19] cpus: Filter for target specific CPU (loongarch) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 06/19] cpus: Filter for target specific CPU (s390x) Philippe Mathieu-Daudé
` (14 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo
Enforce qemu_get_cpu() to return MIPS CPUs in MIPS specific files.
Mechanical change using the following coccinelle script:
@@ expression index; @@
- qemu_get_cpu(index, NULL)
+ qemu_get_cpu(index, TYPE_MIPS_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/sysemu/cp0_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c
index fcaba37c40..af0cd60829 100644
--- a/target/mips/tcg/sysemu/cp0_helper.c
+++ b/target/mips/tcg/sysemu/cp0_helper.c
@@ -126,7 +126,7 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
cs = env_cpu(env);
vpe_idx = tc_idx / cs->nr_threads;
*tc = tc_idx % cs->nr_threads;
- other_cs = qemu_get_cpu(vpe_idx, NULL);
+ other_cs = qemu_get_cpu(vpe_idx, TYPE_MIPS_CPU);
if (other_cs == NULL) {
return env;
}
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 06/19] cpus: Filter for target specific CPU (s390x)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 05/19] cpus: Filter for target specific CPU (mips) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 07/19] cpus: Filter for target specific CPU (riscv) Philippe Mathieu-Daudé
` (13 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Christian Borntraeger, Halil Pasic, Eric Farman,
David Hildenbrand, Ilya Leoshkevich
Enforce qemu_get_cpu() to return S390X CPUs in S390X specific files.
Mechanical change using the following coccinelle script:
@@ expression index; @@
- qemu_get_cpu(index, NULL)
+ qemu_get_cpu(index, TYPE_S390_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/s390x/ipl.c | 2 +-
hw/s390x/s390-virtio-ccw.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c
index 14cd0a1f7b..377f43416c 100644
--- a/hw/s390x/ipl.c
+++ b/hw/s390x/ipl.c
@@ -671,7 +671,7 @@ void s390_ipl_get_reset_request(CPUState **cs, enum s390_reset *reset_type)
{
S390IPLState *ipl = get_ipl_device();
- *cs = qemu_get_cpu(ipl->reset_cpu_index, NULL);
+ *cs = qemu_get_cpu(ipl->reset_cpu_index, TYPE_S390_CPU);
if (!*cs) {
/* use any CPU */
*cs = first_cpu;
diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
index 7628b746a8..3bb4b13c5e 100644
--- a/hw/s390x/s390-virtio-ccw.c
+++ b/hw/s390x/s390-virtio-ccw.c
@@ -583,7 +583,7 @@ static HotplugHandler *s390_get_hotplug_handler(MachineState *machine,
static void s390_nmi(NMIState *n, int cpu_index, Error **errp)
{
- CPUState *cs = qemu_get_cpu(cpu_index, NULL);
+ CPUState *cs = qemu_get_cpu(cpu_index, TYPE_S390_CPU);
s390_cpu_restart(S390_CPU(cs));
}
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 07/19] cpus: Filter for target specific CPU (riscv)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 06/19] cpus: Filter for target specific CPU (s390x) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 08/19] cpus: Filter for target specific CPU (ppc) Philippe Mathieu-Daudé
` (12 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Alistair Francis, Bin Meng, Palmer Dabbelt, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
Enforce qemu_get_cpu() to return RISCV CPUs in RISCV specific files.
Mechanical change using the following coccinelle script:
@@ expression index; @@
- qemu_get_cpu(index, NULL)
+ qemu_get_cpu(index, TYPE_RISCV_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/intc/sifive_plic.c | 2 +-
hw/riscv/boot.c | 2 +-
hw/riscv/opentitan.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 3e2534ac04..ea0e7af16e 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -499,7 +499,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
for (i = 0; i < plic->num_addrs; i++) {
int cpu_num = plic->addr_config[i].hartid;
- CPUState *cpu = qemu_get_cpu(cpu_num, NULL);
+ CPUState *cpu = qemu_get_cpu(cpu_num, TYPE_RISCV_CPU);
if (plic->addr_config[i].mode == PLICMode_M) {
qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index ea733b3df1..1d004660d4 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -49,7 +49,7 @@ char *riscv_plic_hart_config_string(int hart_count)
int i;
for (i = 0; i < hart_count; i++) {
- CPUState *cs = qemu_get_cpu(i, NULL);
+ CPUState *cs = qemu_get_cpu(i, TYPE_RISCV_CPU);
CPURISCVState *env = &RISCV_CPU(cs)->env;
if (kvm_enabled()) {
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index e98361de19..106ef5d2d0 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -190,7 +190,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
for (i = 0; i < ms->smp.cpus; i++) {
- CPUState *cpu = qemu_get_cpu(i, NULL);
+ CPUState *cpu = qemu_get_cpu(i, TYPE_RISCV_CPU);
qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
@@ -223,7 +223,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
0, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_TIMER_TIMEREXPIRED0_0));
qdev_connect_gpio_out(DEVICE(&s->timer), 0,
- qdev_get_gpio_in(DEVICE(qemu_get_cpu(0, NULL)),
+ qdev_get_gpio_in(DEVICE(qemu_get_cpu(0, TYPE_RISCV_CPU)),
IRQ_M_TIMER));
/* SPI-Hosts */
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 08/19] cpus: Filter for target specific CPU (ppc)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 07/19] cpus: Filter for target specific CPU (riscv) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 09/19] cpus: Filter for target specific CPU (x86) Philippe Mathieu-Daudé
` (11 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé
Enforce qemu_get_cpu() to return PPC CPUs in PPC specific files.
Mechanical change using the following coccinelle script:
@@ expression index; @@
- qemu_get_cpu(index, NULL)
+ qemu_get_cpu(index, TYPE_POWERPC_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/ppc/e500.c | 2 +-
hw/ppc/ppce500_spin.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 380bbe1fe6..c4bf3fef32 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -495,7 +495,7 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
char *cpu_name;
uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20);
- cpu = qemu_get_cpu(i, NULL);
+ cpu = qemu_get_cpu(i, TYPE_POWERPC_CPU);
if (cpu == NULL) {
continue;
}
diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c
index 3b113fbbdb..142bd45f18 100644
--- a/hw/ppc/ppce500_spin.c
+++ b/hw/ppc/ppce500_spin.c
@@ -125,7 +125,7 @@ static void spin_write(void *opaque, hwaddr addr, uint64_t value,
SpinInfo *curspin = &s->spin[env_idx];
uint8_t *curspin_p = (uint8_t*)curspin;
- cpu = qemu_get_cpu(env_idx, NULL);
+ cpu = qemu_get_cpu(env_idx, TYPE_POWERPC_CPU);
if (cpu == NULL) {
/* Unknown CPU */
return;
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 09/19] cpus: Filter for target specific CPU (x86)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 08/19] cpus: Filter for target specific CPU (ppc) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 10/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_ARM_CPU) Philippe Mathieu-Daudé
` (10 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
David Woodhouse, Paul Durrant, Marcel Apfelbaum, Marcelo Tosatti,
kvm
Enforce qemu_get_cpu() to return X86 CPUs in X86 specific files.
Mechanical change using the following coccinelle script:
@@ expression index; @@
- qemu_get_cpu(index, NULL)
+ qemu_get_cpu(index, TYPE_X86_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/hyperv/hyperv.c | 2 +-
hw/i386/kvm/xen_evtchn.c | 8 ++++----
target/i386/kvm/xen-emu.c | 14 +++++++-------
target/i386/monitor.c | 2 +-
4 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c
index a43f29ad8d..cdda93e14d 100644
--- a/hw/hyperv/hyperv.c
+++ b/hw/hyperv/hyperv.c
@@ -226,7 +226,7 @@ struct HvSintRoute {
static CPUState *hyperv_find_vcpu(uint32_t vp_index)
{
- CPUState *cs = qemu_get_cpu(vp_index, NULL);
+ CPUState *cs = qemu_get_cpu(vp_index, TYPE_X86_CPU);
assert(hyperv_vp_index(cs) == vp_index);
return cs;
}
diff --git a/hw/i386/kvm/xen_evtchn.c b/hw/i386/kvm/xen_evtchn.c
index de3650ba3b..d75b53934d 100644
--- a/hw/i386/kvm/xen_evtchn.c
+++ b/hw/i386/kvm/xen_evtchn.c
@@ -542,7 +542,7 @@ static void deassign_kernel_port(evtchn_port_t port)
static int assign_kernel_port(uint16_t type, evtchn_port_t port,
uint32_t vcpu_id)
{
- CPUState *cpu = qemu_get_cpu(vcpu_id, NULL);
+ CPUState *cpu = qemu_get_cpu(vcpu_id, TYPE_X86_CPU);
struct kvm_xen_hvm_attr ha;
if (!cpu) {
@@ -589,7 +589,7 @@ static bool valid_port(evtchn_port_t port)
static bool valid_vcpu(uint32_t vcpu)
{
- return !!qemu_get_cpu(vcpu, NULL);
+ return !!qemu_get_cpu(vcpu, TYPE_X86_CPU);
}
static void unbind_backend_ports(XenEvtchnState *s)
@@ -917,7 +917,7 @@ static int set_port_pending(XenEvtchnState *s, evtchn_port_t port)
if (s->evtchn_in_kernel) {
XenEvtchnPort *p = &s->port_table[port];
- CPUState *cpu = qemu_get_cpu(p->vcpu, NULL);
+ CPUState *cpu = qemu_get_cpu(p->vcpu, TYPE_X86_CPU);
struct kvm_irq_routing_xen_evtchn evt;
if (!cpu) {
@@ -1779,7 +1779,7 @@ int xen_evtchn_translate_pirq_msi(struct kvm_irq_routing_entry *route,
return -EINVAL;
}
- cpu = qemu_get_cpu(s->port_table[port].vcpu, NULL);
+ cpu = qemu_get_cpu(s->port_table[port].vcpu, TYPE_X86_CPU);
if (!cpu) {
return -EINVAL;
}
diff --git a/target/i386/kvm/xen-emu.c b/target/i386/kvm/xen-emu.c
index f289af906c..0a973c0259 100644
--- a/target/i386/kvm/xen-emu.c
+++ b/target/i386/kvm/xen-emu.c
@@ -384,7 +384,7 @@ static void do_set_vcpu_info_gpa(CPUState *cs, run_on_cpu_data data)
void *kvm_xen_get_vcpu_info_hva(uint32_t vcpu_id)
{
- CPUState *cs = qemu_get_cpu(vcpu_id, NULL);
+ CPUState *cs = qemu_get_cpu(vcpu_id, TYPE_X86_CPU);
if (!cs) {
return NULL;
}
@@ -418,7 +418,7 @@ void kvm_xen_maybe_deassert_callback(CPUState *cs)
void kvm_xen_set_callback_asserted(void)
{
- CPUState *cs = qemu_get_cpu(0, NULL);
+ CPUState *cs = qemu_get_cpu(0, TYPE_X86_CPU);
if (cs) {
X86_CPU(cs)->env.xen_callback_asserted = true;
@@ -427,7 +427,7 @@ void kvm_xen_set_callback_asserted(void)
void kvm_xen_inject_vcpu_callback_vector(uint32_t vcpu_id, int type)
{
- CPUState *cs = qemu_get_cpu(vcpu_id, NULL);
+ CPUState *cs = qemu_get_cpu(vcpu_id, TYPE_X86_CPU);
uint8_t vector;
if (!cs) {
@@ -491,7 +491,7 @@ static void do_set_vcpu_timer_virq(CPUState *cs, run_on_cpu_data data)
int kvm_xen_set_vcpu_virq(uint32_t vcpu_id, uint16_t virq, uint16_t port)
{
- CPUState *cs = qemu_get_cpu(vcpu_id, NULL);
+ CPUState *cs = qemu_get_cpu(vcpu_id, TYPE_X86_CPU);
if (!cs) {
return -ENOENT;
@@ -588,7 +588,7 @@ static int xen_set_shared_info(uint64_t gfn)
trace_kvm_xen_set_shared_info(gfn);
for (i = 0; i < XEN_LEGACY_MAX_VCPUS; i++) {
- CPUState *cpu = qemu_get_cpu(i, NULL);
+ CPUState *cpu = qemu_get_cpu(i, TYPE_X86_CPU);
if (cpu) {
async_run_on_cpu(cpu, do_set_vcpu_info_default_gpa,
RUN_ON_CPU_HOST_ULONG(gpa));
@@ -834,7 +834,7 @@ static int kvm_xen_hcall_evtchn_upcall_vector(struct kvm_xen_exit *exit,
return -EINVAL;
}
- target_cs = qemu_get_cpu(up.vcpu, NULL);
+ target_cs = qemu_get_cpu(up.vcpu, TYPE_X86_CPU);
if (!target_cs) {
return -EINVAL;
}
@@ -1161,7 +1161,7 @@ static bool kvm_xen_hcall_vcpu_op(struct kvm_xen_exit *exit, X86CPU *cpu,
{
CPUState *cs = CPU(cpu);
CPUState *dest = cs->cpu_index == vcpu_id ? cs : qemu_get_cpu(vcpu_id,
- NULL);
+ TYPE_X86_CPU);
int err;
if (!dest) {
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
index aca7be61dd..01bfb4e3f1 100644
--- a/target/i386/monitor.c
+++ b/target/i386/monitor.c
@@ -592,7 +592,7 @@ void hmp_mce(Monitor *mon, const QDict *qdict)
if (qdict_get_try_bool(qdict, "broadcast", false)) {
flags |= MCE_INJECT_BROADCAST;
}
- cs = qemu_get_cpu(cpu_index, NULL);
+ cs = qemu_get_cpu(cpu_index, TYPE_X86_CPU);
if (cs != NULL) {
cpu = X86_CPU(cs);
cpu_x86_inject_mce(mon, cpu, bank, status, mcg_status, addr, misc,
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 10/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_ARM_CPU)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 09/19] cpus: Filter for target specific CPU (x86) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:53 ` Cédric Le Goater
2023-10-20 16:36 ` [PATCH 11/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_POWERPC_CPU) Philippe Mathieu-Daudé
` (9 subsequent siblings)
19 siblings, 1 reply; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Cédric Le Goater, Andrew Jeffery, Joel Stanley,
Igor Mitsyanko, Rob Herring, Subbaraya Sundeep, Alistair Francis,
Felipe Balbi, Niek Linnenbank, Radoslaw Biernacki, Leif Lindholm,
Marcin Juszkiewicz, Alexandre Iooss
Mechanical change using the following coccinelle script:
@@ @@
- first_cpu
+ qemu_get_cpu(0, TYPE_ARM_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/aspeed.c | 5 +++--
hw/arm/bananapi_m2u.c | 3 ++-
hw/arm/boot.c | 12 ++++++------
hw/arm/exynos4_boards.c | 6 ++++--
hw/arm/highbank.c | 3 ++-
hw/arm/microbit.c | 3 ++-
hw/arm/mps2-tz.c | 3 ++-
hw/arm/mps2.c | 3 ++-
hw/arm/msf2-som.c | 3 ++-
hw/arm/musca.c | 3 ++-
hw/arm/netduino2.c | 3 ++-
hw/arm/netduinoplus2.c | 2 +-
hw/arm/olimex-stm32-h405.c | 2 +-
hw/arm/orangepi.c | 3 ++-
hw/arm/realview.c | 5 +++--
hw/arm/sbsa-ref.c | 3 ++-
hw/arm/stellaris.c | 3 ++-
hw/arm/stm32vldiscovery.c | 2 +-
hw/arm/vexpress.c | 3 ++-
hw/arm/virt.c | 17 ++++++++++-------
hw/arm/xilinx_zynq.c | 3 ++-
target/arm/arch_dump.c | 6 +++---
22 files changed, 58 insertions(+), 38 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index f8ba67531a..6a4d87bfe2 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -446,7 +446,8 @@ static void aspeed_machine_init(MachineState *machine)
}
}
- arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
+ arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
+ &aspeed_board_binfo);
}
static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
@@ -1553,7 +1554,7 @@ static void aspeed_minibmc_machine_init(MachineState *machine)
amc->i2c_init(bmc);
}
- armv7m_load_kernel(ARM_CPU(first_cpu),
+ armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
machine->kernel_filename,
0,
AST1030_INTERNAL_FLASH_SIZE);
diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
index 74121d8966..431b1c9bf9 100644
--- a/hw/arm/bananapi_m2u.c
+++ b/hw/arm/bananapi_m2u.c
@@ -127,7 +127,8 @@ static void bpim2u_init(MachineState *machine)
bpim2u_binfo.loader_start = r40->memmap[AW_R40_DEV_SDRAM];
bpim2u_binfo.ram_size = machine->ram_size;
bpim2u_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
- arm_load_kernel(ARM_CPU(first_cpu), machine, &bpim2u_binfo);
+ arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
+ &bpim2u_binfo);
}
static void bpim2u_machine_init(MachineClass *mc)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index f7def3a60c..71c0775984 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -781,7 +781,7 @@ static void do_cpu_reset(void *opaque)
/* Set to non-secure if not a secure boot */
if (!info->secure_boot &&
- (cs != first_cpu || !info->secure_board_setup)) {
+ (cs != qemu_get_cpu(0, TYPE_ARM_CPU) || !info->secure_board_setup)) {
/* Linux expects non-secure state */
env->cp15.scr_el3 |= SCR_NS;
/* Set NSACR.{CP11,CP10} so NS can access the FPU */
@@ -800,7 +800,7 @@ static void do_cpu_reset(void *opaque)
cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw);
}
- if (cs == first_cpu) {
+ if (cs == qemu_get_cpu(0, TYPE_ARM_CPU)) {
AddressSpace *as = arm_boot_address_space(cpu, info);
cpu_set_pc(cs, info->loader_start);
@@ -1187,7 +1187,7 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
}
info->is_linux = is_linux;
- for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+ for (cs = qemu_get_cpu(0, TYPE_ARM_CPU); cs; cs = CPU_NEXT(cs)) {
ARM_CPU(cs)->env.boot_info = info;
}
}
@@ -1264,7 +1264,7 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
* actually loading a kernel, the handler is also responsible for
* arranging that we start it correctly.
*/
- for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+ for (cs = qemu_get_cpu(0, TYPE_ARM_CPU); cs; cs = CPU_NEXT(cs)) {
qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
nb_cpus++;
}
@@ -1325,7 +1325,7 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
}
if (info->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
- for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+ for (cs = qemu_get_cpu(0, TYPE_ARM_CPU); cs; cs = CPU_NEXT(cs)) {
Object *cpuobj = OBJECT(cs);
object_property_set_int(cpuobj, "psci-conduit", info->psci_conduit,
@@ -1335,7 +1335,7 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
* code in do_cpu_reset(), we assume first_cpu is the primary
* CPU.
*/
- if (cs != first_cpu) {
+ if (cs != qemu_get_cpu(0, TYPE_ARM_CPU)) {
object_property_set_bool(cpuobj, "start-powered-off", true,
&error_abort);
}
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index ef5bcbc212..f8cf0588b4 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -136,7 +136,8 @@ static void nuri_init(MachineState *machine)
{
exynos4_boards_init_common(machine, EXYNOS4_BOARD_NURI);
- arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo);
+ arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
+ &exynos4_board_binfo);
}
static void smdkc210_init(MachineState *machine)
@@ -146,7 +147,8 @@ static void smdkc210_init(MachineState *machine)
lan9215_init(SMDK_LAN9118_BASE_ADDR,
qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
- arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo);
+ arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
+ &exynos4_board_binfo);
}
static void nuri_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index f12aacea6b..393fa8a468 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -328,7 +328,8 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
highbank_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
- arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo);
+ arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
+ &highbank_binfo);
}
static void highbank_init(MachineState *machine)
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index 50df362088..19c2fc3b8e 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -56,7 +56,8 @@ static void microbit_init(MachineState *machine)
memory_region_add_subregion_overlap(&s->nrf51.container, NRF51_TWI_BASE,
mr, -1);
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
+ machine->kernel_filename,
0, s->nrf51.flash_size);
}
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index eae3639da2..0b26eab45d 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -1217,7 +1217,8 @@ static void mps2tz_common_init(MachineState *machine)
mms->remap_irq);
}
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
+ machine->kernel_filename,
0, boot_ram_size(mms));
}
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index d92fd60684..86e5ca0ce6 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -462,7 +462,8 @@ static void mps2_common_init(MachineState *machine)
qdev_get_gpio_in(armv7m,
mmc->fpga_type == FPGA_AN511 ? 47 : 13));
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
+ machine->kernel_filename,
0, 0x400000);
}
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 7b3106c790..42a3eb4905 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -100,7 +100,8 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
+ machine->kernel_filename,
0, soc->envm_size);
}
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index 6eeee57c9d..8d9b93d931 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -597,7 +597,8 @@ static void musca_init(MachineState *machine)
"cfg_sec_resp", 0));
}
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
+ machine->kernel_filename,
0, 0x2000000);
}
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index 83753d53a3..61fe0346fe 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -48,7 +48,8 @@ static void netduino2_init(MachineState *machine)
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
+ machine->kernel_filename,
0, FLASH_SIZE);
}
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index 515c081605..ad68421b97 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -48,7 +48,7 @@ static void netduinoplus2_init(MachineState *machine)
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- armv7m_load_kernel(ARM_CPU(first_cpu),
+ armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
machine->kernel_filename,
0, FLASH_SIZE);
}
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
index 3aa61c91b7..a44c6188c4 100644
--- a/hw/arm/olimex-stm32-h405.c
+++ b/hw/arm/olimex-stm32-h405.c
@@ -51,7 +51,7 @@ static void olimex_stm32_h405_init(MachineState *machine)
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- armv7m_load_kernel(ARM_CPU(first_cpu),
+ armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
machine->kernel_filename,
0, FLASH_SIZE);
}
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index 10653361ed..7d44715111 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -105,7 +105,8 @@ static void orangepi_init(MachineState *machine)
orangepi_binfo.loader_start = h3->memmap[AW_H3_DEV_SDRAM];
orangepi_binfo.ram_size = machine->ram_size;
orangepi_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
- arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
+ arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
+ &orangepi_binfo);
}
static void orangepi_machine_init(MachineClass *mc)
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 8f89526596..be709146c8 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -136,7 +136,7 @@ static void realview_init(MachineState *machine,
cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
}
- cpu = ARM_CPU(first_cpu);
+ cpu = ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU));
env = &cpu->env;
if (arm_feature(env, ARM_FEATURE_V7)) {
if (is_mpcore) {
@@ -384,7 +384,8 @@ static void realview_init(MachineState *machine,
realview_binfo.ram_size = ram_size;
realview_binfo.board_id = realview_board_id[board_type];
realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
- arm_load_kernel(ARM_CPU(first_cpu), machine, &realview_binfo);
+ arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
+ &realview_binfo);
}
static void realview_eb_init(MachineState *machine)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index a85004809f..01c948725c 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -844,7 +844,8 @@ static void sbsa_ref_init(MachineState *machine)
sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
sms->bootinfo.get_dtb = sbsa_ref_dtb;
sms->bootinfo.firmware_loaded = firmware_loaded;
- arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo);
+ arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
+ &sms->bootinfo);
}
static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index aa5b0ddfaa..0920b9cb86 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1307,7 +1307,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
- armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size);
+ armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
+ ms->kernel_filename, 0, flash_size);
}
/* FIXME: Figure out how to generate these from stellaris_boards. */
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index 67675e952f..2df943295b 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -51,7 +51,7 @@ static void stm32vldiscovery_init(MachineState *machine)
qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- armv7m_load_kernel(ARM_CPU(first_cpu),
+ armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
machine->kernel_filename,
0, FLASH_SIZE);
}
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index e20d865d5a..8107a7057a 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -712,7 +712,8 @@ static void vexpress_common_init(MachineState *machine)
daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
/* When booting Linux we should be in secure state if the CPU has one. */
daughterboard->bootinfo.secure_boot = vms->secure;
- arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo);
+ arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
+ &daughterboard->bootinfo);
}
static bool vexpress_get_secure(Object *obj, Error **errp)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index da5b738f0a..9f69be85ce 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -605,7 +605,7 @@ static void fdt_add_gic_node(VirtMachineState *vms)
static void fdt_add_pmu_nodes(const VirtMachineState *vms)
{
- ARMCPU *armcpu = ARM_CPU(first_cpu);
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU));
uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
MachineState *ms = MACHINE(vms);
@@ -1652,7 +1652,7 @@ void virt_machine_done(Notifier *notifier, void *data)
VirtMachineState *vms = container_of(notifier, VirtMachineState,
machine_done);
MachineState *ms = MACHINE(vms);
- ARMCPU *cpu = ARM_CPU(first_cpu);
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU));
struct arm_boot_info *info = &vms->bootinfo;
AddressSpace *as = arm_boot_address_space(cpu, info);
@@ -1957,9 +1957,11 @@ static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
bool aarch64, pmu, steal_time;
CPUState *cpu;
- aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
- pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
- steal_time = object_property_get_bool(OBJECT(first_cpu),
+ aarch64 = object_property_get_bool(OBJECT(qemu_get_cpu(0, TYPE_ARM_CPU)),
+ "aarch64", NULL);
+ pmu = object_property_get_bool(OBJECT(qemu_get_cpu(0, TYPE_ARM_CPU)),
+ "pmu", NULL);
+ steal_time = object_property_get_bool(OBJECT(qemu_get_cpu(0, TYPE_ARM_CPU)),
"kvm-steal-time", NULL);
if (kvm_enabled()) {
@@ -2001,7 +2003,7 @@ static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
} else {
if (aarch64 && vms->highmem) {
int requested_pa_size = 64 - clz64(vms->highest_gpa);
- int pamax = arm_pamax(ARM_CPU(first_cpu));
+ int pamax = arm_pamax(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)));
if (pamax < requested_pa_size) {
error_report("VCPU supports less PA bits (%d) than "
@@ -2324,7 +2326,8 @@ static void machvirt_init(MachineState *machine)
vms->bootinfo.skip_dtb_autoload = true;
vms->bootinfo.firmware_loaded = firmware_loaded;
vms->bootinfo.psci_conduit = vms->psci_conduit;
- arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
+ arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
+ &vms->bootinfo);
vms->machine_done.notify = virt_machine_done;
qemu_add_machine_init_done_notifier(&vms->machine_done);
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 8dc2ea83a9..90a052b841 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -349,7 +349,8 @@ static void zynq_init(MachineState *machine)
zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
zynq_binfo.write_board_setup = zynq_write_board_setup;
- arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo);
+ arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
+ &zynq_binfo);
}
static void zynq_machine_class_init(ObjectClass *oc, void *data)
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
index 2d8e41ab8a..25dffccb99 100644
--- a/target/arm/arch_dump.c
+++ b/target/arm/arch_dump.c
@@ -395,11 +395,11 @@ int cpu_get_dump_info(ArchDumpInfo *info,
GuestPhysBlock *block;
hwaddr lowest_addr = ULLONG_MAX;
- if (first_cpu == NULL) {
+ if (qemu_get_cpu(0, TYPE_ARM_CPU) == NULL) {
return -1;
}
- cpu = ARM_CPU(first_cpu);
+ cpu = ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU));
env = &cpu->env;
/* Take a best guess at the phys_base. If we get it wrong then crash
@@ -443,7 +443,7 @@ int cpu_get_dump_info(ArchDumpInfo *info,
ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
{
- ARMCPU *cpu = ARM_CPU(first_cpu);
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU));
size_t note_size;
if (class == ELFCLASS64) {
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 11/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_POWERPC_CPU)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 10/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_ARM_CPU) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 12/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_MIPS_CPU) Philippe Mathieu-Daudé
` (8 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Nicholas Piggin, Daniel Henrique Barboza, Cédric Le Goater,
Hervé Poussineau, David Gibson, Harsh Prateek Bora,
Alexey Kardashevskiy
Mechanical change using the following coccinelle script:
@@ @@
- first_cpu
+ qemu_get_cpu(0, TYPE_POWERPC_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/ppc/e500.c | 2 +-
hw/ppc/ppc.c | 4 ++--
hw/ppc/prep_systemio.c | 2 +-
hw/ppc/spapr.c | 11 ++++++-----
hw/ppc/spapr_caps.c | 10 +++++-----
hw/ppc/spapr_rtas.c | 2 +-
hw/ppc/spapr_vof.c | 2 +-
hw/ppc/vof.c | 3 ++-
target/ppc/arch_dump.c | 4 ++--
9 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index c4bf3fef32..02d14404d9 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -373,7 +373,7 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
MachineState *machine = MACHINE(pms);
unsigned int smp_cpus = machine->smp.cpus;
const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
- CPUPPCState *env = cpu_env(first_cpu);
+ CPUPPCState *env = cpu_env(qemu_get_cpu(0, TYPE_POWERPC_CPU));
int ret = -1;
uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };
int fdt_size;
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index be167710a3..be0b1536f5 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -970,7 +970,7 @@ void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value)
static void timebase_save(PPCTimebase *tb)
{
uint64_t ticks = cpu_get_host_ticks();
- PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
+ PowerPCCPU *first_ppc_cpu = POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU));
if (!first_ppc_cpu->env.tb_env) {
error_report("No timebase object");
@@ -998,7 +998,7 @@ static void timebase_save(PPCTimebase *tb)
static void timebase_load(PPCTimebase *tb)
{
CPUState *cpu;
- PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
+ PowerPCCPU *first_ppc_cpu = POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU));
int64_t tb_off_adj, tb_off;
unsigned long freq;
diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c
index c96cefb13d..0431cde91c 100644
--- a/hw/ppc/prep_systemio.c
+++ b/hw/ppc/prep_systemio.c
@@ -261,7 +261,7 @@ static void prep_systemio_realize(DeviceState *dev, Error **errp)
s->iomap_type = PORT0850_IOMAP_NONCONTIGUOUS;
qemu_set_irq(s->non_contiguous_io_map_irq,
s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS);
- cpu = POWERPC_CPU(first_cpu);
+ cpu = POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU));
s->softreset_irq = qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_HRESET);
isa_register_portio_list(isa, &s->portio, 0x0, ppc_io800_port_list, s,
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index cb840676d3..a5006eaa5e 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -981,7 +981,7 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt,
int chosen)
{
- PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
+ PowerPCCPU *first_ppc_cpu = POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU));
char val[2 * 4] = {
23, 0x00, /* XICS / XIVE mode */
@@ -1125,7 +1125,7 @@ static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
* Older KVM versions with older guest kernels were broken
* with the magic page, don't allow the guest to map it.
*/
- if (!kvmppc_get_hypercall(cpu_env(first_cpu), hypercall,
+ if (!kvmppc_get_hypercall(cpu_env(qemu_get_cpu(0, TYPE_POWERPC_CPU)), hypercall,
sizeof(hypercall))) {
_FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
hypercall, sizeof(hypercall)));
@@ -1669,7 +1669,7 @@ static void spapr_machine_reset(MachineState *machine, ShutdownCause reason)
pef_kvm_reset(machine->cgs, &error_fatal);
spapr_caps_apply(spapr);
- first_ppc_cpu = POWERPC_CPU(first_cpu);
+ first_ppc_cpu = POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU));
if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
spapr->max_compat_pvr)) {
@@ -1845,7 +1845,7 @@ static int spapr_post_load(void *opaque, int version_id)
}
if (kvm_enabled() && spapr->patb_entry) {
- PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
+ PowerPCCPU *cpu = POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU));
bool radix = !!(spapr->patb_entry & PATE1_GR);
bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
@@ -4014,7 +4014,8 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev)
*/
if (hotplugged) {
for (i = 0; i < cc->nr_threads; i++) {
- ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr,
+ ppc_set_compat(core->threads[i],
+ POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU))->compat_pvr,
&error_abort);
}
}
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index 5a0755d34f..0c1f00d869 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -194,7 +194,7 @@ static void cap_htm_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
{
ERRP_GUARD();
- PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
+ PowerPCCPU *cpu = POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU));
CPUPPCState *env = &cpu->env;
if (!val) {
@@ -213,7 +213,7 @@ static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
{
ERRP_GUARD();
- PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
+ PowerPCCPU *cpu = POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU));
CPUPPCState *env = &cpu->env;
if (!val) {
@@ -440,7 +440,7 @@ static void cap_nested_kvm_hv_apply(SpaprMachineState *spapr,
uint8_t val, Error **errp)
{
ERRP_GUARD();
- PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
+ PowerPCCPU *cpu = POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU));
CPUPPCState *env = &cpu->env;
if (!val) {
@@ -494,7 +494,7 @@ static void cap_large_decr_apply(SpaprMachineState *spapr,
uint8_t val, Error **errp)
{
ERRP_GUARD();
- PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
+ PowerPCCPU *cpu = POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU));
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
if (!val) {
@@ -632,7 +632,7 @@ static void cap_ail_mode_3_apply(SpaprMachineState *spapr,
uint8_t val, Error **errp)
{
ERRP_GUARD();
- PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
+ PowerPCCPU *cpu = POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU));
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
if (!val) {
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 7df21581c2..3d4e93a188 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -539,7 +539,7 @@ uint64_t qtest_rtas_call(char *cmd, uint32_t nargs, uint64_t args,
for (token = 0; token < RTAS_TOKEN_MAX - RTAS_TOKEN_BASE; token++) {
if (strcmp(cmd, rtas_table[token].name) == 0) {
SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
- PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
+ PowerPCCPU *cpu = POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU));
rtas_table[token].fn(cpu, spapr, token + RTAS_TOKEN_BASE,
nargs, args, nret, rets);
diff --git a/hw/ppc/spapr_vof.c b/hw/ppc/spapr_vof.c
index 09f29be0b9..301b3cd433 100644
--- a/hw/ppc/spapr_vof.c
+++ b/hw/ppc/spapr_vof.c
@@ -58,7 +58,7 @@ void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp)
{
target_ulong stack_ptr;
Vof *vof = spapr->vof;
- PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
+ PowerPCCPU *first_ppc_cpu = POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU));
vof_init(vof, spapr->rma_size, errp);
diff --git a/hw/ppc/vof.c b/hw/ppc/vof.c
index e3b430a81f..9fa1cd9e19 100644
--- a/hw/ppc/vof.c
+++ b/hw/ppc/vof.c
@@ -797,7 +797,8 @@ static uint32_t vof_call_method(MachineState *ms, Vof *vof, uint32_t methodaddr,
VofMachineIfClass *vmc = VOF_MACHINE_GET_CLASS(vmo);
g_assert(vmc->client_architecture_support);
- ret = (uint32_t)vmc->client_architecture_support(ms, first_cpu,
+ ret = (uint32_t)vmc->client_architecture_support(ms,
+ qemu_get_cpu(0, TYPE_POWERPC_CPU),
param1);
}
diff --git a/target/ppc/arch_dump.c b/target/ppc/arch_dump.c
index a8315659d9..be2a78d01f 100644
--- a/target/ppc/arch_dump.c
+++ b/target/ppc/arch_dump.c
@@ -228,11 +228,11 @@ int cpu_get_dump_info(ArchDumpInfo *info,
{
PowerPCCPU *cpu;
- if (first_cpu == NULL) {
+ if (qemu_get_cpu(0, TYPE_POWERPC_CPU) == NULL) {
return -1;
}
- cpu = POWERPC_CPU(first_cpu);
+ cpu = POWERPC_CPU(qemu_get_cpu(0, TYPE_POWERPC_CPU));
info->d_machine = PPC_ELF_MACHINE;
info->d_class = ELFCLASS;
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 12/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_MIPS_CPU)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 11/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_POWERPC_CPU) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 13/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_M68K_CPU) Philippe Mathieu-Daudé
` (7 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Huacai Chen, Jiaxun Yang, Aurelien Jarno, Aleksandar Rikalo
Mechanical change using the following coccinelle script:
@@ @@
- first_cpu
+ qemu_get_cpu(0, TYPE_MIPS_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/internal.h | 2 +-
hw/intc/mips_gic.c | 2 +-
hw/mips/bootloader.c | 3 ++-
hw/mips/cps.c | 5 +++--
hw/mips/loongson3_bootp.c | 2 +-
hw/mips/loongson3_virt.c | 7 ++++---
hw/mips/malta.c | 2 +-
hw/misc/mips_cpc.c | 4 ++--
target/mips/tcg/sysemu/cp0_helper.c | 8 ++++----
target/mips/tcg/sysemu/tlb_helper.c | 2 +-
10 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 1d0c026c7d..d373063fd0 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -270,7 +270,7 @@ static inline int mips_vpe_active(CPUMIPSState *env)
static inline int mips_vp_active(CPUMIPSState *env)
{
- CPUState *other_cs = first_cpu;
+ CPUState *other_cs = qemu_get_cpu(0, TYPE_MIPS_CPU);
/* Check if the VP disabled other VPs (which means the VP is enabled) */
if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c
index 77ba7348a3..4c4791aefa 100644
--- a/hw/intc/mips_gic.c
+++ b/hw/intc/mips_gic.c
@@ -406,7 +406,7 @@ static void mips_gic_init(Object *obj)
static void mips_gic_realize(DeviceState *dev, Error **errp)
{
MIPSGICState *s = MIPS_GIC(dev);
- CPUState *cs = first_cpu;
+ CPUState *cs = qemu_get_cpu(0, TYPE_MIPS_CPU);
int i;
if (s->num_vps > GIC_MAX_VPS) {
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 1dd6ef2096..c4943f193f 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -51,7 +51,8 @@ typedef enum bl_reg {
static bool bootcpu_supports_isa(uint64_t isa_mask)
{
- return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask);
+ return cpu_supports_isa(&MIPS_CPU(qemu_get_cpu(0, TYPE_MIPS_CPU))->env,
+ isa_mask);
}
static void st_nm32_p(void **ptr, uint32_t insn)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 2b5269ebf1..d2f72cbf90 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -107,7 +107,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
if (itu_present) {
object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU);
object_property_set_link(OBJECT(&s->itu), "cpu[0]",
- OBJECT(first_cpu), &error_abort);
+ OBJECT(qemu_get_cpu(0, TYPE_MIPS_CPU)),
+ &error_abort);
object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16,
&error_abort);
object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16,
@@ -147,7 +148,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
/* Global Configuration Registers */
- gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4;
+ gcr_base = MIPS_CPU(qemu_get_cpu(0, TYPE_MIPS_CPU))->env.CP0_CMGCRBase << 4;
object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR);
object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp,
diff --git a/hw/mips/loongson3_bootp.c b/hw/mips/loongson3_bootp.c
index f99af22932..3ad9cf2f0c 100644
--- a/hw/mips/loongson3_bootp.c
+++ b/hw/mips/loongson3_bootp.c
@@ -32,7 +32,7 @@ static void init_cpu_info(void *g_cpuinfo, uint64_t cpu_freq)
struct efi_cpuinfo_loongson *c = g_cpuinfo;
c->cputype = cpu_to_le32(Loongson_3A);
- c->processor_id = cpu_to_le32(MIPS_CPU(first_cpu)->env.CP0_PRid);
+ c->processor_id = cpu_to_le32(MIPS_CPU(qemu_get_cpu(0, TYPE_MIPS_CPU))->env.CP0_PRid);
if (cpu_freq > UINT_MAX) {
c->cpu_clock_freq = cpu_to_le32(UINT_MAX);
} else {
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
index b74b358874..9dd943d477 100644
--- a/hw/mips/loongson3_virt.c
+++ b/hw/mips/loongson3_virt.c
@@ -159,7 +159,8 @@ static uint64_t get_cpu_freq_hz(void)
};
if (kvm_enabled()) {
- ret = kvm_vcpu_ioctl(first_cpu, KVM_GET_ONE_REG, &freq_reg);
+ ret = kvm_vcpu_ioctl(qemu_get_cpu(0, TYPE_MIPS_CPU), KVM_GET_ONE_REG,
+ &freq_reg);
if (ret >= 0) {
return freq * 2;
}
@@ -387,7 +388,7 @@ static void main_cpu_reset(void *opaque)
/* Loongson-3 reset stuff */
if (loaderparams.kernel_filename) {
- if (cpu == MIPS_CPU(first_cpu)) {
+ if (cpu == MIPS_CPU(qemu_get_cpu(0, TYPE_MIPS_CPU))) {
env->active_tc.gpr[4] = loaderparams.a0;
env->active_tc.gpr[5] = loaderparams.a1;
env->active_tc.gpr[6] = loaderparams.a2;
@@ -543,7 +544,7 @@ static void mips_loongson3_virt_init(MachineState *machine)
pin, cpu->env.irq[ip + 2]);
}
}
- env = &MIPS_CPU(first_cpu)->env;
+ env = &MIPS_CPU(qemu_get_cpu(0, TYPE_MIPS_CPU))->env;
/* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */
memory_region_init_rom(bios, NULL, "loongson3.bios",
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index dac27fad9d..2e26b8a26d 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1044,7 +1044,7 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
qemu_register_reset(main_cpu_reset, cpu);
}
- cpu = MIPS_CPU(first_cpu);
+ cpu = MIPS_CPU(qemu_get_cpu(0, TYPE_MIPS_CPU));
env = &cpu->env;
*i8259_irq = env->irq[2];
*cbus_irq = env->irq[4];
diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c
index 4a94c87054..583081cdeb 100644
--- a/hw/misc/mips_cpc.c
+++ b/hw/misc/mips_cpc.c
@@ -44,7 +44,7 @@ static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data)
static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
{
- CPUState *cs = first_cpu;
+ CPUState *cs = qemu_get_cpu(0, TYPE_MIPS_CPU);
CPU_FOREACH(cs) {
uint64_t i = 1ULL << cs->cpu_index;
@@ -62,7 +62,7 @@ static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
{
- CPUState *cs = first_cpu;
+ CPUState *cs = qemu_get_cpu(0, TYPE_MIPS_CPU);
CPU_FOREACH(cs) {
uint64_t i = 1ULL << cs->cpu_index;
diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c
index af0cd60829..bf934be58a 100644
--- a/target/mips/tcg/sysemu/cp0_helper.c
+++ b/target/mips/tcg/sysemu/cp0_helper.c
@@ -1633,7 +1633,7 @@ target_ulong helper_emt(void)
target_ulong helper_dvpe(CPUMIPSState *env)
{
- CPUState *other_cs = first_cpu;
+ CPUState *other_cs = qemu_get_cpu(0, TYPE_MIPS_CPU);
target_ulong prev = env->mvp->CP0_MVPControl;
CPU_FOREACH(other_cs) {
@@ -1649,7 +1649,7 @@ target_ulong helper_dvpe(CPUMIPSState *env)
target_ulong helper_evpe(CPUMIPSState *env)
{
- CPUState *other_cs = first_cpu;
+ CPUState *other_cs = qemu_get_cpu(0, TYPE_MIPS_CPU);
target_ulong prev = env->mvp->CP0_MVPControl;
CPU_FOREACH(other_cs) {
@@ -1669,7 +1669,7 @@ target_ulong helper_evpe(CPUMIPSState *env)
/* R6 Multi-threading */
target_ulong helper_dvp(CPUMIPSState *env)
{
- CPUState *other_cs = first_cpu;
+ CPUState *other_cs = qemu_get_cpu(0, TYPE_MIPS_CPU);
target_ulong prev = env->CP0_VPControl;
if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
@@ -1687,7 +1687,7 @@ target_ulong helper_dvp(CPUMIPSState *env)
target_ulong helper_evp(CPUMIPSState *env)
{
- CPUState *other_cs = first_cpu;
+ CPUState *other_cs = qemu_get_cpu(0, TYPE_MIPS_CPU);
target_ulong prev = env->CP0_VPControl;
if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index 7dbc2e24c4..2d31c8e17f 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -344,7 +344,7 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type)
uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1);
uint8_t invMsgR = 0;
uint32_t invMsgMMid = env->CP0_MemoryMapID;
- CPUState *other_cs = first_cpu;
+ CPUState *other_cs = qemu_get_cpu(0, TYPE_MIPS_CPU);
#ifdef TARGET_MIPS64
invMsgR = extract64(arg, 62, 2);
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 13/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_M68K_CPU)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 12/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_MIPS_CPU) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 14/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_S390X_CPU) Philippe Mathieu-Daudé
` (6 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Laurent Vivier
Mechanical change using the following coccinelle script:
@@ @@
- first_cpu
+ qemu_get_cpu(0, TYPE_M68K_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/intc/m68k_irqc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/m68k_irqc.c b/hw/intc/m68k_irqc.c
index 0c515e4ecb..071937e6eb 100644
--- a/hw/intc/m68k_irqc.c
+++ b/hw/intc/m68k_irqc.c
@@ -35,7 +35,7 @@ static void m68k_irqc_print_info(InterruptStatsProvider *obj, Monitor *mon)
static void m68k_set_irq(void *opaque, int irq, int level)
{
M68KIRQCState *s = opaque;
- M68kCPU *cpu = M68K_CPU(first_cpu);
+ M68kCPU *cpu = M68K_CPU(qemu_get_cpu(0, TYPE_M68K_CPU));
int i;
if (level) {
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 14/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_S390X_CPU)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 13/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_M68K_CPU) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 15/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RISCV_CPU) Philippe Mathieu-Daudé
` (5 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Christian Borntraeger, David Hildenbrand, Ilya Leoshkevich,
Halil Pasic, Eric Farman
Mechanical change using the following coccinelle script:
@@ @@
- first_cpu
+ qemu_get_cpu(0, TYPE_S390_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/s390x/ipl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c
index 377f43416c..1f2296f456 100644
--- a/hw/s390x/ipl.c
+++ b/hw/s390x/ipl.c
@@ -674,7 +674,7 @@ void s390_ipl_get_reset_request(CPUState **cs, enum s390_reset *reset_type)
*cs = qemu_get_cpu(ipl->reset_cpu_index, TYPE_S390_CPU);
if (!*cs) {
/* use any CPU */
- *cs = first_cpu;
+ *cs = qemu_get_cpu(0, TYPE_S390_CPU);
}
*reset_type = ipl->reset_type;
}
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 15/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RISCV_CPU)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 14/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_S390X_CPU) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 16/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_TRICORE_CPU) Philippe Mathieu-Daudé
` (4 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Palmer Dabbelt, Bin Meng, Weiwei Li, Daniel Henrique Barboza,
Liu Zhiwei
Mechanical change using the following coccinelle script:
@@ @@
- first_cpu
+ qemu_get_cpu(0, TYPE_RISCV_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/riscv/boot.c | 2 +-
target/riscv/arch_dump.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 1d004660d4..5e979f7b6a 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -437,7 +437,7 @@ void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)
{
CPUState *cs;
- for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+ for (cs = qemu_get_cpu(0, TYPE_RISCV_CPU); cs; cs = CPU_NEXT(cs)) {
RISCVCPU *riscv_cpu = RISCV_CPU(cs);
riscv_cpu->env.kernel_addr = kernel_addr;
riscv_cpu->env.fdt_addr = fdt_addr;
diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c
index 434c8a3dbb..4813d1ac1f 100644
--- a/target/riscv/arch_dump.c
+++ b/target/riscv/arch_dump.c
@@ -167,10 +167,10 @@ int cpu_get_dump_info(ArchDumpInfo *info,
RISCVCPU *cpu;
CPURISCVState *env;
- if (first_cpu == NULL) {
+ if (qemu_get_cpu(0, TYPE_RISCV_CPU) == NULL) {
return -1;
}
- cpu = RISCV_CPU(first_cpu);
+ cpu = RISCV_CPU(qemu_get_cpu(0, TYPE_RISCV_CPU));
env = &cpu->env;
info->d_machine = EM_RISCV;
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 16/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_TRICORE_CPU)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 15/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RISCV_CPU) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 17/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_SUPERH_CPU) Philippe Mathieu-Daudé
` (3 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Bastian Koppelmann
Mechanical change using the following coccinelle script:
@@ @@
- first_cpu
+ qemu_get_cpu(0, TYPE_TRICORE_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/tricore/triboard.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/tricore/triboard.c b/hw/tricore/triboard.c
index 4dba0259cd..1fe6692f97 100644
--- a/hw/tricore/triboard.c
+++ b/hw/tricore/triboard.c
@@ -46,7 +46,7 @@ static void tricore_load_kernel(const char *kernel_filename)
error_report("no kernel file '%s'", kernel_filename);
exit(1);
}
- cpu = TRICORE_CPU(first_cpu);
+ cpu = TRICORE_CPU(qemu_get_cpu(0, TYPE_TRICORE_CPU));
env = &cpu->env;
env->PC = entry;
}
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 17/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_SUPERH_CPU)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 16/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_TRICORE_CPU) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 18/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RX_CPU) Philippe Mathieu-Daudé
` (2 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Yoshinori Sato, Magnus Damm
Mechanical change using the following coccinelle script:
@@ @@
- first_cpu
+ qemu_get_cpu(0, TYPE_SUPERH_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/intc/sh_intc.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/intc/sh_intc.c b/hw/intc/sh_intc.c
index c9b0b0c1ec..be76a96ebc 100644
--- a/hw/intc/sh_intc.c
+++ b/hw/intc/sh_intc.c
@@ -44,12 +44,14 @@ void sh_intc_toggle_source(struct intc_source *source,
if (source->pending) {
source->parent->pending++;
if (source->parent->pending == 1) {
- cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
+ cpu_interrupt(qemu_get_cpu(0, TYPE_SUPERH_CPU),
+ CPU_INTERRUPT_HARD);
}
} else {
source->parent->pending--;
if (source->parent->pending == 0) {
- cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(qemu_get_cpu(0, TYPE_SUPERH_CPU),
+ CPU_INTERRUPT_HARD);
}
}
}
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 18/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RX_CPU)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 17/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_SUPERH_CPU) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 19/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_X86_CPU) Philippe Mathieu-Daudé
2023-10-23 13:59 ` [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Zhao Liu
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Yoshinori Sato
Mechanical change using the following coccinelle script:
@@ @@
- first_cpu
+ qemu_get_cpu(0, TYPE_RX_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/rx/rx-gdbsim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c
index 47c17026c7..091f83cc60 100644
--- a/hw/rx/rx-gdbsim.c
+++ b/hw/rx/rx-gdbsim.c
@@ -126,7 +126,7 @@ static void rx_gdbsim_init(MachineState *machine)
* the latter half of the SDRAM space.
*/
kernel_offset = machine->ram_size / 2;
- rx_load_image(RX_CPU(first_cpu), kernel_filename,
+ rx_load_image(RX_CPU(qemu_get_cpu(0, TYPE_RX_CPU)), kernel_filename,
SDRAM_BASE + kernel_offset, kernel_offset);
if (dtb_filename) {
ram_addr_t dtb_offset;
@@ -152,7 +152,7 @@ static void rx_gdbsim_init(MachineState *machine)
qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
rom_ptr(SDRAM_BASE + dtb_offset, dtb_size));
/* Set dtb address to R1 */
- RX_CPU(first_cpu)->env.regs[1] = SDRAM_BASE + dtb_offset;
+ RX_CPU(qemu_get_cpu(0, TYPE_RX_CPU))->env.regs[1] = SDRAM_BASE + dtb_offset;
}
}
}
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 19/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_X86_CPU)
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (17 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 18/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RX_CPU) Philippe Mathieu-Daudé
@ 2023-10-20 16:36 ` Philippe Mathieu-Daudé
2023-10-23 13:59 ` [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Zhao Liu
19 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 16:36 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Philippe Mathieu-Daudé,
Marcel Apfelbaum, Sergio Lopez, Marcelo Tosatti, kvm
Mechanical change using the following coccinelle script:
@@ @@
- first_cpu
+ qemu_get_cpu(0, TYPE_X86_CPU)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/i386/kvm/clock.c | 4 ++--
hw/i386/kvmvapic.c | 3 ++-
hw/i386/microvm.c | 2 +-
hw/i386/pc.c | 7 ++++---
hw/i386/pc_piix.c | 3 ++-
hw/i386/x86.c | 2 +-
hw/isa/lpc_ich9.c | 2 +-
target/i386/arch_dump.c | 6 +++---
target/i386/kvm/kvm.c | 6 +++---
target/i386/tcg/sysemu/fpu_helper.c | 4 ++--
10 files changed, 21 insertions(+), 18 deletions(-)
diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c
index f25977d3f6..00067adde3 100644
--- a/hw/i386/kvm/clock.c
+++ b/hw/i386/kvm/clock.c
@@ -65,7 +65,7 @@ struct pvclock_vcpu_time_info {
static uint64_t kvmclock_current_nsec(KVMClockState *s)
{
- CPUState *cpu = first_cpu;
+ CPUState *cpu = qemu_get_cpu(0, TYPE_X86_CPU);
CPUX86State *env = cpu_env(cpu);
hwaddr kvmclock_struct_pa;
uint64_t migration_tsc = env->tsc;
@@ -330,7 +330,7 @@ static const TypeInfo kvmclock_info = {
/* Note: Must be called after VCPU initialization. */
void kvmclock_create(bool create_always)
{
- X86CPU *cpu = X86_CPU(first_cpu);
+ X86CPU *cpu = X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU));
assert(kvm_enabled());
if (!kvm_has_adjust_clock()) {
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 43f8a8f679..e10c2bfc5a 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -760,7 +760,8 @@ static void kvmvapic_vm_state_change(void *opaque, bool running,
if (s->state == VAPIC_ACTIVE) {
if (ms->smp.cpus == 1) {
- run_on_cpu(first_cpu, do_vapic_enable, RUN_ON_CPU_HOST_PTR(s));
+ run_on_cpu(qemu_get_cpu(0, TYPE_X86_CPU), do_vapic_enable,
+ RUN_ON_CPU_HOST_PTR(s));
} else {
zero = g_malloc0(s->rom_state.vapic_size);
cpu_physical_memory_write(s->vapic_paddr, zero,
diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
index b9c93039e2..d043f71992 100644
--- a/hw/i386/microvm.c
+++ b/hw/i386/microvm.c
@@ -229,7 +229,7 @@ static void microvm_devices_init(MicrovmMachineState *mms)
if (x86_machine_is_acpi_enabled(x86ms) && mms->pcie == ON_OFF_AUTO_ON) {
/* use topmost 25% of the address space available */
- hwaddr phys_size = (hwaddr)1 << X86_CPU(first_cpu)->phys_bits;
+ hwaddr phys_size = (hwaddr)1 << X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU))->phys_bits;
if (phys_size > 0x1000000ll) {
mms->gpex.mmio64.size = phys_size / 4;
mms->gpex.mmio64.base = phys_size - mms->gpex.mmio64.size;
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index bb3854d1d0..7f10078096 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -813,7 +813,7 @@ static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
{
- X86CPU *cpu = X86_CPU(first_cpu);
+ X86CPU *cpu = X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU));
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
MachineState *ms = MACHINE(pcms);
@@ -898,7 +898,7 @@ void pc_memory_init(PCMachineState *pcms,
X86MachineState *x86ms = X86_MACHINE(pcms);
hwaddr maxphysaddr, maxusedaddr;
hwaddr cxl_base, cxl_resv_end = 0;
- X86CPU *cpu = X86_CPU(first_cpu);
+ X86CPU *cpu = X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU));
assert(machine->ram_size == x86ms->below_4g_mem_size +
x86ms->above_4g_mem_size);
@@ -1182,7 +1182,8 @@ static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
}
port92 = isa_create_simple(isa_bus, TYPE_PORT92);
- a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
+ a20_line = qemu_allocate_irqs(handle_a20_line_change,
+ qemu_get_cpu(0, TYPE_X86_CPU), 2);
i8042_setup_a20_line(i8042, a20_line[0]);
qdev_connect_gpio_out_named(DEVICE(port92),
PORT92_A20_LINE, 0, a20_line[1]);
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index e36a3262b2..1e0c2bb2e3 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -363,7 +363,8 @@ static void pc_init1(MachineState *machine,
if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
PCIDevice *piix4_pm;
- smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
+ smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt,
+ qemu_get_cpu(0, TYPE_X86_CPU), 0);
piix4_pm = pci_new(piix3_devfn + 3, TYPE_PIIX4_PM);
qdev_prop_set_uint32(DEVICE(piix4_pm), "smb_io_base", 0xb100);
qdev_prop_set_bit(DEVICE(piix4_pm), "smm-enabled",
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index b3d054889b..ef7949ac42 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -538,7 +538,7 @@ uint64_t cpu_get_tsc(CPUX86State *env)
/* IRQ handling */
static void pic_irq_request(void *opaque, int irq, int level)
{
- CPUState *cs = first_cpu;
+ CPUState *cs = qemu_get_cpu(0, TYPE_X86_CPU);
X86CPU *cpu = X86_CPU(cs);
trace_x86_pic_interrupt(irq, level);
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 3f59980aa0..0b9c37e0bf 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -327,7 +327,7 @@ static PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
void ich9_generate_smi(void)
{
- cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
+ cpu_interrupt(qemu_get_cpu(0, TYPE_X86_CPU), CPU_INTERRUPT_SMI);
}
/* Returns -1 on error, IRQ number on success */
diff --git a/target/i386/arch_dump.c b/target/i386/arch_dump.c
index c290910a04..c167f893db 100644
--- a/target/i386/arch_dump.c
+++ b/target/i386/arch_dump.c
@@ -185,7 +185,7 @@ int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
X86CPU *cpu = X86_CPU(cs);
int ret;
#ifdef TARGET_X86_64
- X86CPU *first_x86_cpu = X86_CPU(first_cpu);
+ X86CPU *first_x86_cpu = X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU));
bool lma = !!(first_x86_cpu->env.hflags & HF_LMA_MASK);
if (lma) {
@@ -401,8 +401,8 @@ int cpu_get_dump_info(ArchDumpInfo *info,
GuestPhysBlock *block;
#ifdef TARGET_X86_64
- X86CPU *first_x86_cpu = X86_CPU(first_cpu);
- lma = first_cpu && (first_x86_cpu->env.hflags & HF_LMA_MASK);
+ X86CPU *first_x86_cpu = X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU));
+ lma = qemu_get_cpu(0, TYPE_X86_CPU) && (first_x86_cpu->env.hflags & HF_LMA_MASK);
#endif
if (lma) {
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index ab72bcdfad..c38e68275e 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -3464,7 +3464,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
* Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
* only sync them to KVM on the first cpu
*/
- if (current_cpu == first_cpu) {
+ if (current_cpu == qemu_get_cpu(0, TYPE_X86_CPU)) {
if (has_msr_hv_hypercall) {
kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
env->msr_hv_guest_os_id);
@@ -5601,10 +5601,10 @@ uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
CPUX86State *env;
uint64_t ext_id;
- if (!first_cpu) {
+ if (!qemu_get_cpu(0, TYPE_X86_CPU)) {
return address;
}
- env = &X86_CPU(first_cpu)->env;
+ env = &X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU))->env;
if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) {
return address;
}
diff --git a/target/i386/tcg/sysemu/fpu_helper.c b/target/i386/tcg/sysemu/fpu_helper.c
index 93506cdd94..942d04037c 100644
--- a/target/i386/tcg/sysemu/fpu_helper.c
+++ b/target/i386/tcg/sysemu/fpu_helper.c
@@ -41,13 +41,13 @@ void fpu_check_raise_ferr_irq(CPUX86State *env)
void cpu_clear_ignne(void)
{
- CPUX86State *env = &X86_CPU(first_cpu)->env;
+ CPUX86State *env = &X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU))->env;
env->hflags2 &= ~HF2_IGNNE_MASK;
}
void cpu_set_ignne(void)
{
- CPUX86State *env = &X86_CPU(first_cpu)->env;
+ CPUX86State *env = &X86_CPU(qemu_get_cpu(0, TYPE_X86_CPU))->env;
assert(qemu_mutex_iothread_locked());
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH 10/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_ARM_CPU)
2023-10-20 16:36 ` [PATCH 10/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_ARM_CPU) Philippe Mathieu-Daudé
@ 2023-10-20 16:53 ` Cédric Le Goater
0 siblings, 0 replies; 27+ messages in thread
From: Cédric Le Goater @ 2023-10-20 16:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Andrew Jeffery, Joel Stanley,
Igor Mitsyanko, Rob Herring, Subbaraya Sundeep, Alistair Francis,
Felipe Balbi, Niek Linnenbank, Radoslaw Biernacki, Leif Lindholm,
Marcin Juszkiewicz, Alexandre Iooss
On 10/20/23 18:36, Philippe Mathieu-Daudé wrote:
> Mechanical change using the following coccinelle script:
>
> @@ @@
> - first_cpu
> + qemu_get_cpu(0, TYPE_ARM_CPU)
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
For aspeed,
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed.c | 5 +++--
> hw/arm/bananapi_m2u.c | 3 ++-
> hw/arm/boot.c | 12 ++++++------
> hw/arm/exynos4_boards.c | 6 ++++--
> hw/arm/highbank.c | 3 ++-
> hw/arm/microbit.c | 3 ++-
> hw/arm/mps2-tz.c | 3 ++-
> hw/arm/mps2.c | 3 ++-
> hw/arm/msf2-som.c | 3 ++-
> hw/arm/musca.c | 3 ++-
> hw/arm/netduino2.c | 3 ++-
> hw/arm/netduinoplus2.c | 2 +-
> hw/arm/olimex-stm32-h405.c | 2 +-
> hw/arm/orangepi.c | 3 ++-
> hw/arm/realview.c | 5 +++--
> hw/arm/sbsa-ref.c | 3 ++-
> hw/arm/stellaris.c | 3 ++-
> hw/arm/stm32vldiscovery.c | 2 +-
> hw/arm/vexpress.c | 3 ++-
> hw/arm/virt.c | 17 ++++++++++-------
> hw/arm/xilinx_zynq.c | 3 ++-
> target/arm/arch_dump.c | 6 +++---
> 22 files changed, 58 insertions(+), 38 deletions(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index f8ba67531a..6a4d87bfe2 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -446,7 +446,8 @@ static void aspeed_machine_init(MachineState *machine)
> }
> }
>
> - arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
> + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
> + &aspeed_board_binfo);
> }
>
> static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
> @@ -1553,7 +1554,7 @@ static void aspeed_minibmc_machine_init(MachineState *machine)
> amc->i2c_init(bmc);
> }
>
> - armv7m_load_kernel(ARM_CPU(first_cpu),
> + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
> machine->kernel_filename,
> 0,
> AST1030_INTERNAL_FLASH_SIZE);
> diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
> index 74121d8966..431b1c9bf9 100644
> --- a/hw/arm/bananapi_m2u.c
> +++ b/hw/arm/bananapi_m2u.c
> @@ -127,7 +127,8 @@ static void bpim2u_init(MachineState *machine)
> bpim2u_binfo.loader_start = r40->memmap[AW_R40_DEV_SDRAM];
> bpim2u_binfo.ram_size = machine->ram_size;
> bpim2u_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
> - arm_load_kernel(ARM_CPU(first_cpu), machine, &bpim2u_binfo);
> + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
> + &bpim2u_binfo);
> }
>
> static void bpim2u_machine_init(MachineClass *mc)
> diff --git a/hw/arm/boot.c b/hw/arm/boot.c
> index f7def3a60c..71c0775984 100644
> --- a/hw/arm/boot.c
> +++ b/hw/arm/boot.c
> @@ -781,7 +781,7 @@ static void do_cpu_reset(void *opaque)
>
> /* Set to non-secure if not a secure boot */
> if (!info->secure_boot &&
> - (cs != first_cpu || !info->secure_board_setup)) {
> + (cs != qemu_get_cpu(0, TYPE_ARM_CPU) || !info->secure_board_setup)) {
> /* Linux expects non-secure state */
> env->cp15.scr_el3 |= SCR_NS;
> /* Set NSACR.{CP11,CP10} so NS can access the FPU */
> @@ -800,7 +800,7 @@ static void do_cpu_reset(void *opaque)
> cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw);
> }
>
> - if (cs == first_cpu) {
> + if (cs == qemu_get_cpu(0, TYPE_ARM_CPU)) {
> AddressSpace *as = arm_boot_address_space(cpu, info);
>
> cpu_set_pc(cs, info->loader_start);
> @@ -1187,7 +1187,7 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
> }
> info->is_linux = is_linux;
>
> - for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
> + for (cs = qemu_get_cpu(0, TYPE_ARM_CPU); cs; cs = CPU_NEXT(cs)) {
> ARM_CPU(cs)->env.boot_info = info;
> }
> }
> @@ -1264,7 +1264,7 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
> * actually loading a kernel, the handler is also responsible for
> * arranging that we start it correctly.
> */
> - for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
> + for (cs = qemu_get_cpu(0, TYPE_ARM_CPU); cs; cs = CPU_NEXT(cs)) {
> qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
> nb_cpus++;
> }
> @@ -1325,7 +1325,7 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
> }
>
> if (info->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
> - for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
> + for (cs = qemu_get_cpu(0, TYPE_ARM_CPU); cs; cs = CPU_NEXT(cs)) {
> Object *cpuobj = OBJECT(cs);
>
> object_property_set_int(cpuobj, "psci-conduit", info->psci_conduit,
> @@ -1335,7 +1335,7 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
> * code in do_cpu_reset(), we assume first_cpu is the primary
> * CPU.
> */
> - if (cs != first_cpu) {
> + if (cs != qemu_get_cpu(0, TYPE_ARM_CPU)) {
> object_property_set_bool(cpuobj, "start-powered-off", true,
> &error_abort);
> }
> diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
> index ef5bcbc212..f8cf0588b4 100644
> --- a/hw/arm/exynos4_boards.c
> +++ b/hw/arm/exynos4_boards.c
> @@ -136,7 +136,8 @@ static void nuri_init(MachineState *machine)
> {
> exynos4_boards_init_common(machine, EXYNOS4_BOARD_NURI);
>
> - arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo);
> + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
> + &exynos4_board_binfo);
> }
>
> static void smdkc210_init(MachineState *machine)
> @@ -146,7 +147,8 @@ static void smdkc210_init(MachineState *machine)
>
> lan9215_init(SMDK_LAN9118_BASE_ADDR,
> qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
> - arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo);
> + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
> + &exynos4_board_binfo);
> }
>
> static void nuri_class_init(ObjectClass *oc, void *data)
> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
> index f12aacea6b..393fa8a468 100644
> --- a/hw/arm/highbank.c
> +++ b/hw/arm/highbank.c
> @@ -328,7 +328,8 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
> highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
> highbank_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
>
> - arm_load_kernel(ARM_CPU(first_cpu), machine, &highbank_binfo);
> + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
> + &highbank_binfo);
> }
>
> static void highbank_init(MachineState *machine)
> diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
> index 50df362088..19c2fc3b8e 100644
> --- a/hw/arm/microbit.c
> +++ b/hw/arm/microbit.c
> @@ -56,7 +56,8 @@ static void microbit_init(MachineState *machine)
> memory_region_add_subregion_overlap(&s->nrf51.container, NRF51_TWI_BASE,
> mr, -1);
>
> - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
> + machine->kernel_filename,
> 0, s->nrf51.flash_size);
> }
>
> diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
> index eae3639da2..0b26eab45d 100644
> --- a/hw/arm/mps2-tz.c
> +++ b/hw/arm/mps2-tz.c
> @@ -1217,7 +1217,8 @@ static void mps2tz_common_init(MachineState *machine)
> mms->remap_irq);
> }
>
> - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
> + machine->kernel_filename,
> 0, boot_ram_size(mms));
> }
>
> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
> index d92fd60684..86e5ca0ce6 100644
> --- a/hw/arm/mps2.c
> +++ b/hw/arm/mps2.c
> @@ -462,7 +462,8 @@ static void mps2_common_init(MachineState *machine)
> qdev_get_gpio_in(armv7m,
> mmc->fpga_type == FPGA_AN511 ? 47 : 13));
>
> - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
> + machine->kernel_filename,
> 0, 0x400000);
> }
>
> diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
> index 7b3106c790..42a3eb4905 100644
> --- a/hw/arm/msf2-som.c
> +++ b/hw/arm/msf2-som.c
> @@ -100,7 +100,8 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
> cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
> sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
>
> - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
> + machine->kernel_filename,
> 0, soc->envm_size);
> }
>
> diff --git a/hw/arm/musca.c b/hw/arm/musca.c
> index 6eeee57c9d..8d9b93d931 100644
> --- a/hw/arm/musca.c
> +++ b/hw/arm/musca.c
> @@ -597,7 +597,8 @@ static void musca_init(MachineState *machine)
> "cfg_sec_resp", 0));
> }
>
> - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
> + machine->kernel_filename,
> 0, 0x2000000);
> }
>
> diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
> index 83753d53a3..61fe0346fe 100644
> --- a/hw/arm/netduino2.c
> +++ b/hw/arm/netduino2.c
> @@ -48,7 +48,8 @@ static void netduino2_init(MachineState *machine)
> qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
> + machine->kernel_filename,
> 0, FLASH_SIZE);
> }
>
> diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
> index 515c081605..ad68421b97 100644
> --- a/hw/arm/netduinoplus2.c
> +++ b/hw/arm/netduinoplus2.c
> @@ -48,7 +48,7 @@ static void netduinoplus2_init(MachineState *machine)
> qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> - armv7m_load_kernel(ARM_CPU(first_cpu),
> + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
> machine->kernel_filename,
> 0, FLASH_SIZE);
> }
> diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
> index 3aa61c91b7..a44c6188c4 100644
> --- a/hw/arm/olimex-stm32-h405.c
> +++ b/hw/arm/olimex-stm32-h405.c
> @@ -51,7 +51,7 @@ static void olimex_stm32_h405_init(MachineState *machine)
> qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> - armv7m_load_kernel(ARM_CPU(first_cpu),
> + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
> machine->kernel_filename,
> 0, FLASH_SIZE);
> }
> diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
> index 10653361ed..7d44715111 100644
> --- a/hw/arm/orangepi.c
> +++ b/hw/arm/orangepi.c
> @@ -105,7 +105,8 @@ static void orangepi_init(MachineState *machine)
> orangepi_binfo.loader_start = h3->memmap[AW_H3_DEV_SDRAM];
> orangepi_binfo.ram_size = machine->ram_size;
> orangepi_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
> - arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
> + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
> + &orangepi_binfo);
> }
>
> static void orangepi_machine_init(MachineClass *mc)
> diff --git a/hw/arm/realview.c b/hw/arm/realview.c
> index 8f89526596..be709146c8 100644
> --- a/hw/arm/realview.c
> +++ b/hw/arm/realview.c
> @@ -136,7 +136,7 @@ static void realview_init(MachineState *machine,
>
> cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
> }
> - cpu = ARM_CPU(first_cpu);
> + cpu = ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU));
> env = &cpu->env;
> if (arm_feature(env, ARM_FEATURE_V7)) {
> if (is_mpcore) {
> @@ -384,7 +384,8 @@ static void realview_init(MachineState *machine,
> realview_binfo.ram_size = ram_size;
> realview_binfo.board_id = realview_board_id[board_type];
> realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
> - arm_load_kernel(ARM_CPU(first_cpu), machine, &realview_binfo);
> + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
> + &realview_binfo);
> }
>
> static void realview_eb_init(MachineState *machine)
> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> index a85004809f..01c948725c 100644
> --- a/hw/arm/sbsa-ref.c
> +++ b/hw/arm/sbsa-ref.c
> @@ -844,7 +844,8 @@ static void sbsa_ref_init(MachineState *machine)
> sms->bootinfo.loader_start = sbsa_ref_memmap[SBSA_MEM].base;
> sms->bootinfo.get_dtb = sbsa_ref_dtb;
> sms->bootinfo.firmware_loaded = firmware_loaded;
> - arm_load_kernel(ARM_CPU(first_cpu), machine, &sms->bootinfo);
> + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
> + &sms->bootinfo);
> }
>
> static const CPUArchIdList *sbsa_ref_possible_cpu_arch_ids(MachineState *ms)
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index aa5b0ddfaa..0920b9cb86 100644
> --- a/hw/arm/stellaris.c
> +++ b/hw/arm/stellaris.c
> @@ -1307,7 +1307,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
> create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
> create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
>
> - armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, 0, flash_size);
> + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
> + ms->kernel_filename, 0, flash_size);
> }
>
> /* FIXME: Figure out how to generate these from stellaris_boards. */
> diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
> index 67675e952f..2df943295b 100644
> --- a/hw/arm/stm32vldiscovery.c
> +++ b/hw/arm/stm32vldiscovery.c
> @@ -51,7 +51,7 @@ static void stm32vldiscovery_init(MachineState *machine)
> qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> - armv7m_load_kernel(ARM_CPU(first_cpu),
> + armv7m_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)),
> machine->kernel_filename,
> 0, FLASH_SIZE);
> }
> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
> index e20d865d5a..8107a7057a 100644
> --- a/hw/arm/vexpress.c
> +++ b/hw/arm/vexpress.c
> @@ -712,7 +712,8 @@ static void vexpress_common_init(MachineState *machine)
> daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
> /* When booting Linux we should be in secure state if the CPU has one. */
> daughterboard->bootinfo.secure_boot = vms->secure;
> - arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo);
> + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
> + &daughterboard->bootinfo);
> }
>
> static bool vexpress_get_secure(Object *obj, Error **errp)
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index da5b738f0a..9f69be85ce 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -605,7 +605,7 @@ static void fdt_add_gic_node(VirtMachineState *vms)
>
> static void fdt_add_pmu_nodes(const VirtMachineState *vms)
> {
> - ARMCPU *armcpu = ARM_CPU(first_cpu);
> + ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU));
> uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
> MachineState *ms = MACHINE(vms);
>
> @@ -1652,7 +1652,7 @@ void virt_machine_done(Notifier *notifier, void *data)
> VirtMachineState *vms = container_of(notifier, VirtMachineState,
> machine_done);
> MachineState *ms = MACHINE(vms);
> - ARMCPU *cpu = ARM_CPU(first_cpu);
> + ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU));
> struct arm_boot_info *info = &vms->bootinfo;
> AddressSpace *as = arm_boot_address_space(cpu, info);
>
> @@ -1957,9 +1957,11 @@ static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
> bool aarch64, pmu, steal_time;
> CPUState *cpu;
>
> - aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
> - pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
> - steal_time = object_property_get_bool(OBJECT(first_cpu),
> + aarch64 = object_property_get_bool(OBJECT(qemu_get_cpu(0, TYPE_ARM_CPU)),
> + "aarch64", NULL);
> + pmu = object_property_get_bool(OBJECT(qemu_get_cpu(0, TYPE_ARM_CPU)),
> + "pmu", NULL);
> + steal_time = object_property_get_bool(OBJECT(qemu_get_cpu(0, TYPE_ARM_CPU)),
> "kvm-steal-time", NULL);
>
> if (kvm_enabled()) {
> @@ -2001,7 +2003,7 @@ static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
> } else {
> if (aarch64 && vms->highmem) {
> int requested_pa_size = 64 - clz64(vms->highest_gpa);
> - int pamax = arm_pamax(ARM_CPU(first_cpu));
> + int pamax = arm_pamax(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)));
>
> if (pamax < requested_pa_size) {
> error_report("VCPU supports less PA bits (%d) than "
> @@ -2324,7 +2326,8 @@ static void machvirt_init(MachineState *machine)
> vms->bootinfo.skip_dtb_autoload = true;
> vms->bootinfo.firmware_loaded = firmware_loaded;
> vms->bootinfo.psci_conduit = vms->psci_conduit;
> - arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
> + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
> + &vms->bootinfo);
>
> vms->machine_done.notify = virt_machine_done;
> qemu_add_machine_init_done_notifier(&vms->machine_done);
> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
> index 8dc2ea83a9..90a052b841 100644
> --- a/hw/arm/xilinx_zynq.c
> +++ b/hw/arm/xilinx_zynq.c
> @@ -349,7 +349,8 @@ static void zynq_init(MachineState *machine)
> zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
> zynq_binfo.write_board_setup = zynq_write_board_setup;
>
> - arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo);
> + arm_load_kernel(ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU)), machine,
> + &zynq_binfo);
> }
>
> static void zynq_machine_class_init(ObjectClass *oc, void *data)
> diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
> index 2d8e41ab8a..25dffccb99 100644
> --- a/target/arm/arch_dump.c
> +++ b/target/arm/arch_dump.c
> @@ -395,11 +395,11 @@ int cpu_get_dump_info(ArchDumpInfo *info,
> GuestPhysBlock *block;
> hwaddr lowest_addr = ULLONG_MAX;
>
> - if (first_cpu == NULL) {
> + if (qemu_get_cpu(0, TYPE_ARM_CPU) == NULL) {
> return -1;
> }
>
> - cpu = ARM_CPU(first_cpu);
> + cpu = ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU));
> env = &cpu->env;
>
> /* Take a best guess at the phys_base. If we get it wrong then crash
> @@ -443,7 +443,7 @@ int cpu_get_dump_info(ArchDumpInfo *info,
>
> ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
> {
> - ARMCPU *cpu = ARM_CPU(first_cpu);
> + ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0, TYPE_ARM_CPU));
> size_t note_size;
>
> if (class == ELFCLASS64) {
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type
2023-10-20 16:36 ` [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type Philippe Mathieu-Daudé
@ 2023-10-20 17:14 ` Peter Maydell
2023-10-20 17:29 ` Philippe Mathieu-Daudé
2023-10-23 14:21 ` Zhao Liu
2023-10-23 15:12 ` David Woodhouse
2 siblings, 1 reply; 27+ messages in thread
From: Peter Maydell @ 2023-10-20 17:14 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Thomas Huth, Richard Henderson, Paolo Bonzini,
Alistair Francis, qemu-arm, qemu-riscv, Edgar E. Iglesias,
qemu-ppc, Eduardo Habkost, Michael S. Tsirkin, qemu-s390x,
Alex Bennée, Zhao Liu, Andrey Smirnov, Radoslaw Biernacki,
Leif Lindholm, Marcin Juszkiewicz, Shannon Zhao, Igor Mammedov,
Ani Sinha, Alistair Francis, David Woodhouse, Paul Durrant,
Marcel Apfelbaum, Palmer Dabbelt, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Song Gao, Thomas Huth,
Christian Borntraeger, Halil Pasic, Eric Farman,
David Hildenbrand, Ilya Leoshkevich, Yanan Wang,
Dr. David Alan Gilbert, Marcelo Tosatti, Aurelien Jarno,
Jiaxun Yang, Aleksandar Rikalo, kvm
On Fri, 20 Oct 2023 at 17:36, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> Heterogeneous machines have different type of CPU.
> qemu_get_cpu() returning unfiltered CPUs doesn't make
> sense anymore. Add a 'type' argument to filter CPU by
> QOM type.
I'm not sure "filter by CPU type" is ever really the
correct answer to this problem, though.
Picking out a handful of arm-related parts to this patchset
as examples of different situations where we're currently
using qemu_get_cpu():
> diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
> index 474cfdc87c..1c1585f3e1 100644
> --- a/hw/arm/fsl-imx7.c
> +++ b/hw/arm/fsl-imx7.c
> @@ -212,7 +212,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
>
> for (i = 0; i < smp_cpus; i++) {
> SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
> - DeviceState *d = DEVICE(qemu_get_cpu(i));
> + DeviceState *d = DEVICE(qemu_get_cpu(i, NULL));
>
> irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
> sysbus_connect_irq(sbd, i, irq);
This is an Arm SoC object. What it wants is not "the i'th Arm
CPU in the whole system", but "the i'th CPU in this SoC object".
Conveniently, it has easy access to that: s->cpu[i].
> diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c
> index e7c3d99224..0a698171ab 100644
> --- a/hw/arm/pxa2xx_gpio.c
> +++ b/hw/arm/pxa2xx_gpio.c
> @@ -303,7 +303,7 @@ static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
> {
> PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
>
> - s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
> + s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu, NULL));
>
> qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
> qdev_init_gpio_out(dev, s->handler, s->lines);
This is grabbing a private pointer to the CPU object[*], which
we can do more cleanly by setting a link property, and getting
the board code to pass a pointer to the CPU.
[*] it then uses that pointer to mess with the internals of
the CPU to implement wake-up-on-GPIO in a completely horrible
way, but let's assume we don't want to try to clean that up now...
> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> index 3c7dfcd6dc..3571d5038f 100644
> --- a/hw/arm/sbsa-ref.c
> +++ b/hw/arm/sbsa-ref.c
> @@ -275,7 +275,7 @@ static void create_fdt(SBSAMachineState *sms)
>
> for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
> char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
> - ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
> + ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu, NULL));
> CPUState *cs = CPU(armcpu);
> uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu);
This is in a board model. By definition the board model for a
non-heterogenous board knows it isn't in a heterogenous system
model, and it doesn't need to say "specifically the first Arm CPU".
So I think we should be able to leave it alone...
> diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
> index bfd8aa5644..8c9098d5d3 100644
> --- a/hw/cpu/a15mpcore.c
> +++ b/hw/cpu/a15mpcore.c
> @@ -65,7 +65,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
> /* Make the GIC's TZ support match the CPUs. We assume that
> * either all the CPUs have TZ, or none do.
> */
> - cpuobj = OBJECT(qemu_get_cpu(0));
> + cpuobj = OBJECT(qemu_get_cpu(0, NULL));
> has_el3 = object_property_find(cpuobj, "has_el3") &&
> object_property_get_bool(cpuobj, "has_el3", &error_abort);
> qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
> @@ -90,7 +90,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
> * appropriate GIC PPI inputs
> */
> for (i = 0; i < s->num_cpu; i++) {
> - DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
> + DeviceState *cpudev = DEVICE(qemu_get_cpu(i, NULL));
> int ppibase = s->num_irq - 32 + i * 32;
> int irq;
> /* Mapping from the output timer irq lines from the CPU to the
This is another case where what we want is "the Nth CPU
associated with this peripheral block", not the Nth CPU of
some particular architecture. (It's not as easy to figure
out where we would get that from as it is in the fsl-imx7
case, though -- perhaps we would need to tweak the API
these objects have somehow to pass in pointers to the CPUs?)
> diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
> index 2ebf880ead..cdf21dfc11 100644
> --- a/hw/intc/arm_gicv3_common.c
> +++ b/hw/intc/arm_gicv3_common.c
> @@ -392,7 +392,7 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
> s->cpu = g_new0(GICv3CPUState, s->num_cpu);
>
> for (i = 0; i < s->num_cpu; i++) {
> - CPUState *cpu = qemu_get_cpu(i);
> + CPUState *cpu = qemu_get_cpu(i, NULL);
> uint64_t cpu_affid;
>
> s->cpu[i].cpu = cpu;
These gicv3 uses of qemu_get_cpu() are because instead of doing
the theoretical Right Thing and having the GIC object have to
be told which CPUs it is responsible for, we took a shortcut
and said "there's only one GIC, and it's connected to all the CPUs".
The fix is, again, not filtering by CPU type, but having the
board and SoC models do the work to explicitly represent
"this GIC object is attached to these CPU objects" (via link
properties or otherwise).
So overall there are some places where figuring out the right
replacement for qemu_get_cpu() is tricky, and some places where
it's probably fairly straightforward but just an annoying
amount of extra code to write, and some places where we don't
care because we know the board model is not heterogenous.
But I don't think "filter by CPU architecture type" is usually
going to be what we want.
thanks
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type
2023-10-20 17:14 ` Peter Maydell
@ 2023-10-20 17:29 ` Philippe Mathieu-Daudé
2023-10-20 17:40 ` Peter Maydell
0 siblings, 1 reply; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-10-20 17:29 UTC (permalink / raw)
To: Peter Maydell, Alex Bennée
Cc: qemu-devel, Thomas Huth, Richard Henderson, Paolo Bonzini,
Alistair Francis, qemu-arm, qemu-riscv, Edgar E. Iglesias,
qemu-ppc, Eduardo Habkost, Michael S. Tsirkin, qemu-s390x,
Zhao Liu, Andrey Smirnov, Radoslaw Biernacki, Leif Lindholm,
Marcin Juszkiewicz, Shannon Zhao, Igor Mammedov, Ani Sinha,
Alistair Francis, David Woodhouse, Paul Durrant, Marcel Apfelbaum,
Palmer Dabbelt, Bin Meng, Weiwei Li, Daniel Henrique Barboza,
Liu Zhiwei, Song Gao, Thomas Huth, Christian Borntraeger,
Halil Pasic, Eric Farman, David Hildenbrand, Ilya Leoshkevich,
Yanan Wang, Dr. David Alan Gilbert, Marcelo Tosatti,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo, kvm
Hi Peter,
On 20/10/23 19:14, Peter Maydell wrote:
> On Fri, 20 Oct 2023 at 17:36, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>>
>> Heterogeneous machines have different type of CPU.
>> qemu_get_cpu() returning unfiltered CPUs doesn't make
>> sense anymore. Add a 'type' argument to filter CPU by
>> QOM type.
>
> I'm not sure "filter by CPU type" is ever really the
> correct answer to this problem, though.
>
> Picking out a handful of arm-related parts to this patchset
> as examples of different situations where we're currently
> using qemu_get_cpu():
>
>> diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
>> index 474cfdc87c..1c1585f3e1 100644
>> --- a/hw/arm/fsl-imx7.c
>> +++ b/hw/arm/fsl-imx7.c
>> @@ -212,7 +212,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
>>
>> for (i = 0; i < smp_cpus; i++) {
>> SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
>> - DeviceState *d = DEVICE(qemu_get_cpu(i));
>> + DeviceState *d = DEVICE(qemu_get_cpu(i, NULL));
>>
>> irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
>> sysbus_connect_irq(sbd, i, irq);
>
> This is an Arm SoC object. What it wants is not "the i'th Arm
> CPU in the whole system", but "the i'th CPU in this SoC object".
> Conveniently, it has easy access to that: s->cpu[i].
>
>> diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c
>> index e7c3d99224..0a698171ab 100644
>> --- a/hw/arm/pxa2xx_gpio.c
>> +++ b/hw/arm/pxa2xx_gpio.c
>> @@ -303,7 +303,7 @@ static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
>> {
>> PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
>>
>> - s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
>> + s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu, NULL));
>>
>> qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
>> qdev_init_gpio_out(dev, s->handler, s->lines);
>
> This is grabbing a private pointer to the CPU object[*], which
> we can do more cleanly by setting a link property, and getting
> the board code to pass a pointer to the CPU.
>
> [*] it then uses that pointer to mess with the internals of
> the CPU to implement wake-up-on-GPIO in a completely horrible
> way, but let's assume we don't want to try to clean that up now...
>
>> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
>> index 3c7dfcd6dc..3571d5038f 100644
>> --- a/hw/arm/sbsa-ref.c
>> +++ b/hw/arm/sbsa-ref.c
>> @@ -275,7 +275,7 @@ static void create_fdt(SBSAMachineState *sms)
>>
>> for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
>> char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
>> - ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
>> + ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu, NULL));
>> CPUState *cs = CPU(armcpu);
>> uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu);
>
> This is in a board model. By definition the board model for a
> non-heterogenous board knows it isn't in a heterogenous system
> model, and it doesn't need to say "specifically the first Arm CPU".
> So I think we should be able to leave it alone...
>
>> diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
>> index bfd8aa5644..8c9098d5d3 100644
>> --- a/hw/cpu/a15mpcore.c
>> +++ b/hw/cpu/a15mpcore.c
>> @@ -65,7 +65,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
>> /* Make the GIC's TZ support match the CPUs. We assume that
>> * either all the CPUs have TZ, or none do.
>> */
>> - cpuobj = OBJECT(qemu_get_cpu(0));
>> + cpuobj = OBJECT(qemu_get_cpu(0, NULL));
>> has_el3 = object_property_find(cpuobj, "has_el3") &&
>> object_property_get_bool(cpuobj, "has_el3", &error_abort);
>> qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
>> @@ -90,7 +90,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
>> * appropriate GIC PPI inputs
>> */
>> for (i = 0; i < s->num_cpu; i++) {
>> - DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
>> + DeviceState *cpudev = DEVICE(qemu_get_cpu(i, NULL));
>> int ppibase = s->num_irq - 32 + i * 32;
>> int irq;
>> /* Mapping from the output timer irq lines from the CPU to the
>
> This is another case where what we want is "the Nth CPU
> associated with this peripheral block", not the Nth CPU of
> some particular architecture. (It's not as easy to figure
> out where we would get that from as it is in the fsl-imx7
> case, though -- perhaps we would need to tweak the API
> these objects have somehow to pass in pointers to the CPUs?)
>
>> diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
>> index 2ebf880ead..cdf21dfc11 100644
>> --- a/hw/intc/arm_gicv3_common.c
>> +++ b/hw/intc/arm_gicv3_common.c
>> @@ -392,7 +392,7 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
>> s->cpu = g_new0(GICv3CPUState, s->num_cpu);
>>
>> for (i = 0; i < s->num_cpu; i++) {
>> - CPUState *cpu = qemu_get_cpu(i);
>> + CPUState *cpu = qemu_get_cpu(i, NULL);
>> uint64_t cpu_affid;
>>
>> s->cpu[i].cpu = cpu;
>
> These gicv3 uses of qemu_get_cpu() are because instead of doing
> the theoretical Right Thing and having the GIC object have to
> be told which CPUs it is responsible for, we took a shortcut
> and said "there's only one GIC, and it's connected to all the CPUs".
> The fix is, again, not filtering by CPU type, but having the
> board and SoC models do the work to explicitly represent
> "this GIC object is attached to these CPU objects" (via link
> properties or otherwise).
>
>
> So overall there are some places where figuring out the right
> replacement for qemu_get_cpu() is tricky, and some places where
> it's probably fairly straightforward but just an annoying
> amount of extra code to write, and some places where we don't
> care because we know the board model is not heterogenous.
> But I don't think "filter by CPU architecture type" is usually
> going to be what we want.
Thank for these feedbacks. I agree the correct way to fix that
is a tedious case by case audit, most often using link properties.
"we know the board model is not heterogeneous" but we want to
link such board/model altogether in a single binary, using common
APIs.
qemu_get_cpu() isn't scalable, so as you said the board has to
propagate its CPUs as properties to the devices which require
access to them. Eventually removing qemu_get_cpu() use from hw/.
I started isolating PCI Host Bridges devices as an example of
device complex enough to use multiple address spaces, and I figured
it'll take some time... So wanted to give a try at some generic
mechanical changes to allow a small step in my prototype,
postponing the case by case changes. I agree this isn't the best
approach and I should start with few devices, ignoring the rest
of the tree (not converting all at once).
Interrupt Controller are another cases which need CPU as link
properties. See for example this M68K series:
https://lore.kernel.org/qemu-devel/20231020150627.56893-1-philmd@linaro.org/
Regards,
Phil.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type
2023-10-20 17:29 ` Philippe Mathieu-Daudé
@ 2023-10-20 17:40 ` Peter Maydell
0 siblings, 0 replies; 27+ messages in thread
From: Peter Maydell @ 2023-10-20 17:40 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alex Bennée, qemu-devel, Thomas Huth, Richard Henderson,
Paolo Bonzini, Alistair Francis, qemu-arm, qemu-riscv,
Edgar E. Iglesias, qemu-ppc, Eduardo Habkost, Michael S. Tsirkin,
qemu-s390x, Zhao Liu, Andrey Smirnov, Radoslaw Biernacki,
Leif Lindholm, Marcin Juszkiewicz, Shannon Zhao, Igor Mammedov,
Ani Sinha, Alistair Francis, David Woodhouse, Paul Durrant,
Marcel Apfelbaum, Palmer Dabbelt, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Song Gao, Thomas Huth,
Christian Borntraeger, Halil Pasic, Eric Farman,
David Hildenbrand, Ilya Leoshkevich, Yanan Wang,
Dr. David Alan Gilbert, Marcelo Tosatti, Aurelien Jarno,
Jiaxun Yang, Aleksandar Rikalo, kvm
On Fri, 20 Oct 2023 at 18:29, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> Hi Peter,
>
> On 20/10/23 19:14, Peter Maydell wrote:
> > So overall there are some places where figuring out the right
> > replacement for qemu_get_cpu() is tricky, and some places where
> > it's probably fairly straightforward but just an annoying
> > amount of extra code to write, and some places where we don't
> > care because we know the board model is not heterogenous.
> > But I don't think "filter by CPU architecture type" is usually
> > going to be what we want.
>
> Thank for these feedbacks. I agree the correct way to fix that
> is a tedious case by case audit, most often using link properties.
>
> "we know the board model is not heterogeneous" but we want to
> link such board/model altogether in a single binary, using common
> APIs.
This seems to me like a different thing -- just compiling
the different boards into one binary. That should be fine:
in this single-binary qemu, if you tell it -M foo that's an arm
board then qemu_get_cpu() returns the CPUs that are created,
and those will all be Arm. If you tell it -M bar that's a PPC
board, then qemu_get_cpu() will return the CPUs that are
created, and those will all be PPC. The assumptions of the
code that's currently calling qemu_get_cpu() or using the
first_cpu global won't be broken. It shouldn't need us to
change a lot of code that we don't intend to try to use in a
heterogenous-at-runtime setup.
thanks
-- PMM
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 00/19] cpus: Step toward removing global 'first_cpu'
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
` (18 preceding siblings ...)
2023-10-20 16:36 ` [PATCH 19/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_X86_CPU) Philippe Mathieu-Daudé
@ 2023-10-23 13:59 ` Zhao Liu
19 siblings, 0 replies; 27+ messages in thread
From: Zhao Liu @ 2023-10-23 13:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Thomas Huth, Richard Henderson, Paolo Bonzini,
Alistair Francis, qemu-arm, qemu-riscv, Edgar E. Iglesias,
qemu-ppc, Eduardo Habkost, Michael S. Tsirkin, qemu-s390x,
Peter Maydell, Alex Bennée, Zhao Liu
Hi Philippe,
On Fri, Oct 20, 2023 at 06:36:22PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 20 Oct 2023 18:36:22 +0200
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [PATCH 00/19] cpus: Step toward removing global 'first_cpu'
> X-Mailer: git-send-email 2.41.0
>
> Heterogeneous machines have different type of CPU.
> In that context, both 'first_cpu' and qemu_get_cpu(index)
> don't make much sense.
Could you talk more about what the issue that heterogeneous machines
will meet on these 2 things?
This question relates to when one should need to pay attention to CPU
type.
>
> This series first add a 'filter CPU type' argument to
> qemu_get_cpu(), so the behavior respects what we currently
> expect, then replace 'first_cpu' by a qemu_get_cpu(0) call.
Considering that the current uses of first_cpu and qemu_get_cpu(index)
are CPU type-agnostic, would it be more straightforward to convert most
of the current uses to qemu_get_cpu(index, NULL)?
Regards,
Zhao
>
> Testing pass, but I'm still unsure about performance impact.
>
> With this series applied, what is left is:
>
> [OK]
>
> - hw/core/generic-loader.c:127: s->cpu = qemu_get_cpu(s->cpu_num, NULL);
> - linux-user/syscall.c:8990: if (CPU_NEXT(first_cpu)) {
> - monitor/hmp-cmds-target.c:106: cs = vcpu >= 0 ? qemu_get_cpu(vcpu, NULL) : mon_get_cpu(mon);
> - stats/stats-hmp-cmds.c:150: CPUState *cpu = qemu_get_cpu(cpu_index, NULL);
> - system/cpus.c:754: cpu = qemu_get_cpu(cpu_index, NULL);
>
> [likely OK, we don't support heterogeneous accelerators]
>
> - accel/kvm/kvm-all.c:3581: kvm_arch_on_sigbus_vcpu(first_cpu, code, addr);
> - accel/kvm/kvm-all.c:4255: if (first_cpu) {
> - accel/kvm/kvm-all.c:4258: query_stats_schema_vcpu(first_cpu, &stats_args);
>
> [need some toughts...]
>
> - accel/tcg/tcg-accel-ops-rr.c:114: qemu_cond_wait_iothread(first_cpu->halt_cond);
> - accel/tcg/tcg-accel-ops-rr.c:200: while (first_cpu->stopped) {
> - accel/tcg/tcg-accel-ops-rr.c:201: qemu_cond_wait_iothread(first_cpu->halt_cond);
> - accel/tcg/tcg-accel-ops-rr.c:212: cpu = first_cpu;
> - accel/tcg/tcg-accel-ops-rr.c:242: cpu = first_cpu;
> - accel/tcg/tcg-accel-ops-rr.c:336: cpu->thread_id = first_cpu->thread_id;
> - accel/tcg/tcg-accel-ops-rr.c:92: if (!rr_kick_vcpu_timer && CPU_NEXT(first_cpu)) {
> - dump/win_dump.c:115: if (cpu_memory_rw_debug(first_cpu,
> - dump/win_dump.c:128: if (cpu_read_ptr(x64, first_cpu,
> - dump/win_dump.c:135: if (cpu_memory_rw_debug(first_cpu, KiBugcheckData,
> - dump/win_dump.c:210: if (cpu_memory_rw_debug(first_cpu,
> - dump/win_dump.c:258: if (cpu_read_ptr(x64, first_cpu,
> - dump/win_dump.c:265: if (cpu_memory_rw_debug(first_cpu,
> - dump/win_dump.c:286: if (cpu_read_ptr(x64, first_cpu,
> - dump/win_dump.c:294: if (cpu_read_ptr(x64, first_cpu,
> - dump/win_dump.c:378: if (cpu_memory_rw_debug(first_cpu, Context,
> - dump/win_dump.c:384: if (cpu_memory_rw_debug(first_cpu, Context,
> - dump/win_dump.c:400: if (cpu_memory_rw_debug(first_cpu, saved_ctx[i].addr,
> - dump/win_dump.c:410: X86CPU *first_x86_cpu = X86_CPU(first_cpu);
> - gdbstub/gdbstub.c:1521: cc = CPU_GET_CLASS(first_cpu);
> - gdbstub/gdbstub.c:298: CPUState *cpu = first_cpu;
> - gdbstub/system.c:338: if (!first_cpu) {
> - hw/acpi/cpu.c:138: if (!cdev->cpu || cdev->cpu == first_cpu) {
> - hw/acpi/cpu.c:150: if (!cdev->cpu || cdev->cpu == first_cpu) {
> - hw/acpi/cpu.c:671: if (CPU(arch_ids->cpus[i].cpu) != first_cpu) {
> - hw/core/generic-loader.c:134: s->cpu = first_cpu;
> - monitor/hmp-cmds-target.c:39: cpu = qemu_get_cpu(cpu_index, NULL);
> - monitor/hmp-cmds-target.c:62: if (!first_cpu) {
> - monitor/hmp-cmds-target.c:65: monitor_set_cpu(mon, first_cpu->cpu_index);
> - monitor/hmp-cmds-target.c:66: cpu = first_cpu;
> - replay/replay-events.c:130: qemu_cpu_kick(first_cpu);
> - system/cpu-timers.c:254: } else if (first_cpu) {
> - system/cpu-timers.c:263: async_run_on_cpu(first_cpu, do_nothing, RUN_ON_CPU_NULL);
> - system/memory_mapping.c:315: first_paging_enabled_cpu = find_paging_enabled_cpu(first_cpu);
> - system/qtest.c:548: address_space_write(first_cpu->as, ...
> - system/qtest.c:553: address_space_write(first_cpu->as, ...
> - system/qtest.c:558: address_space_write(first_cpu->as, ...
> - system/qtest.c:563: address_space_write(first_cpu->as, ...
> - system/qtest.c:582: address_space_read(first_cpu->as, ...
> - system/qtest.c:587: address_space_read(first_cpu->as, ...
> - system/qtest.c:592: address_space_read(first_cpu->as, ...
> - system/qtest.c:596: address_space_read(first_cpu->as, ...
> - system/qtest.c:617: address_space_read(first_cpu->as, ...
> - system/qtest.c:643: address_space_read(first_cpu->as, ...
> - system/qtest.c:678: address_space_write(first_cpu->as, ...
> - system/qtest.c:701: address_space_write(first_cpu->as, ...
> - system/qtest.c:735: address_space_write(first_cpu->as, ...
> - tests/qtest/fuzz/generic_fuzz.c:241: mr1 = address_space_translate(first_cpu->as,
> - tests/qtest/fuzz/qtest_wrappers.c:110: address_space_read(first_cpu->as, ...
> - tests/qtest/fuzz/qtest_wrappers.c:122: address_space_read(first_cpu->as, ...
> - tests/qtest/fuzz/qtest_wrappers.c:134: address_space_read(first_cpu->as, ...
> - tests/qtest/fuzz/qtest_wrappers.c:146: address_space_read(first_cpu->as, ...
> - tests/qtest/fuzz/qtest_wrappers.c:157: address_space_write(first_cpu->as, ...
> - tests/qtest/fuzz/qtest_wrappers.c:167: address_space_write(first_cpu->as, ...
> - tests/qtest/fuzz/qtest_wrappers.c:177: address_space_write(first_cpu->as, ...
> - tests/qtest/fuzz/qtest_wrappers.c:187: address_space_write(first_cpu->as, ...
> - tests/qtest/fuzz/qtest_wrappers.c:197: address_space_read(first_cpu->as, ...
> - tests/qtest/fuzz/qtest_wrappers.c:207: address_space_read(first_cpu->as, ...
> - tests/qtest/fuzz/qtest_wrappers.c:218: address_space_write(first_cpu->as, ...
> - tests/qtest/fuzz/qtest_wrappers.c:229: address_space_write(first_cpu->as, ...
> - tests/qtest/fuzz/qtest_wrappers.c:242: address_space_write(first_cpu->as, ...
>
> Regards,
>
> Phil.
>
> Based-on: <20231013140116.255-1-philmd@linaro.org>
> "target: Make 'cpu-qom.h' really target agnostic" v2
>
> Philippe Mathieu-Daudé (19):
> cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type
> cpus: Filter for target specific CPU (generic)
> cpus: Filter for target specific CPU (arm)
> cpus: Filter for target specific CPU (loongarch)
> cpus: Filter for target specific CPU (mips)
> cpus: Filter for target specific CPU (s390x)
> cpus: Filter for target specific CPU (riscv)
> cpus: Filter for target specific CPU (ppc)
> cpus: Filter for target specific CPU (x86)
> cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_ARM_CPU)
> cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_POWERPC_CPU)
> cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_MIPS_CPU)
> cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_M68K_CPU)
> cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_S390X_CPU)
> cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RISCV_CPU)
> cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_TRICORE_CPU)
> cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_SUPERH_CPU)
> cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RX_CPU)
> cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_X86_CPU)
>
> include/hw/core/cpu.h | 3 ++-
> target/mips/internal.h | 2 +-
> cpu-common.c | 5 ++++-
> hw/arm/aspeed.c | 5 +++--
> hw/arm/bananapi_m2u.c | 3 ++-
> hw/arm/boot.c | 14 +++++++-------
> hw/arm/exynos4_boards.c | 6 ++++--
> hw/arm/fsl-imx7.c | 2 +-
> hw/arm/highbank.c | 3 ++-
> hw/arm/microbit.c | 3 ++-
> hw/arm/mps2-tz.c | 3 ++-
> hw/arm/mps2.c | 3 ++-
> hw/arm/msf2-som.c | 3 ++-
> hw/arm/musca.c | 3 ++-
> hw/arm/netduino2.c | 3 ++-
> hw/arm/netduinoplus2.c | 2 +-
> hw/arm/olimex-stm32-h405.c | 2 +-
> hw/arm/orangepi.c | 3 ++-
> hw/arm/pxa2xx_gpio.c | 2 +-
> hw/arm/realview.c | 5 +++--
> hw/arm/sbsa-ref.c | 7 ++++---
> hw/arm/stellaris.c | 3 ++-
> hw/arm/stm32vldiscovery.c | 2 +-
> hw/arm/vexpress.c | 5 +++--
> hw/arm/virt-acpi-build.c | 2 +-
> hw/arm/virt.c | 25 ++++++++++++++-----------
> hw/arm/xilinx_zynq.c | 3 ++-
> hw/arm/xlnx-versal-virt.c | 2 +-
> hw/core/generic-loader.c | 2 +-
> hw/cpu/a15mpcore.c | 4 ++--
> hw/cpu/a9mpcore.c | 2 +-
> hw/hyperv/hyperv.c | 2 +-
> hw/i386/kvm/clock.c | 4 ++--
> hw/i386/kvm/xen_evtchn.c | 8 ++++----
> hw/i386/kvmvapic.c | 3 ++-
> hw/i386/microvm.c | 2 +-
> hw/i386/pc.c | 7 ++++---
> hw/i386/pc_piix.c | 3 ++-
> hw/i386/x86.c | 2 +-
> hw/intc/arm_gicv3_common.c | 3 ++-
> hw/intc/arm_gicv3_cpuif.c | 2 +-
> hw/intc/arm_gicv3_kvm.c | 2 +-
> hw/intc/m68k_irqc.c | 2 +-
> hw/intc/mips_gic.c | 2 +-
> hw/intc/riscv_aclint.c | 2 +-
> hw/intc/sh_intc.c | 6 ++++--
> hw/intc/sifive_plic.c | 4 ++--
> hw/isa/lpc_ich9.c | 2 +-
> hw/loongarch/virt.c | 10 +++++-----
> hw/m68k/mcf5206.c | 2 +-
> hw/mips/bootloader.c | 3 ++-
> hw/mips/cps.c | 5 +++--
> hw/mips/loongson3_bootp.c | 2 +-
> hw/mips/loongson3_virt.c | 7 ++++---
> hw/mips/malta.c | 2 +-
> hw/misc/mips_cpc.c | 4 ++--
> hw/ppc/e500.c | 4 ++--
> hw/ppc/ppc.c | 4 ++--
> hw/ppc/ppce500_spin.c | 2 +-
> hw/ppc/prep_systemio.c | 2 +-
> hw/ppc/spapr.c | 11 ++++++-----
> hw/ppc/spapr_caps.c | 10 +++++-----
> hw/ppc/spapr_rtas.c | 2 +-
> hw/ppc/spapr_vof.c | 2 +-
> hw/ppc/vof.c | 3 ++-
> hw/riscv/boot.c | 4 ++--
> hw/riscv/opentitan.c | 4 ++--
> hw/rx/rx-gdbsim.c | 4 ++--
> hw/s390x/ipl.c | 4 ++--
> hw/s390x/s390-virtio-ccw.c | 2 +-
> hw/tricore/triboard.c | 2 +-
> monitor/hmp-cmds-target.c | 4 ++--
> stats/stats-hmp-cmds.c | 2 +-
> system/cpus.c | 2 +-
> target/arm/arch_dump.c | 6 +++---
> target/i386/arch_dump.c | 6 +++---
> target/i386/kvm/kvm.c | 6 +++---
> target/i386/kvm/xen-emu.c | 15 ++++++++-------
> target/i386/monitor.c | 2 +-
> target/i386/tcg/sysemu/fpu_helper.c | 4 ++--
> target/mips/cpu.c | 2 +-
> target/mips/tcg/sysemu/cp0_helper.c | 10 +++++-----
> target/mips/tcg/sysemu/tlb_helper.c | 2 +-
> target/ppc/arch_dump.c | 4 ++--
> target/riscv/arch_dump.c | 4 ++--
> target/s390x/cpu_models.c | 10 +++++-----
> 86 files changed, 199 insertions(+), 163 deletions(-)
>
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type
2023-10-20 16:36 ` [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type Philippe Mathieu-Daudé
2023-10-20 17:14 ` Peter Maydell
@ 2023-10-23 14:21 ` Zhao Liu
2023-10-23 15:12 ` David Woodhouse
2 siblings, 0 replies; 27+ messages in thread
From: Zhao Liu @ 2023-10-23 14:21 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Thomas Huth, Richard Henderson, Paolo Bonzini,
Alistair Francis, qemu-arm, qemu-riscv, Edgar E. Iglesias,
qemu-ppc, Eduardo Habkost, Michael S. Tsirkin, qemu-s390x,
Peter Maydell, Alex Bennée, Andrey Smirnov,
Radoslaw Biernacki, Leif Lindholm, Marcin Juszkiewicz,
Shannon Zhao, Igor Mammedov, Ani Sinha, Alistair Francis,
David Woodhouse, Paul Durrant, Marcel Apfelbaum, Palmer Dabbelt,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Song Gao, Thomas Huth, Christian Borntraeger, Halil Pasic,
Eric Farman, David Hildenbrand, Ilya Leoshkevich, Yanan Wang,
Dr. David Alan Gilbert, Marcelo Tosatti, Aurelien Jarno,
Jiaxun Yang, Aleksandar Rikalo, Zhao Liu, kvm
Hi Philippe,
On Fri, Oct 20, 2023 at 06:36:23PM +0200, Philippe Mathieu-Daudé wrote:
> Date: Fri, 20 Oct 2023 18:36:23 +0200
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Subject: [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter
> CPUs by QOM type
> X-Mailer: git-send-email 2.41.0
>
> Heterogeneous machines have different type of CPU.
> qemu_get_cpu() returning unfiltered CPUs doesn't make
> sense anymore. Add a 'type' argument to filter CPU by
> QOM type.
>
> Type in "hw/core/cpu.h" and implementation in cpu-common.c
> modified manually, then convert all call sites by passing
> a NULL argument using the following coccinelle script:
>
> @@
> expression index;
> @@
> - qemu_get_cpu(index)
> + qemu_get_cpu(index, NULL)
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> RFC: Is this hot path code? What is the cost of this QOM cast check?
> ---
> include/hw/core/cpu.h | 3 ++-
> cpu-common.c | 5 ++++-
> hw/arm/boot.c | 2 +-
> hw/arm/fsl-imx7.c | 2 +-
> hw/arm/pxa2xx_gpio.c | 2 +-
> hw/arm/sbsa-ref.c | 4 ++--
> hw/arm/vexpress.c | 2 +-
> hw/arm/virt-acpi-build.c | 2 +-
> hw/arm/virt.c | 8 ++++----
> hw/arm/xlnx-versal-virt.c | 2 +-
> hw/core/generic-loader.c | 2 +-
> hw/cpu/a15mpcore.c | 4 ++--
> hw/cpu/a9mpcore.c | 2 +-
> hw/hyperv/hyperv.c | 2 +-
> hw/i386/kvm/xen_evtchn.c | 8 ++++----
> hw/intc/arm_gicv3_common.c | 2 +-
> hw/intc/arm_gicv3_cpuif.c | 2 +-
> hw/intc/arm_gicv3_kvm.c | 2 +-
> hw/intc/riscv_aclint.c | 2 +-
> hw/intc/sifive_plic.c | 4 ++--
> hw/loongarch/virt.c | 10 +++++-----
> hw/m68k/mcf5206.c | 2 +-
> hw/ppc/e500.c | 2 +-
> hw/ppc/ppce500_spin.c | 2 +-
> hw/riscv/boot.c | 2 +-
> hw/riscv/opentitan.c | 4 ++--
> hw/s390x/ipl.c | 2 +-
> hw/s390x/s390-virtio-ccw.c | 2 +-
> monitor/hmp-cmds-target.c | 4 ++--
> stats/stats-hmp-cmds.c | 2 +-
> system/cpus.c | 2 +-
> target/i386/kvm/xen-emu.c | 15 ++++++++-------
> target/i386/monitor.c | 2 +-
> target/mips/cpu.c | 2 +-
> target/mips/tcg/sysemu/cp0_helper.c | 2 +-
> target/s390x/cpu_models.c | 10 +++++-----
> 36 files changed, 66 insertions(+), 61 deletions(-)
>
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 12205b7882..2a6008dd96 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -903,12 +903,13 @@ static inline bool cpu_in_exclusive_context(const CPUState *cpu)
> /**
> * qemu_get_cpu:
> * @index: The CPUState@cpu_index value of the CPU to obtain.
The meaning of index needs to be clearly defined here, I understand that
on a heterogeneous machine, CPUs of different ISAs will be numbered from
0 respectively, i.e. CPU0 of type0 is numbered 0, CPU1 of type0 is
numbered 1, and CPU 2 of type1 is also numbered 0, CPU3 of tyoe1 is also
numbered 1, thus we need another "type" to differentiate between CPU0
and CPU2, and CPU1 and CPU3...Is my understanding correct?
If so, the change to the qemu_get_cpu() interface actually implies a
change in the meaning of "index"; in the context of the old
qemu_get_cpu(index), "index" looked to refer to the system wide index,
while in the context of the new qemu_get_cpu(index, type), "index"
becomes the sub index of a certain cluster range.
If future heterogeneous machines still use different clusters to
organize different ISA cores, can we consider introducing the
cluster_index/qemu_get_cluster_cpu(cluster_index, type)? This seems to
avoid the confusion caused by the different meanings of index in
symmetric and heterogeneous machines.
Regards,
Zhao
> + * @type: The QOM type to filter for, including its derivatives.
> *
> * Gets a CPU matching @index.
> *
> * Returns: The CPU or %NULL if there is no matching CPU.
> */
> -CPUState *qemu_get_cpu(int index);
> +CPUState *qemu_get_cpu(int index, const char *type);
>
> /**
> * cpu_exists:
> diff --git a/cpu-common.c b/cpu-common.c
> index c81fd72d16..e0d7f7e7e7 100644
> --- a/cpu-common.c
> +++ b/cpu-common.c
> @@ -107,11 +107,14 @@ void cpu_list_remove(CPUState *cpu)
> cpu_list_generation_id++;
> }
>
> -CPUState *qemu_get_cpu(int index)
> +CPUState *qemu_get_cpu(int index, const char *type)
> {
> CPUState *cpu;
>
> CPU_FOREACH(cpu) {
> + if (type && !object_dynamic_cast(OBJECT(cpu), type)) {
> + continue;
> + }
> if (cpu->cpu_index == index) {
> return cpu;
> }
> diff --git a/hw/arm/boot.c b/hw/arm/boot.c
> index 24fa169060..e260168cf5 100644
> --- a/hw/arm/boot.c
> +++ b/hw/arm/boot.c
> @@ -438,7 +438,7 @@ static void fdt_add_psci_node(void *fdt)
> uint32_t cpu_off_fn;
> uint32_t cpu_on_fn;
> uint32_t migrate_fn;
> - ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
> + ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0, NULL));
> const char *psci_method;
> int64_t psci_conduit;
> int rc;
> diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
> index 474cfdc87c..1c1585f3e1 100644
> --- a/hw/arm/fsl-imx7.c
> +++ b/hw/arm/fsl-imx7.c
> @@ -212,7 +212,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
>
> for (i = 0; i < smp_cpus; i++) {
> SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
> - DeviceState *d = DEVICE(qemu_get_cpu(i));
> + DeviceState *d = DEVICE(qemu_get_cpu(i, NULL));
>
> irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
> sysbus_connect_irq(sbd, i, irq);
> diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c
> index e7c3d99224..0a698171ab 100644
> --- a/hw/arm/pxa2xx_gpio.c
> +++ b/hw/arm/pxa2xx_gpio.c
> @@ -303,7 +303,7 @@ static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
> {
> PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
>
> - s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
> + s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu, NULL));
>
> qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
> qdev_init_gpio_out(dev, s->handler, s->lines);
> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> index 3c7dfcd6dc..3571d5038f 100644
> --- a/hw/arm/sbsa-ref.c
> +++ b/hw/arm/sbsa-ref.c
> @@ -275,7 +275,7 @@ static void create_fdt(SBSAMachineState *sms)
>
> for (cpu = sms->smp_cpus - 1; cpu >= 0; cpu--) {
> char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
> - ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
> + ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu, NULL));
> CPUState *cs = CPU(armcpu);
> uint64_t mpidr = sbsa_ref_cpu_mp_affinity(sms, cpu);
>
> @@ -478,7 +478,7 @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
> * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
> */
> for (i = 0; i < smp_cpus; i++) {
> - DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
> + DeviceState *cpudev = DEVICE(qemu_get_cpu(i, NULL));
> int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
> int irq;
> /*
> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
> index 8ff37f52ca..0590332fe5 100644
> --- a/hw/arm/vexpress.c
> +++ b/hw/arm/vexpress.c
> @@ -257,7 +257,7 @@ static void init_cpus(MachineState *ms, const char *cpu_type,
>
> /* Connect the CPUs to the GIC */
> for (n = 0; n < smp_cpus; n++) {
> - DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
> + DeviceState *cpudev = DEVICE(qemu_get_cpu(n, NULL));
>
> sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
> sysbus_connect_irq(busdev, n + smp_cpus,
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 6b674231c2..fd6c239c31 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -727,7 +727,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
> build_append_int_noprefix(table_data, 0, 3); /* Reserved */
>
> for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
> - ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
> + ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i, NULL));
> uint64_t physical_base_address = 0, gich = 0, gicv = 0;
> uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0;
> uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 15e74249f9..a8f9d88519 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -355,7 +355,7 @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
>
> qemu_fdt_add_subnode(ms->fdt, "/timer");
>
> - armcpu = ARM_CPU(qemu_get_cpu(0));
> + armcpu = ARM_CPU(qemu_get_cpu(0, NULL));
> if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
> const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
> qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
> @@ -394,7 +394,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
> * at least one of them has Aff3 populated, we set #address-cells to 2.
> */
> for (cpu = 0; cpu < smp_cpus; cpu++) {
> - ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
> + ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu, NULL));
>
> if (armcpu->mp_affinity & ARM_AFF3_MASK) {
> addr_cells = 2;
> @@ -408,7 +408,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
>
> for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
> char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
> - ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
> + ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu, NULL));
> CPUState *cs = CPU(armcpu);
>
> qemu_fdt_add_subnode(ms->fdt, nodename);
> @@ -799,7 +799,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
> * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
> */
> for (i = 0; i < smp_cpus; i++) {
> - DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
> + DeviceState *cpudev = DEVICE(qemu_get_cpu(i, NULL));
> int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
> /* Mapping from the output timer irq lines from the CPU to the
> * GIC PPI inputs we use for the virt board.
> diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
> index 88c561ff63..419ee3b882 100644
> --- a/hw/arm/xlnx-versal-virt.c
> +++ b/hw/arm/xlnx-versal-virt.c
> @@ -103,7 +103,7 @@ static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit)
>
> for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) {
> char *name = g_strdup_printf("/cpus/cpu@%d", i);
> - ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
> + ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i, NULL));
>
> qemu_fdt_add_subnode(s->fdt, name);
> qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity);
> diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
> index d4b5c501d8..98830ebd5b 100644
> --- a/hw/core/generic-loader.c
> +++ b/hw/core/generic-loader.c
> @@ -124,7 +124,7 @@ static void generic_loader_realize(DeviceState *dev, Error **errp)
> qemu_register_reset(generic_loader_reset, dev);
>
> if (s->cpu_num != CPU_NONE) {
> - s->cpu = qemu_get_cpu(s->cpu_num);
> + s->cpu = qemu_get_cpu(s->cpu_num, NULL);
> if (!s->cpu) {
> error_setg(errp, "Specified boot CPU#%d is nonexistent",
> s->cpu_num);
> diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
> index bfd8aa5644..8c9098d5d3 100644
> --- a/hw/cpu/a15mpcore.c
> +++ b/hw/cpu/a15mpcore.c
> @@ -65,7 +65,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
> /* Make the GIC's TZ support match the CPUs. We assume that
> * either all the CPUs have TZ, or none do.
> */
> - cpuobj = OBJECT(qemu_get_cpu(0));
> + cpuobj = OBJECT(qemu_get_cpu(0, NULL));
> has_el3 = object_property_find(cpuobj, "has_el3") &&
> object_property_get_bool(cpuobj, "has_el3", &error_abort);
> qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
> @@ -90,7 +90,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
> * appropriate GIC PPI inputs
> */
> for (i = 0; i < s->num_cpu; i++) {
> - DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
> + DeviceState *cpudev = DEVICE(qemu_get_cpu(i, NULL));
> int ppibase = s->num_irq - 32 + i * 32;
> int irq;
> /* Mapping from the output timer irq lines from the CPU to the
> diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
> index d03f57e579..62b7fb3836 100644
> --- a/hw/cpu/a9mpcore.c
> +++ b/hw/cpu/a9mpcore.c
> @@ -56,7 +56,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
> CPUState *cpu0;
> Object *cpuobj;
>
> - cpu0 = qemu_get_cpu(0);
> + cpu0 = qemu_get_cpu(0, NULL);
> cpuobj = OBJECT(cpu0);
> if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) {
> /* We might allow Cortex-A5 once we model it */
> diff --git a/hw/hyperv/hyperv.c b/hw/hyperv/hyperv.c
> index 57b402b956..a43f29ad8d 100644
> --- a/hw/hyperv/hyperv.c
> +++ b/hw/hyperv/hyperv.c
> @@ -226,7 +226,7 @@ struct HvSintRoute {
>
> static CPUState *hyperv_find_vcpu(uint32_t vp_index)
> {
> - CPUState *cs = qemu_get_cpu(vp_index);
> + CPUState *cs = qemu_get_cpu(vp_index, NULL);
> assert(hyperv_vp_index(cs) == vp_index);
> return cs;
> }
> diff --git a/hw/i386/kvm/xen_evtchn.c b/hw/i386/kvm/xen_evtchn.c
> index a731738411..de3650ba3b 100644
> --- a/hw/i386/kvm/xen_evtchn.c
> +++ b/hw/i386/kvm/xen_evtchn.c
> @@ -542,7 +542,7 @@ static void deassign_kernel_port(evtchn_port_t port)
> static int assign_kernel_port(uint16_t type, evtchn_port_t port,
> uint32_t vcpu_id)
> {
> - CPUState *cpu = qemu_get_cpu(vcpu_id);
> + CPUState *cpu = qemu_get_cpu(vcpu_id, NULL);
> struct kvm_xen_hvm_attr ha;
>
> if (!cpu) {
> @@ -589,7 +589,7 @@ static bool valid_port(evtchn_port_t port)
>
> static bool valid_vcpu(uint32_t vcpu)
> {
> - return !!qemu_get_cpu(vcpu);
> + return !!qemu_get_cpu(vcpu, NULL);
> }
>
> static void unbind_backend_ports(XenEvtchnState *s)
> @@ -917,7 +917,7 @@ static int set_port_pending(XenEvtchnState *s, evtchn_port_t port)
>
> if (s->evtchn_in_kernel) {
> XenEvtchnPort *p = &s->port_table[port];
> - CPUState *cpu = qemu_get_cpu(p->vcpu);
> + CPUState *cpu = qemu_get_cpu(p->vcpu, NULL);
> struct kvm_irq_routing_xen_evtchn evt;
>
> if (!cpu) {
> @@ -1779,7 +1779,7 @@ int xen_evtchn_translate_pirq_msi(struct kvm_irq_routing_entry *route,
> return -EINVAL;
> }
>
> - cpu = qemu_get_cpu(s->port_table[port].vcpu);
> + cpu = qemu_get_cpu(s->port_table[port].vcpu, NULL);
> if (!cpu) {
> return -EINVAL;
> }
> diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
> index 2ebf880ead..cdf21dfc11 100644
> --- a/hw/intc/arm_gicv3_common.c
> +++ b/hw/intc/arm_gicv3_common.c
> @@ -392,7 +392,7 @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
> s->cpu = g_new0(GICv3CPUState, s->num_cpu);
>
> for (i = 0; i < s->num_cpu; i++) {
> - CPUState *cpu = qemu_get_cpu(i);
> + CPUState *cpu = qemu_get_cpu(i, NULL);
> uint64_t cpu_affid;
>
> s->cpu[i].cpu = cpu;
> diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
> index d07b13eb27..f765b3d4b5 100644
> --- a/hw/intc/arm_gicv3_cpuif.c
> +++ b/hw/intc/arm_gicv3_cpuif.c
> @@ -2795,7 +2795,7 @@ void gicv3_init_cpuif(GICv3State *s)
> int i;
>
> for (i = 0; i < s->num_cpu; i++) {
> - ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
> + ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i, NULL));
> GICv3CPUState *cs = &s->cpu[i];
>
> /*
> diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
> index 72ad916d3d..d1ff9886aa 100644
> --- a/hw/intc/arm_gicv3_kvm.c
> +++ b/hw/intc/arm_gicv3_kvm.c
> @@ -808,7 +808,7 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
> gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
>
> for (i = 0; i < s->num_cpu; i++) {
> - ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
> + ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i, NULL));
>
> define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
> }
> diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
> index ab1a0b4b3a..a97c0449ec 100644
> --- a/hw/intc/riscv_aclint.c
> +++ b/hw/intc/riscv_aclint.c
> @@ -483,7 +483,7 @@ static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp)
>
> /* Claim software interrupt bits */
> for (i = 0; i < swi->num_harts; i++) {
> - RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i));
> + RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(swi->hartid_base + i, NULL));
> /* We don't claim mip.SSIP because it is writable by software */
> if (riscv_cpu_claim_interrupts(cpu, swi->sswi ? 0 : MIP_MSIP) < 0) {
> error_report("MSIP already claimed");
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index 5522ede2cf..a32e7f1924 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -392,7 +392,7 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
> * hardware controlled when a PLIC is attached.
> */
> for (i = 0; i < s->num_harts; i++) {
> - RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
> + RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i, NULL));
> if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
> error_setg(errp, "SEIP already claimed");
> return;
> @@ -499,7 +499,7 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
>
> for (i = 0; i < plic->num_addrs; i++) {
> int cpu_num = plic->addr_config[i].hartid;
> - CPUState *cpu = qemu_get_cpu(cpu_num);
> + CPUState *cpu = qemu_get_cpu(cpu_num, NULL);
>
> if (plic->addr_config[i].mode == PLICMode_M) {
> qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
> diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
> index 2952fe452e..e888aea892 100644
> --- a/hw/loongarch/virt.c
> +++ b/hw/loongarch/virt.c
> @@ -170,7 +170,7 @@ static void fdt_add_cpu_nodes(const LoongArchMachineState *lams)
> /* cpu nodes */
> for (num = smp_cpus - 1; num >= 0; num--) {
> char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
> - LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));
> + LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num, NULL));
> CPUState *cs = CPU(cpu);
>
> qemu_fdt_add_subnode(ms->fdt, nodename);
> @@ -560,7 +560,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
> * +--------+ +---------+ +---------+
> */
> for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
> - cpu_state = qemu_get_cpu(cpu);
> + cpu_state = qemu_get_cpu(cpu, NULL);
> cpudev = DEVICE(cpu_state);
> lacpu = LOONGARCH_CPU(cpu_state);
> env = &(lacpu->env);
> @@ -594,7 +594,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
> * cpu_pin[9:2] <= intc_pin[7:0]
> */
> for (cpu = 0; cpu < MIN(ms->smp.cpus, EXTIOI_CPUS); cpu++) {
> - cpudev = DEVICE(qemu_get_cpu(cpu));
> + cpudev = DEVICE(qemu_get_cpu(cpu, NULL));
> for (pin = 0; pin < LS3A_INTC_IP; pin++) {
> qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
> qdev_get_gpio_in(cpudev, pin + 2));
> @@ -726,7 +726,7 @@ static void loongarch_direct_kernel_boot(LoongArchMachineState *lams,
> kernel_addr = load_kernel_info(loaderparams);
> if (!machine->firmware) {
> for (i = 0; i < machine->smp.cpus; i++) {
> - lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
> + lacpu = LOONGARCH_CPU(qemu_get_cpu(i, NULL));
> lacpu->env.load_elf = true;
> lacpu->env.elf_address = kernel_addr;
> }
> @@ -859,7 +859,7 @@ static void loongarch_init(MachineState *machine)
> fdt_add_flash_node(lams);
> /* register reset function */
> for (i = 0; i < machine->smp.cpus; i++) {
> - lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
> + lacpu = LOONGARCH_CPU(qemu_get_cpu(i, NULL));
> qemu_register_reset(reset_load_elf, lacpu);
> }
> /* Initialize the IO interrupt subsystem */
> diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c
> index 2ab1b4f059..a0851f58a9 100644
> --- a/hw/m68k/mcf5206.c
> +++ b/hw/m68k/mcf5206.c
> @@ -601,7 +601,7 @@ static void mcf5206_mbar_realize(DeviceState *dev, Error **errp)
> s->timer[1] = m5206_timer_init(s->pic[10]);
> s->uart[0] = mcf_uart_init(s->pic[12], serial_hd(0));
> s->uart[1] = mcf_uart_init(s->pic[13], serial_hd(1));
> - s->cpu = M68K_CPU(qemu_get_cpu(0));
> + s->cpu = M68K_CPU(qemu_get_cpu(0, NULL));
> }
>
> static void mcf5206_mbar_class_init(ObjectClass *oc, void *data)
> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
> index e04114fb3c..380bbe1fe6 100644
> --- a/hw/ppc/e500.c
> +++ b/hw/ppc/e500.c
> @@ -495,7 +495,7 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
> char *cpu_name;
> uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20);
>
> - cpu = qemu_get_cpu(i);
> + cpu = qemu_get_cpu(i, NULL);
> if (cpu == NULL) {
> continue;
> }
> diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c
> index bbce63e8a4..3b113fbbdb 100644
> --- a/hw/ppc/ppce500_spin.c
> +++ b/hw/ppc/ppce500_spin.c
> @@ -125,7 +125,7 @@ static void spin_write(void *opaque, hwaddr addr, uint64_t value,
> SpinInfo *curspin = &s->spin[env_idx];
> uint8_t *curspin_p = (uint8_t*)curspin;
>
> - cpu = qemu_get_cpu(env_idx);
> + cpu = qemu_get_cpu(env_idx, NULL);
> if (cpu == NULL) {
> /* Unknown CPU */
> return;
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index 52bf8e67de..ea733b3df1 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -49,7 +49,7 @@ char *riscv_plic_hart_config_string(int hart_count)
> int i;
>
> for (i = 0; i < hart_count; i++) {
> - CPUState *cs = qemu_get_cpu(i);
> + CPUState *cs = qemu_get_cpu(i, NULL);
> CPURISCVState *env = &RISCV_CPU(cs)->env;
>
> if (kvm_enabled()) {
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 436503f1ba..e98361de19 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -190,7 +190,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
>
> for (i = 0; i < ms->smp.cpus; i++) {
> - CPUState *cpu = qemu_get_cpu(i);
> + CPUState *cpu = qemu_get_cpu(i, NULL);
>
> qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
> qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
> @@ -223,7 +223,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> 0, qdev_get_gpio_in(DEVICE(&s->plic),
> IBEX_TIMER_TIMEREXPIRED0_0));
> qdev_connect_gpio_out(DEVICE(&s->timer), 0,
> - qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
> + qdev_get_gpio_in(DEVICE(qemu_get_cpu(0, NULL)),
> IRQ_M_TIMER));
>
> /* SPI-Hosts */
> diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c
> index 515dcf51b5..14cd0a1f7b 100644
> --- a/hw/s390x/ipl.c
> +++ b/hw/s390x/ipl.c
> @@ -671,7 +671,7 @@ void s390_ipl_get_reset_request(CPUState **cs, enum s390_reset *reset_type)
> {
> S390IPLState *ipl = get_ipl_device();
>
> - *cs = qemu_get_cpu(ipl->reset_cpu_index);
> + *cs = qemu_get_cpu(ipl->reset_cpu_index, NULL);
> if (!*cs) {
> /* use any CPU */
> *cs = first_cpu;
> diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c
> index 2d75f2131f..7628b746a8 100644
> --- a/hw/s390x/s390-virtio-ccw.c
> +++ b/hw/s390x/s390-virtio-ccw.c
> @@ -583,7 +583,7 @@ static HotplugHandler *s390_get_hotplug_handler(MachineState *machine,
>
> static void s390_nmi(NMIState *n, int cpu_index, Error **errp)
> {
> - CPUState *cs = qemu_get_cpu(cpu_index);
> + CPUState *cs = qemu_get_cpu(cpu_index, NULL);
>
> s390_cpu_restart(S390_CPU(cs));
> }
> diff --git a/monitor/hmp-cmds-target.c b/monitor/hmp-cmds-target.c
> index d9fbcac08d..e501b997f8 100644
> --- a/monitor/hmp-cmds-target.c
> +++ b/monitor/hmp-cmds-target.c
> @@ -36,7 +36,7 @@ int monitor_set_cpu(Monitor *mon, int cpu_index)
> {
> CPUState *cpu;
>
> - cpu = qemu_get_cpu(cpu_index);
> + cpu = qemu_get_cpu(cpu_index, NULL);
> if (cpu == NULL) {
> return -1;
> }
> @@ -103,7 +103,7 @@ void hmp_info_registers(Monitor *mon, const QDict *qdict)
> cpu_dump_state(cs, NULL, CPU_DUMP_FPU);
> }
> } else {
> - cs = vcpu >= 0 ? qemu_get_cpu(vcpu) : mon_get_cpu(mon);
> + cs = vcpu >= 0 ? qemu_get_cpu(vcpu, NULL) : mon_get_cpu(mon);
>
> if (!cs) {
> if (vcpu >= 0) {
> diff --git a/stats/stats-hmp-cmds.c b/stats/stats-hmp-cmds.c
> index 1f91bf8bd5..0e58336c7f 100644
> --- a/stats/stats-hmp-cmds.c
> +++ b/stats/stats-hmp-cmds.c
> @@ -147,7 +147,7 @@ static StatsFilter *stats_filter(StatsTarget target, const char *names,
> case STATS_TARGET_VCPU:
> {
> strList *vcpu_list = NULL;
> - CPUState *cpu = qemu_get_cpu(cpu_index);
> + CPUState *cpu = qemu_get_cpu(cpu_index, NULL);
> char *canonical_path = object_get_canonical_path(OBJECT(cpu));
>
> QAPI_LIST_PREPEND(vcpu_list, canonical_path);
> diff --git a/system/cpus.c b/system/cpus.c
> index 0848e0dbdb..3e7c80e91b 100644
> --- a/system/cpus.c
> +++ b/system/cpus.c
> @@ -751,7 +751,7 @@ void qmp_memsave(int64_t addr, int64_t size, const char *filename,
> cpu_index = 0;
> }
>
> - cpu = qemu_get_cpu(cpu_index);
> + cpu = qemu_get_cpu(cpu_index, NULL);
> if (cpu == NULL) {
> error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "cpu-index",
> "a CPU number");
> diff --git a/target/i386/kvm/xen-emu.c b/target/i386/kvm/xen-emu.c
> index 76348f9d5d..f289af906c 100644
> --- a/target/i386/kvm/xen-emu.c
> +++ b/target/i386/kvm/xen-emu.c
> @@ -384,7 +384,7 @@ static void do_set_vcpu_info_gpa(CPUState *cs, run_on_cpu_data data)
>
> void *kvm_xen_get_vcpu_info_hva(uint32_t vcpu_id)
> {
> - CPUState *cs = qemu_get_cpu(vcpu_id);
> + CPUState *cs = qemu_get_cpu(vcpu_id, NULL);
> if (!cs) {
> return NULL;
> }
> @@ -418,7 +418,7 @@ void kvm_xen_maybe_deassert_callback(CPUState *cs)
>
> void kvm_xen_set_callback_asserted(void)
> {
> - CPUState *cs = qemu_get_cpu(0);
> + CPUState *cs = qemu_get_cpu(0, NULL);
>
> if (cs) {
> X86_CPU(cs)->env.xen_callback_asserted = true;
> @@ -427,7 +427,7 @@ void kvm_xen_set_callback_asserted(void)
>
> void kvm_xen_inject_vcpu_callback_vector(uint32_t vcpu_id, int type)
> {
> - CPUState *cs = qemu_get_cpu(vcpu_id);
> + CPUState *cs = qemu_get_cpu(vcpu_id, NULL);
> uint8_t vector;
>
> if (!cs) {
> @@ -491,7 +491,7 @@ static void do_set_vcpu_timer_virq(CPUState *cs, run_on_cpu_data data)
>
> int kvm_xen_set_vcpu_virq(uint32_t vcpu_id, uint16_t virq, uint16_t port)
> {
> - CPUState *cs = qemu_get_cpu(vcpu_id);
> + CPUState *cs = qemu_get_cpu(vcpu_id, NULL);
>
> if (!cs) {
> return -ENOENT;
> @@ -588,7 +588,7 @@ static int xen_set_shared_info(uint64_t gfn)
> trace_kvm_xen_set_shared_info(gfn);
>
> for (i = 0; i < XEN_LEGACY_MAX_VCPUS; i++) {
> - CPUState *cpu = qemu_get_cpu(i);
> + CPUState *cpu = qemu_get_cpu(i, NULL);
> if (cpu) {
> async_run_on_cpu(cpu, do_set_vcpu_info_default_gpa,
> RUN_ON_CPU_HOST_ULONG(gpa));
> @@ -834,7 +834,7 @@ static int kvm_xen_hcall_evtchn_upcall_vector(struct kvm_xen_exit *exit,
> return -EINVAL;
> }
>
> - target_cs = qemu_get_cpu(up.vcpu);
> + target_cs = qemu_get_cpu(up.vcpu, NULL);
> if (!target_cs) {
> return -EINVAL;
> }
> @@ -1160,7 +1160,8 @@ static bool kvm_xen_hcall_vcpu_op(struct kvm_xen_exit *exit, X86CPU *cpu,
> int cmd, int vcpu_id, uint64_t arg)
> {
> CPUState *cs = CPU(cpu);
> - CPUState *dest = cs->cpu_index == vcpu_id ? cs : qemu_get_cpu(vcpu_id);
> + CPUState *dest = cs->cpu_index == vcpu_id ? cs : qemu_get_cpu(vcpu_id,
> + NULL);
> int err;
>
> if (!dest) {
> diff --git a/target/i386/monitor.c b/target/i386/monitor.c
> index 6512846327..aca7be61dd 100644
> --- a/target/i386/monitor.c
> +++ b/target/i386/monitor.c
> @@ -592,7 +592,7 @@ void hmp_mce(Monitor *mon, const QDict *qdict)
> if (qdict_get_try_bool(qdict, "broadcast", false)) {
> flags |= MCE_INJECT_BROADCAST;
> }
> - cs = qemu_get_cpu(cpu_index);
> + cs = qemu_get_cpu(cpu_index, NULL);
> if (cs != NULL) {
> cpu = X86_CPU(cs);
> cpu_x86_inject_mce(mon, cpu, bank, status, mcg_status, addr, misc,
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index 83ee54f766..17e9e06a15 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -117,7 +117,7 @@ static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>
> void cpu_set_exception_base(int vp_index, target_ulong address)
> {
> - MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
> + MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index, NULL));
> vp->env.exception_base = address;
> }
>
> diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c
> index 5da1124589..fcaba37c40 100644
> --- a/target/mips/tcg/sysemu/cp0_helper.c
> +++ b/target/mips/tcg/sysemu/cp0_helper.c
> @@ -126,7 +126,7 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
> cs = env_cpu(env);
> vpe_idx = tc_idx / cs->nr_threads;
> *tc = tc_idx % cs->nr_threads;
> - other_cs = qemu_get_cpu(vpe_idx);
> + other_cs = qemu_get_cpu(vpe_idx, NULL);
> if (other_cs == NULL) {
> return env;
> }
> diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
> index b1e77b3a2b..4a44ee56a9 100644
> --- a/target/s390x/cpu_models.c
> +++ b/target/s390x/cpu_models.c
> @@ -150,7 +150,7 @@ uint32_t s390_get_hmfai(void)
> static S390CPU *cpu;
>
> if (!cpu) {
> - cpu = S390_CPU(qemu_get_cpu(0));
> + cpu = S390_CPU(qemu_get_cpu(0, NULL));
> }
>
> if (!cpu || !cpu->model) {
> @@ -164,7 +164,7 @@ uint8_t s390_get_mha_pow(void)
> static S390CPU *cpu;
>
> if (!cpu) {
> - cpu = S390_CPU(qemu_get_cpu(0));
> + cpu = S390_CPU(qemu_get_cpu(0, NULL));
> }
>
> if (!cpu || !cpu->model) {
> @@ -179,7 +179,7 @@ uint32_t s390_get_ibc_val(void)
> static S390CPU *cpu;
>
> if (!cpu) {
> - cpu = S390_CPU(qemu_get_cpu(0));
> + cpu = S390_CPU(qemu_get_cpu(0, NULL));
> }
>
> if (!cpu || !cpu->model) {
> @@ -199,7 +199,7 @@ void s390_get_feat_block(S390FeatType type, uint8_t *data)
> static S390CPU *cpu;
>
> if (!cpu) {
> - cpu = S390_CPU(qemu_get_cpu(0));
> + cpu = S390_CPU(qemu_get_cpu(0, NULL));
> }
>
> if (!cpu || !cpu->model) {
> @@ -213,7 +213,7 @@ bool s390_has_feat(S390Feat feat)
> static S390CPU *cpu;
>
> if (!cpu) {
> - cpu = S390_CPU(qemu_get_cpu(0));
> + cpu = S390_CPU(qemu_get_cpu(0, NULL));
> }
>
> if (!cpu || !cpu->model) {
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type
2023-10-20 16:36 ` [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type Philippe Mathieu-Daudé
2023-10-20 17:14 ` Peter Maydell
2023-10-23 14:21 ` Zhao Liu
@ 2023-10-23 15:12 ` David Woodhouse
2 siblings, 0 replies; 27+ messages in thread
From: David Woodhouse @ 2023-10-23 15:12 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Thomas Huth, Richard Henderson, Paolo Bonzini, Alistair Francis,
qemu-arm, qemu-riscv, Edgar E. Iglesias, qemu-ppc,
Eduardo Habkost, Michael S. Tsirkin, qemu-s390x, Peter Maydell,
Alex Bennée, Zhao Liu, Andrey Smirnov, Radoslaw Biernacki,
Leif Lindholm, Marcin Juszkiewicz, Shannon Zhao, Igor Mammedov,
Ani Sinha, Alistair Francis, Paul Durrant, Marcel Apfelbaum,
Palmer Dabbelt, Bin Meng, Weiwei Li, Daniel Henrique Barboza,
Liu Zhiwei, Song Gao, Thomas Huth, Christian Borntraeger,
Halil Pasic, Eric Farman, David Hildenbrand, Ilya Leoshkevich,
Yanan Wang, Dr. David Alan Gilbert, Marcelo Tosatti,
Aurelien Jarno, Jiaxun Yang, Aleksandar Rikalo, kvm
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On Fri, 2023-10-20 at 18:36 +0200, Philippe Mathieu-Daudé wrote:
> Heterogeneous machines have different type of CPU.
> qemu_get_cpu() returning unfiltered CPUs doesn't make
> sense anymore. Add a 'type' argument to filter CPU by
> QOM type.
>
> Type in "hw/core/cpu.h" and implementation in cpu-common.c
> modified manually, then convert all call sites by passing
> a NULL argument using the following coccinelle script:
>
> @@
> expression index;
> @@
> - qemu_get_cpu(index)
> + qemu_get_cpu(index, NULL)
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> RFC: Is this hot path code? What is the cost of this QOM cast check?
A bunch of them in the Xen emulation code are during interrupt
delivery. So yes, kind of hot path :)
In hw/i386/kvm/xen_evtchn.c I they're almost all just looking up a CPU
with qemu_get_cpu() so that they can call kvm_arch_vcpu_id() to get its
APIC ID. Mostly to send an MSI there or otherwise talk to the kernel
about it.
Perhaps it could keep a simple array of { vCPU ID, APIC ID } instead.
There's one case in valid_vcpu() where it's checking that a given vCPU
does exist, which could use that same array.
In target/i386/kvm/xen-emu.c there are some slow paths which are less
interesting (xen_set_shared_info(), kvm_xen_has_vcpu_callback_vector(),
kvm_xen_set_vcpu_virq(), kvm_xen_hcall_evtchn_upcall_vector()
kvm_xen_hcall_vcpu_op() does have a fast path (the singleshot timer
handling, although most guests seem to use a different hypercall for
that). But it doesn't actually call qemu_get_cpu() for that fast path
anyway, since it'll use the CPU it was *called* on.
kvm_xen_get_vcpu_info_hva() wants a pointer stored in cpu->env, and is
called in *one* fast path in xen_evtchn.c, again interrupt delivery (in
set_port_pending). But only in the case where we're running on an old
kernel and don't just ask the kernel to deliver the event. So I can
live with not optimising that.
kvm_xen_set_callback_asserted() is only for the case where event
channels are being delivered to the guest via emulated GSI, so not the
high-performance case. And I still do want to hook that up properly to
the ack on the *interrupt controllers* anyway (qv¹).
Finally, kvm_xen_injecft_vcpu_callback_vector() is also only for older
kernels where we don't ask the kernel to deliver the event.
tl;dr: we don't care about anything in xen.emu.c. So I think we could
live with just a fast lookup from vCPU# → APIC ID for the cases in
xen_evtchn.c.
¹ https://lore.kernel.org/all/70eb35a08a7c48993812b7f088fa9ae3f2c8b925.camel@infradead.org/T/
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^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2023-10-23 15:14 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-10-20 16:36 [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Philippe Mathieu-Daudé
2023-10-20 16:36 ` [RFC PATCH 01/19] cpus: Add argument to qemu_get_cpu() to filter CPUs by QOM type Philippe Mathieu-Daudé
2023-10-20 17:14 ` Peter Maydell
2023-10-20 17:29 ` Philippe Mathieu-Daudé
2023-10-20 17:40 ` Peter Maydell
2023-10-23 14:21 ` Zhao Liu
2023-10-23 15:12 ` David Woodhouse
2023-10-20 16:36 ` [PATCH 02/19] cpus: Filter for target specific CPU (generic) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 03/19] cpus: Filter for target specific CPU (arm) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 04/19] cpus: Filter for target specific CPU (loongarch) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 05/19] cpus: Filter for target specific CPU (mips) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 06/19] cpus: Filter for target specific CPU (s390x) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 07/19] cpus: Filter for target specific CPU (riscv) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 08/19] cpus: Filter for target specific CPU (ppc) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 09/19] cpus: Filter for target specific CPU (x86) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 10/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_ARM_CPU) Philippe Mathieu-Daudé
2023-10-20 16:53 ` Cédric Le Goater
2023-10-20 16:36 ` [PATCH 11/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_POWERPC_CPU) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 12/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_MIPS_CPU) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 13/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_M68K_CPU) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 14/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_S390X_CPU) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 15/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RISCV_CPU) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 16/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_TRICORE_CPU) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 17/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_SUPERH_CPU) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 18/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RX_CPU) Philippe Mathieu-Daudé
2023-10-20 16:36 ` [PATCH 19/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_X86_CPU) Philippe Mathieu-Daudé
2023-10-23 13:59 ` [PATCH 00/19] cpus: Step toward removing global 'first_cpu' Zhao Liu
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