From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: deller@gmx.de
Subject: [PATCH v2 23/65] target/hppa: Pass d to do_sub_cond
Date: Fri, 20 Oct 2023 13:42:49 -0700 [thread overview]
Message-ID: <20231020204331.139847-24-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org>
Hoist the resolution of d up one level above do_sub_cond.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 77 ++++++++++++++++++++++++++---------------
1 file changed, 49 insertions(+), 28 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index e84311d886..d480bac03d 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -446,12 +446,15 @@ static DisasCond cond_make_n(void)
};
}
-static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0)
+static DisasCond cond_make_tmp(TCGCond c, TCGv_reg a0, TCGv_reg a1)
{
assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS);
- return (DisasCond){
- .c = c, .a0 = a0, .a1 = tcg_constant_reg(0)
- };
+ return (DisasCond){ .c = c, .a0 = a0, .a1 = a1 };
+}
+
+static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0)
+{
+ return cond_make_tmp(c, a0, tcg_constant_reg(0));
}
static DisasCond cond_make_0(TCGCond c, TCGv_reg a0)
@@ -463,15 +466,12 @@ static DisasCond cond_make_0(TCGCond c, TCGv_reg a0)
static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1)
{
- DisasCond r = { .c = c };
+ TCGv_reg t0 = tcg_temp_new();
+ TCGv_reg t1 = tcg_temp_new();
- assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS);
- r.a0 = tcg_temp_new();
- tcg_gen_mov_reg(r.a0, a0);
- r.a1 = tcg_temp_new();
- tcg_gen_mov_reg(r.a1, a1);
-
- return r;
+ tcg_gen_mov_reg(t0, a0);
+ tcg_gen_mov_reg(t1, a1);
+ return cond_make_tmp(c, t0, t1);
}
static void cond_free(DisasCond *cond)
@@ -910,36 +910,55 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d,
can use the inputs directly. This can allow other computation to be
deleted as unused. */
-static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, TCGv_reg res,
- TCGv_reg in1, TCGv_reg in2, TCGv_reg sv)
+static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d,
+ TCGv_reg res, TCGv_reg in1,
+ TCGv_reg in2, TCGv_reg sv)
{
- DisasCond cond;
- bool d = false;
+ TCGCond tc;
+ bool ext_uns;
switch (cf >> 1) {
case 1: /* = / <> */
- cond = cond_make(TCG_COND_EQ, in1, in2);
+ tc = TCG_COND_EQ;
+ ext_uns = true;
break;
case 2: /* < / >= */
- cond = cond_make(TCG_COND_LT, in1, in2);
+ tc = TCG_COND_LT;
+ ext_uns = false;
break;
case 3: /* <= / > */
- cond = cond_make(TCG_COND_LE, in1, in2);
+ tc = TCG_COND_LE;
+ ext_uns = false;
break;
case 4: /* << / >>= */
- cond = cond_make(TCG_COND_LTU, in1, in2);
+ tc = TCG_COND_LTU;
+ ext_uns = true;
break;
case 5: /* <<= / >> */
- cond = cond_make(TCG_COND_LEU, in1, in2);
+ tc = TCG_COND_LEU;
+ ext_uns = true;
break;
default:
return do_cond(ctx, cf, d, res, NULL, sv);
}
- if (cf & 1) {
- cond.c = tcg_invert_cond(cond.c);
- }
- return cond;
+ if (cf & 1) {
+ tc = tcg_invert_cond(tc);
+ }
+ if (cond_need_ext(ctx, d)) {
+ TCGv_reg t1 = tcg_temp_new();
+ TCGv_reg t2 = tcg_temp_new();
+
+ if (ext_uns) {
+ tcg_gen_ext32u_reg(t1, in1);
+ tcg_gen_ext32u_reg(t2, in2);
+ } else {
+ tcg_gen_ext32s_reg(t1, in1);
+ tcg_gen_ext32s_reg(t2, in2);
+ }
+ return cond_make_tmp(tc, t1, t2);
+ }
+ return cond_make(tc, in1, in2);
}
/*
@@ -1267,7 +1286,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
/* Compute the condition. We cannot use the special case for borrow. */
if (!is_b) {
- cond = do_sub_cond(ctx, cf, dest, in1, in2, sv);
+ cond = do_sub_cond(ctx, cf, d, dest, in1, in2, sv);
} else {
cond = do_cond(ctx, cf, d, dest, get_carry(ctx, d, cb, cb_msb), sv);
}
@@ -1321,6 +1340,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1,
{
TCGv_reg dest, sv;
DisasCond cond;
+ bool d = false;
dest = tcg_temp_new();
tcg_gen_sub_reg(dest, in1, in2);
@@ -1332,7 +1352,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1,
}
/* Form the condition for the compare. */
- cond = do_sub_cond(ctx, cf, dest, in1, in2, sv);
+ cond = do_sub_cond(ctx, cf, d, dest, in1, in2, sv);
/* Clear. */
tcg_gen_movi_reg(dest, 0);
@@ -3028,6 +3048,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1,
{
TCGv_reg dest, in2, sv;
DisasCond cond;
+ bool d = false;
in2 = load_gpr(ctx, r);
dest = tcg_temp_new();
@@ -3039,7 +3060,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1,
sv = do_sub_sv(ctx, dest, in1, in2);
}
- cond = do_sub_cond(ctx, c * 2 + f, dest, in1, in2, sv);
+ cond = do_sub_cond(ctx, c * 2 + f, d, dest, in1, in2, sv);
return do_cbranch(ctx, disp, n, &cond);
}
--
2.34.1
next prev parent reply other threads:[~2023-10-20 20:45 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-20 20:42 [PATCH v2 00/65] target/hppa: Implement hppa64-cpu Richard Henderson
2023-10-20 20:42 ` [PATCH v2 01/65] tcg: Improve expansion of deposit of constant Richard Henderson
2023-10-20 20:42 ` [PATCH v2 02/65] tcg: Improve expansion of deposit into a constant Richard Henderson
2023-10-20 20:42 ` [PATCH v2 03/65] target/hppa: Remove get_temp Richard Henderson
2023-10-20 20:42 ` [PATCH v2 04/65] target/hppa: Remove get_temp_tl Richard Henderson
2023-10-20 20:42 ` [PATCH v2 05/65] target/hppa: Remove load_const Richard Henderson
2023-10-20 21:15 ` Philippe Mathieu-Daudé
2023-10-20 20:42 ` [PATCH v2 06/65] target/hppa: Fix hppa64 case in machine.c Richard Henderson
2023-10-20 20:42 ` [PATCH v2 07/65] target/hppa: Fix load in do_load_32 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 08/65] target/hppa: Truncate rotate count in trans_shrpw_sar Richard Henderson
2023-10-20 20:42 ` [PATCH v2 09/65] target/hppa: Fix trans_ds for hppa64 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 10/65] target/hppa: Fix do_add, do_sub " Richard Henderson
2023-10-20 20:42 ` [PATCH v2 11/65] target/hppa: Fix bb_sar " Richard Henderson
2023-10-20 20:42 ` [PATCH v2 12/65] target/hppa: Fix extrw and depw with sar " Richard Henderson
2023-10-20 20:42 ` [PATCH v2 13/65] target/hppa: Introduce TYPE_HPPA64_CPU Richard Henderson
2023-10-20 21:19 ` Philippe Mathieu-Daudé
2023-10-20 20:42 ` [PATCH v2 14/65] target/hppa: Make HPPA_BTLB_ENTRIES variable Richard Henderson
2023-10-20 20:42 ` [PATCH v2 15/65] target/hppa: Implement cpu_list Richard Henderson
2023-10-20 20:42 ` [PATCH v2 16/65] target/hppa: Implement hppa_cpu_class_by_name Richard Henderson
2023-10-20 20:42 ` [PATCH v2 17/65] target/hppa: Update cpu_hppa_get/put_psw for hppa64 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 18/65] target/hppa: Handle absolute addresses for pa2.0 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 19/65] target/hppa: Adjust hppa_cpu_dump_state for hppa64 Richard Henderson
2023-10-20 21:35 ` Philippe Mathieu-Daudé
2023-10-20 20:42 ` [PATCH v2 20/65] target/hppa: Fix hppa64 addressing Richard Henderson
2023-10-20 20:42 ` [PATCH v2 21/65] target/hppa: sar register allows only 5 bits on 32-bit CPU Richard Henderson
2023-10-20 20:42 ` [PATCH v2 22/65] target/hppa: Pass d to do_cond Richard Henderson
2023-10-20 20:42 ` Richard Henderson [this message]
2023-10-20 20:42 ` [PATCH v2 24/65] target/hppa: Pass d to do_log_cond Richard Henderson
2023-10-20 20:42 ` [PATCH v2 25/65] target/hppa: Pass d to do_sed_cond Richard Henderson
2023-10-20 20:42 ` [PATCH v2 26/65] target/hppa: Pass d to do_unit_cond Richard Henderson
2023-10-20 20:42 ` [PATCH v2 27/65] linux-user/hppa: Fixes for TARGET_ABI32 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 28/65] target/hppa: Drop attempted gdbstub support for hppa64 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 29/65] target/hppa: Remove TARGET_HPPA64 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 30/65] target/hppa: Decode d for logical instructions Richard Henderson
2023-10-20 20:42 ` [PATCH v2 31/65] target/hppa: Decode d for unit instructions Richard Henderson
2023-10-20 20:42 ` [PATCH v2 32/65] target/hppa: Decode d for cmpclr instructions Richard Henderson
2023-10-20 20:42 ` [PATCH v2 33/65] target/hppa: Decode d for add instructions Richard Henderson
2023-10-20 20:43 ` [PATCH v2 34/65] target/hppa: Decode d for sub instructions Richard Henderson
2023-10-20 20:43 ` [PATCH v2 35/65] target/hppa: Decode d for bb instructions Richard Henderson
2023-10-20 20:43 ` [PATCH v2 36/65] target/hppa: Decode d for cmpb instructions Richard Henderson
2023-10-20 20:43 ` [PATCH v2 37/65] target/hppa: Decode CMPIB double-word Richard Henderson
2023-10-20 20:43 ` [PATCH v2 38/65] target/hppa: Decode ADDB double-word Richard Henderson
2023-10-20 20:43 ` [PATCH v2 39/65] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA Richard Henderson
2023-10-20 20:43 ` [PATCH v2 40/65] target/hppa: Implement DEPD, DEPDI Richard Henderson
2023-10-20 20:43 ` [PATCH v2 41/65] target/hppa: Implement EXTRD Richard Henderson
2023-10-20 20:43 ` [PATCH v2 42/65] target/hppa: Implement SHRPD Richard Henderson
2023-10-20 20:43 ` [PATCH v2 43/65] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM Richard Henderson
2023-10-20 20:43 ` [PATCH v2 44/65] target/hppa: Implement STDBY Richard Henderson
2023-10-20 20:43 ` [PATCH v2 45/65] target/hppa: Implement IDTLBT, IITLBT Richard Henderson
2023-10-20 20:43 ` [PATCH v2 46/65] hw/hppa: Use uint32_t instead of target_ureg Richard Henderson
2023-10-20 21:34 ` Philippe Mathieu-Daudé
2023-10-20 20:43 ` [PATCH v2 47/65] target/hppa: Remove TARGET_REGISTER_BITS Richard Henderson
2023-10-20 21:31 ` Philippe Mathieu-Daudé
2023-10-26 16:59 ` Richard Henderson
2023-10-20 20:43 ` [PATCH v2 48/65] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections Richard Henderson
2023-10-20 20:43 ` [PATCH v2 49/65] target/hppa: Remove remaining " Richard Henderson
2023-10-20 20:43 ` [PATCH v2 50/65] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new Richard Henderson
2023-10-20 20:43 ` [PATCH v2 51/65] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 Richard Henderson
2023-10-20 20:43 ` [PATCH v2 52/65] target/hppa: Implement HADD Richard Henderson
2023-10-20 20:43 ` [PATCH v2 53/65] target/hppa: Implement HSUB Richard Henderson
2023-10-20 20:43 ` [PATCH v2 54/65] target/hppa: Implement HAVG Richard Henderson
2023-10-20 20:43 ` [PATCH v2 55/65] target/hppa: Implement HSHL, HSHR Richard Henderson
2023-10-20 20:43 ` [PATCH v2 56/65] target/hppa: Implement HSHLADD, HSHRADD Richard Henderson
2023-10-20 20:43 ` [PATCH v2 57/65] target/hppa: Implement MIXH, MIXW Richard Henderson
2023-10-20 20:43 ` [PATCH v2 58/65] target/hppa: Implement PERMH Richard Henderson
2023-10-20 20:43 ` [PATCH v2 59/65] target/hppa: Fix interruption based on default PSW Richard Henderson
2023-10-20 20:43 ` [PATCH v2 60/65] target/hppa: Precompute zero into DisasContext Richard Henderson
2023-10-20 21:32 ` Philippe Mathieu-Daudé
2023-10-20 20:43 ` [PATCH v2 61/65] target/hppa: Return zero for r0 from load_gpr Richard Henderson
2023-10-20 21:32 ` Philippe Mathieu-Daudé
2023-10-20 20:43 ` [PATCH v2 62/65] target/hppa: Simplify trans_dep*_imm Richard Henderson
2023-10-20 20:43 ` [PATCH v2 63/65] include/hw/elf: Remove truncating signed casts Richard Henderson
2023-10-20 20:43 ` [PATCH v2 64/65] hw/hppa: Translate phys addresses for the cpu Richard Henderson
2023-10-20 20:43 ` [PATCH v2 65/65] linux-user/hppa: Drop EXCP_DUMP from handled exceptions Richard Henderson
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