From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: deller@gmx.de
Subject: [PATCH v2 02/65] tcg: Improve expansion of deposit into a constant
Date: Fri, 20 Oct 2023 13:42:28 -0700 [thread overview]
Message-ID: <20231020204331.139847-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org>
Generalize tcg_gen_deposit_z_* from 0 to any constant.
Use this to automatically simplify tcg_gen_deposit_*.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.c | 295 ++++++++++++++++++++++++++++++---------------------
1 file changed, 174 insertions(+), 121 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 2ef4b866e2..049b684ccc 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -597,6 +597,70 @@ void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
}
}
+static void tcg_gen_deposit_i_i32(TCGv_i32 ret, uint32_t i, TCGv_i32 arg,
+ unsigned int ofs, unsigned int len)
+{
+ i = deposit32(i, ofs, len, 0);
+
+ if (ofs + len == 32) {
+ tcg_gen_shli_i32(ret, arg, ofs);
+ goto finish;
+ }
+ if (ofs == 0) {
+ tcg_gen_andi_i32(ret, arg, (1u << len) - 1);
+ goto finish;
+ }
+ if (TCG_TARGET_HAS_deposit_i32
+ && TCG_TARGET_deposit_i32_valid(ofs, len)) {
+ tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret,
+ tcg_constant_i32(i), arg, ofs, len);
+ return;
+ }
+
+ /*
+ * To help two-operand hosts we prefer to zero-extend first,
+ * which allows ARG to stay live.
+ */
+ switch (len) {
+ case 16:
+ if (TCG_TARGET_HAS_ext16u_i32) {
+ tcg_gen_ext16u_i32(ret, arg);
+ tcg_gen_shli_i32(ret, ret, ofs);
+ goto finish;
+ }
+ break;
+ case 8:
+ if (TCG_TARGET_HAS_ext8u_i32) {
+ tcg_gen_ext8u_i32(ret, arg);
+ tcg_gen_shli_i32(ret, ret, ofs);
+ goto finish;
+ }
+ break;
+ }
+ /* Otherwise prefer zero-extension over AND for code size. */
+ switch (ofs + len) {
+ case 16:
+ if (TCG_TARGET_HAS_ext16u_i32) {
+ tcg_gen_shli_i32(ret, arg, ofs);
+ tcg_gen_ext16u_i32(ret, ret);
+ goto finish;
+ }
+ break;
+ case 8:
+ if (TCG_TARGET_HAS_ext8u_i32) {
+ tcg_gen_shli_i32(ret, arg, ofs);
+ tcg_gen_ext8u_i32(ret, ret);
+ goto finish;
+ }
+ break;
+ }
+ tcg_gen_andi_i32(ret, arg, (1u << len) - 1);
+ tcg_gen_shli_i32(ret, ret, ofs);
+
+ finish:
+ tcg_gen_ori_i32(ret, ret, i);
+}
+
void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
unsigned int ofs, unsigned int len)
{
@@ -613,6 +677,14 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
tcg_gen_mov_i32(ret, arg2);
return;
}
+
+ /* Deposit of a value into a constant. */
+ ts = tcgv_i32_temp(arg1);
+ if (ts->kind == TEMP_CONST) {
+ tcg_gen_deposit_i_i32(ret, ts->val, arg2, ofs, len);
+ return;
+ }
+
if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) {
tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
return;
@@ -667,53 +739,7 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
tcg_debug_assert(len <= 32);
tcg_debug_assert(ofs + len <= 32);
- if (ofs + len == 32) {
- tcg_gen_shli_i32(ret, arg, ofs);
- } else if (ofs == 0) {
- tcg_gen_andi_i32(ret, arg, (1u << len) - 1);
- } else if (TCG_TARGET_HAS_deposit_i32
- && TCG_TARGET_deposit_i32_valid(ofs, len)) {
- TCGv_i32 zero = tcg_constant_i32(0);
- tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, zero, arg, ofs, len);
- } else {
- /* To help two-operand hosts we prefer to zero-extend first,
- which allows ARG to stay live. */
- switch (len) {
- case 16:
- if (TCG_TARGET_HAS_ext16u_i32) {
- tcg_gen_ext16u_i32(ret, arg);
- tcg_gen_shli_i32(ret, ret, ofs);
- return;
- }
- break;
- case 8:
- if (TCG_TARGET_HAS_ext8u_i32) {
- tcg_gen_ext8u_i32(ret, arg);
- tcg_gen_shli_i32(ret, ret, ofs);
- return;
- }
- break;
- }
- /* Otherwise prefer zero-extension over AND for code size. */
- switch (ofs + len) {
- case 16:
- if (TCG_TARGET_HAS_ext16u_i32) {
- tcg_gen_shli_i32(ret, arg, ofs);
- tcg_gen_ext16u_i32(ret, ret);
- return;
- }
- break;
- case 8:
- if (TCG_TARGET_HAS_ext8u_i32) {
- tcg_gen_shli_i32(ret, arg, ofs);
- tcg_gen_ext8u_i32(ret, ret);
- return;
- }
- break;
- }
- tcg_gen_andi_i32(ret, arg, (1u << len) - 1);
- tcg_gen_shli_i32(ret, ret, ofs);
- }
+ tcg_gen_deposit_i_i32(ret, 0, arg, ofs, len);
}
void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
@@ -2226,6 +2252,98 @@ void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
}
}
+static void tcg_gen_deposit_i_i64(TCGv_i64 ret, uint64_t i, TCGv_i64 arg,
+ unsigned int ofs, unsigned int len)
+{
+ i = deposit64(i, ofs, len, 0);
+
+ if (ofs + len == 64) {
+ tcg_gen_shli_i64(ret, arg, ofs);
+ goto finish;
+ }
+ if (ofs == 0) {
+ tcg_gen_andi_i64(ret, arg, (1ull << len) - 1);
+ goto finish;
+ }
+ if (TCG_TARGET_HAS_deposit_i64
+ && TCG_TARGET_deposit_i64_valid(ofs, len)) {
+ tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret,
+ tcg_constant_i64(i), arg, ofs, len);
+ return;
+ }
+
+ if (TCG_TARGET_REG_BITS == 32) {
+ if (ofs >= 32) {
+ tcg_gen_deposit_i_i32(TCGV_HIGH(ret), i >> 32,
+ TCGV_LOW(arg), ofs - 32, len);
+ tcg_gen_movi_i32(TCGV_LOW(ret), i);
+ return;
+ }
+ if (ofs + len <= 32) {
+ tcg_gen_deposit_i_i32(TCGV_LOW(ret), i, TCGV_LOW(arg), ofs, len);
+ tcg_gen_movi_i32(TCGV_HIGH(ret), i >> 32);
+ return;
+ }
+ }
+
+ /*
+ * To help two-operand hosts we prefer to zero-extend first,
+ * which allows ARG to stay live.
+ */
+ switch (len) {
+ case 32:
+ if (TCG_TARGET_HAS_ext32u_i64) {
+ tcg_gen_ext32u_i64(ret, arg);
+ tcg_gen_shli_i64(ret, ret, ofs);
+ goto finish;
+ }
+ break;
+ case 16:
+ if (TCG_TARGET_HAS_ext16u_i64) {
+ tcg_gen_ext16u_i64(ret, arg);
+ tcg_gen_shli_i64(ret, ret, ofs);
+ goto finish;
+ }
+ break;
+ case 8:
+ if (TCG_TARGET_HAS_ext8u_i64) {
+ tcg_gen_ext8u_i64(ret, arg);
+ tcg_gen_shli_i64(ret, ret, ofs);
+ goto finish;
+ }
+ break;
+ }
+ /* Otherwise prefer zero-extension over AND for code size. */
+ switch (ofs + len) {
+ case 32:
+ if (TCG_TARGET_HAS_ext32u_i64) {
+ tcg_gen_shli_i64(ret, arg, ofs);
+ tcg_gen_ext32u_i64(ret, ret);
+ goto finish;
+ }
+ break;
+ case 16:
+ if (TCG_TARGET_HAS_ext16u_i64) {
+ tcg_gen_shli_i64(ret, arg, ofs);
+ tcg_gen_ext16u_i64(ret, ret);
+ goto finish;
+ }
+ break;
+ case 8:
+ if (TCG_TARGET_HAS_ext8u_i64) {
+ tcg_gen_shli_i64(ret, arg, ofs);
+ tcg_gen_ext8u_i64(ret, ret);
+ goto finish;
+ }
+ break;
+ }
+ tcg_gen_andi_i64(ret, arg, (1ull << len) - 1);
+ tcg_gen_shli_i64(ret, ret, ofs);
+
+ finish:
+ tcg_gen_ori_i64(ret, ret, i);
+}
+
void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
unsigned int ofs, unsigned int len)
{
@@ -2242,6 +2360,14 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
tcg_gen_mov_i64(ret, arg2);
return;
}
+
+ /* Deposit of a value into a constant. */
+ ts = tcgv_i64_temp(arg1);
+ if (ts->kind == TEMP_CONST) {
+ tcg_gen_deposit_i_i64(ret, ts->val, arg2, ofs, len);
+ return;
+ }
+
if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) {
tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
return;
@@ -2311,80 +2437,7 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
tcg_debug_assert(len <= 64);
tcg_debug_assert(ofs + len <= 64);
- if (ofs + len == 64) {
- tcg_gen_shli_i64(ret, arg, ofs);
- } else if (ofs == 0) {
- tcg_gen_andi_i64(ret, arg, (1ull << len) - 1);
- } else if (TCG_TARGET_HAS_deposit_i64
- && TCG_TARGET_deposit_i64_valid(ofs, len)) {
- TCGv_i64 zero = tcg_constant_i64(0);
- tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, zero, arg, ofs, len);
- } else {
- if (TCG_TARGET_REG_BITS == 32) {
- if (ofs >= 32) {
- tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg),
- ofs - 32, len);
- tcg_gen_movi_i32(TCGV_LOW(ret), 0);
- return;
- }
- if (ofs + len <= 32) {
- tcg_gen_deposit_z_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len);
- tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
- return;
- }
- }
- /* To help two-operand hosts we prefer to zero-extend first,
- which allows ARG to stay live. */
- switch (len) {
- case 32:
- if (TCG_TARGET_HAS_ext32u_i64) {
- tcg_gen_ext32u_i64(ret, arg);
- tcg_gen_shli_i64(ret, ret, ofs);
- return;
- }
- break;
- case 16:
- if (TCG_TARGET_HAS_ext16u_i64) {
- tcg_gen_ext16u_i64(ret, arg);
- tcg_gen_shli_i64(ret, ret, ofs);
- return;
- }
- break;
- case 8:
- if (TCG_TARGET_HAS_ext8u_i64) {
- tcg_gen_ext8u_i64(ret, arg);
- tcg_gen_shli_i64(ret, ret, ofs);
- return;
- }
- break;
- }
- /* Otherwise prefer zero-extension over AND for code size. */
- switch (ofs + len) {
- case 32:
- if (TCG_TARGET_HAS_ext32u_i64) {
- tcg_gen_shli_i64(ret, arg, ofs);
- tcg_gen_ext32u_i64(ret, ret);
- return;
- }
- break;
- case 16:
- if (TCG_TARGET_HAS_ext16u_i64) {
- tcg_gen_shli_i64(ret, arg, ofs);
- tcg_gen_ext16u_i64(ret, ret);
- return;
- }
- break;
- case 8:
- if (TCG_TARGET_HAS_ext8u_i64) {
- tcg_gen_shli_i64(ret, arg, ofs);
- tcg_gen_ext8u_i64(ret, ret);
- return;
- }
- break;
- }
- tcg_gen_andi_i64(ret, arg, (1ull << len) - 1);
- tcg_gen_shli_i64(ret, ret, ofs);
- }
+ tcg_gen_deposit_i_i64(ret, 0, arg, ofs, len);
}
void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
--
2.34.1
next prev parent reply other threads:[~2023-10-20 20:44 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-20 20:42 [PATCH v2 00/65] target/hppa: Implement hppa64-cpu Richard Henderson
2023-10-20 20:42 ` [PATCH v2 01/65] tcg: Improve expansion of deposit of constant Richard Henderson
2023-10-20 20:42 ` Richard Henderson [this message]
2023-10-20 20:42 ` [PATCH v2 03/65] target/hppa: Remove get_temp Richard Henderson
2023-10-20 20:42 ` [PATCH v2 04/65] target/hppa: Remove get_temp_tl Richard Henderson
2023-10-20 20:42 ` [PATCH v2 05/65] target/hppa: Remove load_const Richard Henderson
2023-10-20 21:15 ` Philippe Mathieu-Daudé
2023-10-20 20:42 ` [PATCH v2 06/65] target/hppa: Fix hppa64 case in machine.c Richard Henderson
2023-10-20 20:42 ` [PATCH v2 07/65] target/hppa: Fix load in do_load_32 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 08/65] target/hppa: Truncate rotate count in trans_shrpw_sar Richard Henderson
2023-10-20 20:42 ` [PATCH v2 09/65] target/hppa: Fix trans_ds for hppa64 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 10/65] target/hppa: Fix do_add, do_sub " Richard Henderson
2023-10-20 20:42 ` [PATCH v2 11/65] target/hppa: Fix bb_sar " Richard Henderson
2023-10-20 20:42 ` [PATCH v2 12/65] target/hppa: Fix extrw and depw with sar " Richard Henderson
2023-10-20 20:42 ` [PATCH v2 13/65] target/hppa: Introduce TYPE_HPPA64_CPU Richard Henderson
2023-10-20 21:19 ` Philippe Mathieu-Daudé
2023-10-20 20:42 ` [PATCH v2 14/65] target/hppa: Make HPPA_BTLB_ENTRIES variable Richard Henderson
2023-10-20 20:42 ` [PATCH v2 15/65] target/hppa: Implement cpu_list Richard Henderson
2023-10-20 20:42 ` [PATCH v2 16/65] target/hppa: Implement hppa_cpu_class_by_name Richard Henderson
2023-10-20 20:42 ` [PATCH v2 17/65] target/hppa: Update cpu_hppa_get/put_psw for hppa64 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 18/65] target/hppa: Handle absolute addresses for pa2.0 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 19/65] target/hppa: Adjust hppa_cpu_dump_state for hppa64 Richard Henderson
2023-10-20 21:35 ` Philippe Mathieu-Daudé
2023-10-20 20:42 ` [PATCH v2 20/65] target/hppa: Fix hppa64 addressing Richard Henderson
2023-10-20 20:42 ` [PATCH v2 21/65] target/hppa: sar register allows only 5 bits on 32-bit CPU Richard Henderson
2023-10-20 20:42 ` [PATCH v2 22/65] target/hppa: Pass d to do_cond Richard Henderson
2023-10-20 20:42 ` [PATCH v2 23/65] target/hppa: Pass d to do_sub_cond Richard Henderson
2023-10-20 20:42 ` [PATCH v2 24/65] target/hppa: Pass d to do_log_cond Richard Henderson
2023-10-20 20:42 ` [PATCH v2 25/65] target/hppa: Pass d to do_sed_cond Richard Henderson
2023-10-20 20:42 ` [PATCH v2 26/65] target/hppa: Pass d to do_unit_cond Richard Henderson
2023-10-20 20:42 ` [PATCH v2 27/65] linux-user/hppa: Fixes for TARGET_ABI32 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 28/65] target/hppa: Drop attempted gdbstub support for hppa64 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 29/65] target/hppa: Remove TARGET_HPPA64 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 30/65] target/hppa: Decode d for logical instructions Richard Henderson
2023-10-20 20:42 ` [PATCH v2 31/65] target/hppa: Decode d for unit instructions Richard Henderson
2023-10-20 20:42 ` [PATCH v2 32/65] target/hppa: Decode d for cmpclr instructions Richard Henderson
2023-10-20 20:42 ` [PATCH v2 33/65] target/hppa: Decode d for add instructions Richard Henderson
2023-10-20 20:43 ` [PATCH v2 34/65] target/hppa: Decode d for sub instructions Richard Henderson
2023-10-20 20:43 ` [PATCH v2 35/65] target/hppa: Decode d for bb instructions Richard Henderson
2023-10-20 20:43 ` [PATCH v2 36/65] target/hppa: Decode d for cmpb instructions Richard Henderson
2023-10-20 20:43 ` [PATCH v2 37/65] target/hppa: Decode CMPIB double-word Richard Henderson
2023-10-20 20:43 ` [PATCH v2 38/65] target/hppa: Decode ADDB double-word Richard Henderson
2023-10-20 20:43 ` [PATCH v2 39/65] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA Richard Henderson
2023-10-20 20:43 ` [PATCH v2 40/65] target/hppa: Implement DEPD, DEPDI Richard Henderson
2023-10-20 20:43 ` [PATCH v2 41/65] target/hppa: Implement EXTRD Richard Henderson
2023-10-20 20:43 ` [PATCH v2 42/65] target/hppa: Implement SHRPD Richard Henderson
2023-10-20 20:43 ` [PATCH v2 43/65] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM Richard Henderson
2023-10-20 20:43 ` [PATCH v2 44/65] target/hppa: Implement STDBY Richard Henderson
2023-10-20 20:43 ` [PATCH v2 45/65] target/hppa: Implement IDTLBT, IITLBT Richard Henderson
2023-10-20 20:43 ` [PATCH v2 46/65] hw/hppa: Use uint32_t instead of target_ureg Richard Henderson
2023-10-20 21:34 ` Philippe Mathieu-Daudé
2023-10-20 20:43 ` [PATCH v2 47/65] target/hppa: Remove TARGET_REGISTER_BITS Richard Henderson
2023-10-20 21:31 ` Philippe Mathieu-Daudé
2023-10-26 16:59 ` Richard Henderson
2023-10-20 20:43 ` [PATCH v2 48/65] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections Richard Henderson
2023-10-20 20:43 ` [PATCH v2 49/65] target/hppa: Remove remaining " Richard Henderson
2023-10-20 20:43 ` [PATCH v2 50/65] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new Richard Henderson
2023-10-20 20:43 ` [PATCH v2 51/65] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 Richard Henderson
2023-10-20 20:43 ` [PATCH v2 52/65] target/hppa: Implement HADD Richard Henderson
2023-10-20 20:43 ` [PATCH v2 53/65] target/hppa: Implement HSUB Richard Henderson
2023-10-20 20:43 ` [PATCH v2 54/65] target/hppa: Implement HAVG Richard Henderson
2023-10-20 20:43 ` [PATCH v2 55/65] target/hppa: Implement HSHL, HSHR Richard Henderson
2023-10-20 20:43 ` [PATCH v2 56/65] target/hppa: Implement HSHLADD, HSHRADD Richard Henderson
2023-10-20 20:43 ` [PATCH v2 57/65] target/hppa: Implement MIXH, MIXW Richard Henderson
2023-10-20 20:43 ` [PATCH v2 58/65] target/hppa: Implement PERMH Richard Henderson
2023-10-20 20:43 ` [PATCH v2 59/65] target/hppa: Fix interruption based on default PSW Richard Henderson
2023-10-20 20:43 ` [PATCH v2 60/65] target/hppa: Precompute zero into DisasContext Richard Henderson
2023-10-20 21:32 ` Philippe Mathieu-Daudé
2023-10-20 20:43 ` [PATCH v2 61/65] target/hppa: Return zero for r0 from load_gpr Richard Henderson
2023-10-20 21:32 ` Philippe Mathieu-Daudé
2023-10-20 20:43 ` [PATCH v2 62/65] target/hppa: Simplify trans_dep*_imm Richard Henderson
2023-10-20 20:43 ` [PATCH v2 63/65] include/hw/elf: Remove truncating signed casts Richard Henderson
2023-10-20 20:43 ` [PATCH v2 64/65] hw/hppa: Translate phys addresses for the cpu Richard Henderson
2023-10-20 20:43 ` [PATCH v2 65/65] linux-user/hppa: Drop EXCP_DUMP from handled exceptions Richard Henderson
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