From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: deller@gmx.de
Subject: [PATCH v2 49/65] target/hppa: Remove remaining TARGET_REGISTER_BITS redirections
Date: Fri, 20 Oct 2023 13:43:15 -0700 [thread overview]
Message-ID: <20231020204331.139847-50-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org>
The conversions to/from i64 can be eliminated entirely,
folding computation into adjacent operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 46 ++++++++++++-----------------------------
1 file changed, 13 insertions(+), 33 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 1a57ccc49b..95de007c69 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -33,15 +33,6 @@
#undef HELPER_H
-/* Since we have a distinction between register size and address size,
- we need to redefine all of these. */
-
-#define tcg_gen_extu_reg_tl tcg_gen_mov_i64
-#define tcg_gen_trunc_i64_reg tcg_gen_mov_i64
-#define tcg_gen_extu_reg_i64 tcg_gen_mov_i64
-#define tcg_gen_ext_reg_i64 tcg_gen_mov_i64
-
-
typedef struct DisasCond {
TCGCond c;
TCGv_i64 a0, a1;
@@ -1332,8 +1323,7 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs,
*pofs = ofs;
*pgva = addr = tcg_temp_new_i64();
- tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base);
- tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx));
+ tcg_gen_andi_tl(addr, modify <= 0 ? ofs : base, gva_offset_mask(ctx));
#ifndef CONFIG_USER_ONLY
if (!is_phys) {
tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base));
@@ -1945,13 +1935,11 @@ static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a)
unsigned rt = a->t;
unsigned rs = a->sp;
TCGv_i64 t0 = tcg_temp_new_i64();
- TCGv_i64 t1 = tcg_temp_new();
load_spr(ctx, t0, rs);
tcg_gen_shri_i64(t0, t0, 32);
- tcg_gen_trunc_i64_reg(t1, t0);
- save_gpr(ctx, rt, t1);
+ save_gpr(ctx, rt, t0);
cond_free(&ctx->null_cond);
return true;
@@ -2008,22 +1996,21 @@ static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a)
{
unsigned rr = a->r;
unsigned rs = a->sp;
- TCGv_i64 t64;
+ TCGv_i64 tmp;
if (rs >= 5) {
CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG);
}
nullify_over(ctx);
- t64 = tcg_temp_new_i64();
- tcg_gen_extu_reg_i64(t64, load_gpr(ctx, rr));
- tcg_gen_shli_i64(t64, t64, 32);
+ tmp = tcg_temp_new_i64();
+ tcg_gen_shli_i64(tmp, load_gpr(ctx, rr), 32);
if (rs >= 4) {
- tcg_gen_st_i64(t64, tcg_env, offsetof(CPUHPPAState, sr[rs]));
+ tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUHPPAState, sr[rs]));
ctx->tb_flags &= ~TB_FLAG_SR_SAME;
} else {
- tcg_gen_mov_i64(cpu_sr[rs], t64);
+ tcg_gen_mov_i64(cpu_sr[rs], tmp);
}
return nullify_end(ctx);
@@ -2114,11 +2101,8 @@ static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a)
/* We don't implement space registers in user mode. */
tcg_gen_movi_i64(dest, 0);
#else
- TCGv_i64 t0 = tcg_temp_new_i64();
-
- tcg_gen_mov_i64(t0, space_select(ctx, a->sp, load_gpr(ctx, a->b)));
- tcg_gen_shri_i64(t0, t0, 32);
- tcg_gen_trunc_i64_reg(dest, t0);
+ tcg_gen_mov_i64(dest, space_select(ctx, a->sp, load_gpr(ctx, a->b)));
+ tcg_gen_shri_i64(dest, dest, 32);
#endif
save_gpr(ctx, a->t, dest);
@@ -3152,10 +3136,8 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a)
TCGv_i64 s = tcg_temp_new_i64();
tcg_gen_concat32_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1));
- tcg_gen_extu_reg_i64(s, cpu_sar);
- tcg_gen_andi_i64(s, s, 31);
- tcg_gen_shr_i64(t, t, s);
- tcg_gen_trunc_i64_reg(dest, t);
+ tcg_gen_andi_i64(s, cpu_sar, 31);
+ tcg_gen_shr_i64(dest, t, s);
}
save_gpr(ctx, a->t, dest);
@@ -3196,10 +3178,8 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a)
tcg_gen_rotri_i32(t32, t32, sa);
tcg_gen_extu_i32_i64(dest, t32);
} else {
- TCGv_i64 t64 = tcg_temp_new_i64();
- tcg_gen_concat32_i64(t64, t2, cpu_gr[a->r1]);
- tcg_gen_shri_i64(t64, t64, sa);
- tcg_gen_trunc_i64_reg(dest, t64);
+ tcg_gen_concat32_i64(dest, t2, cpu_gr[a->r1]);
+ tcg_gen_extract_i64(dest, dest, sa, 32);
}
}
save_gpr(ctx, a->t, dest);
--
2.34.1
next prev parent reply other threads:[~2023-10-20 20:54 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-20 20:42 [PATCH v2 00/65] target/hppa: Implement hppa64-cpu Richard Henderson
2023-10-20 20:42 ` [PATCH v2 01/65] tcg: Improve expansion of deposit of constant Richard Henderson
2023-10-20 20:42 ` [PATCH v2 02/65] tcg: Improve expansion of deposit into a constant Richard Henderson
2023-10-20 20:42 ` [PATCH v2 03/65] target/hppa: Remove get_temp Richard Henderson
2023-10-20 20:42 ` [PATCH v2 04/65] target/hppa: Remove get_temp_tl Richard Henderson
2023-10-20 20:42 ` [PATCH v2 05/65] target/hppa: Remove load_const Richard Henderson
2023-10-20 21:15 ` Philippe Mathieu-Daudé
2023-10-20 20:42 ` [PATCH v2 06/65] target/hppa: Fix hppa64 case in machine.c Richard Henderson
2023-10-20 20:42 ` [PATCH v2 07/65] target/hppa: Fix load in do_load_32 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 08/65] target/hppa: Truncate rotate count in trans_shrpw_sar Richard Henderson
2023-10-20 20:42 ` [PATCH v2 09/65] target/hppa: Fix trans_ds for hppa64 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 10/65] target/hppa: Fix do_add, do_sub " Richard Henderson
2023-10-20 20:42 ` [PATCH v2 11/65] target/hppa: Fix bb_sar " Richard Henderson
2023-10-20 20:42 ` [PATCH v2 12/65] target/hppa: Fix extrw and depw with sar " Richard Henderson
2023-10-20 20:42 ` [PATCH v2 13/65] target/hppa: Introduce TYPE_HPPA64_CPU Richard Henderson
2023-10-20 21:19 ` Philippe Mathieu-Daudé
2023-10-20 20:42 ` [PATCH v2 14/65] target/hppa: Make HPPA_BTLB_ENTRIES variable Richard Henderson
2023-10-20 20:42 ` [PATCH v2 15/65] target/hppa: Implement cpu_list Richard Henderson
2023-10-20 20:42 ` [PATCH v2 16/65] target/hppa: Implement hppa_cpu_class_by_name Richard Henderson
2023-10-20 20:42 ` [PATCH v2 17/65] target/hppa: Update cpu_hppa_get/put_psw for hppa64 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 18/65] target/hppa: Handle absolute addresses for pa2.0 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 19/65] target/hppa: Adjust hppa_cpu_dump_state for hppa64 Richard Henderson
2023-10-20 21:35 ` Philippe Mathieu-Daudé
2023-10-20 20:42 ` [PATCH v2 20/65] target/hppa: Fix hppa64 addressing Richard Henderson
2023-10-20 20:42 ` [PATCH v2 21/65] target/hppa: sar register allows only 5 bits on 32-bit CPU Richard Henderson
2023-10-20 20:42 ` [PATCH v2 22/65] target/hppa: Pass d to do_cond Richard Henderson
2023-10-20 20:42 ` [PATCH v2 23/65] target/hppa: Pass d to do_sub_cond Richard Henderson
2023-10-20 20:42 ` [PATCH v2 24/65] target/hppa: Pass d to do_log_cond Richard Henderson
2023-10-20 20:42 ` [PATCH v2 25/65] target/hppa: Pass d to do_sed_cond Richard Henderson
2023-10-20 20:42 ` [PATCH v2 26/65] target/hppa: Pass d to do_unit_cond Richard Henderson
2023-10-20 20:42 ` [PATCH v2 27/65] linux-user/hppa: Fixes for TARGET_ABI32 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 28/65] target/hppa: Drop attempted gdbstub support for hppa64 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 29/65] target/hppa: Remove TARGET_HPPA64 Richard Henderson
2023-10-20 20:42 ` [PATCH v2 30/65] target/hppa: Decode d for logical instructions Richard Henderson
2023-10-20 20:42 ` [PATCH v2 31/65] target/hppa: Decode d for unit instructions Richard Henderson
2023-10-20 20:42 ` [PATCH v2 32/65] target/hppa: Decode d for cmpclr instructions Richard Henderson
2023-10-20 20:42 ` [PATCH v2 33/65] target/hppa: Decode d for add instructions Richard Henderson
2023-10-20 20:43 ` [PATCH v2 34/65] target/hppa: Decode d for sub instructions Richard Henderson
2023-10-20 20:43 ` [PATCH v2 35/65] target/hppa: Decode d for bb instructions Richard Henderson
2023-10-20 20:43 ` [PATCH v2 36/65] target/hppa: Decode d for cmpb instructions Richard Henderson
2023-10-20 20:43 ` [PATCH v2 37/65] target/hppa: Decode CMPIB double-word Richard Henderson
2023-10-20 20:43 ` [PATCH v2 38/65] target/hppa: Decode ADDB double-word Richard Henderson
2023-10-20 20:43 ` [PATCH v2 39/65] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA Richard Henderson
2023-10-20 20:43 ` [PATCH v2 40/65] target/hppa: Implement DEPD, DEPDI Richard Henderson
2023-10-20 20:43 ` [PATCH v2 41/65] target/hppa: Implement EXTRD Richard Henderson
2023-10-20 20:43 ` [PATCH v2 42/65] target/hppa: Implement SHRPD Richard Henderson
2023-10-20 20:43 ` [PATCH v2 43/65] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM Richard Henderson
2023-10-20 20:43 ` [PATCH v2 44/65] target/hppa: Implement STDBY Richard Henderson
2023-10-20 20:43 ` [PATCH v2 45/65] target/hppa: Implement IDTLBT, IITLBT Richard Henderson
2023-10-20 20:43 ` [PATCH v2 46/65] hw/hppa: Use uint32_t instead of target_ureg Richard Henderson
2023-10-20 21:34 ` Philippe Mathieu-Daudé
2023-10-20 20:43 ` [PATCH v2 47/65] target/hppa: Remove TARGET_REGISTER_BITS Richard Henderson
2023-10-20 21:31 ` Philippe Mathieu-Daudé
2023-10-26 16:59 ` Richard Henderson
2023-10-20 20:43 ` [PATCH v2 48/65] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections Richard Henderson
2023-10-20 20:43 ` Richard Henderson [this message]
2023-10-20 20:43 ` [PATCH v2 50/65] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new Richard Henderson
2023-10-20 20:43 ` [PATCH v2 51/65] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 Richard Henderson
2023-10-20 20:43 ` [PATCH v2 52/65] target/hppa: Implement HADD Richard Henderson
2023-10-20 20:43 ` [PATCH v2 53/65] target/hppa: Implement HSUB Richard Henderson
2023-10-20 20:43 ` [PATCH v2 54/65] target/hppa: Implement HAVG Richard Henderson
2023-10-20 20:43 ` [PATCH v2 55/65] target/hppa: Implement HSHL, HSHR Richard Henderson
2023-10-20 20:43 ` [PATCH v2 56/65] target/hppa: Implement HSHLADD, HSHRADD Richard Henderson
2023-10-20 20:43 ` [PATCH v2 57/65] target/hppa: Implement MIXH, MIXW Richard Henderson
2023-10-20 20:43 ` [PATCH v2 58/65] target/hppa: Implement PERMH Richard Henderson
2023-10-20 20:43 ` [PATCH v2 59/65] target/hppa: Fix interruption based on default PSW Richard Henderson
2023-10-20 20:43 ` [PATCH v2 60/65] target/hppa: Precompute zero into DisasContext Richard Henderson
2023-10-20 21:32 ` Philippe Mathieu-Daudé
2023-10-20 20:43 ` [PATCH v2 61/65] target/hppa: Return zero for r0 from load_gpr Richard Henderson
2023-10-20 21:32 ` Philippe Mathieu-Daudé
2023-10-20 20:43 ` [PATCH v2 62/65] target/hppa: Simplify trans_dep*_imm Richard Henderson
2023-10-20 20:43 ` [PATCH v2 63/65] include/hw/elf: Remove truncating signed casts Richard Henderson
2023-10-20 20:43 ` [PATCH v2 64/65] hw/hppa: Translate phys addresses for the cpu Richard Henderson
2023-10-20 20:43 ` [PATCH v2 65/65] linux-user/hppa: Drop EXCP_DUMP from handled exceptions Richard Henderson
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