From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk
Subject: [PATCH v3 69/90] target/sparc: Move gen_gsr_fop_DDD insns to decodetree
Date: Fri, 20 Oct 2023 22:31:37 -0700 [thread overview]
Message-ID: <20231021053158.278135-70-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231021053158.278135-1-richard.henderson@linaro.org>
Move FPACK32, FALIGNDATA, BSHUFFLE.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 3 ++
target/sparc/translate.c | 101 ++++++++++++++++++++------------------
2 files changed, 55 insertions(+), 49 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 9ac2a715c0..4e15bfacfb 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -277,9 +277,12 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2
FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @r_r_r
FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r
FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r
+ FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @r_r_r
PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r
+ FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r
FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r
+ BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @r_r_r
FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r
FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 0c5ad342bc..fccfe1d53e 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -748,6 +748,51 @@ static void gen_op_array32(TCGv dst, TCGv src1, TCGv src2)
tcg_gen_shli_tl(dst, dst, 2);
}
+static void gen_op_fpack32(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2)
+{
+#ifdef TARGET_SPARC64
+ gen_helper_fpack32(dst, cpu_gsr, src1, src2);
+#else
+ g_assert_not_reached();
+#endif
+}
+
+static void gen_op_faligndata(TCGv_i64 dst, TCGv_i64 s1, TCGv_i64 s2)
+{
+#ifdef TARGET_SPARC64
+ TCGv t1, t2, shift;
+
+ t1 = tcg_temp_new();
+ t2 = tcg_temp_new();
+ shift = tcg_temp_new();
+
+ tcg_gen_andi_tl(shift, cpu_gsr, 7);
+ tcg_gen_shli_tl(shift, shift, 3);
+ tcg_gen_shl_tl(t1, s1, shift);
+
+ /*
+ * A shift of 64 does not produce 0 in TCG. Divide this into a
+ * shift of (up to 63) followed by a constant shift of 1.
+ */
+ tcg_gen_xori_tl(shift, shift, 63);
+ tcg_gen_shr_tl(t2, s2, shift);
+ tcg_gen_shri_tl(t2, t2, 1);
+
+ tcg_gen_or_tl(dst, t1, t2);
+#else
+ g_assert_not_reached();
+#endif
+}
+
+static void gen_op_bshuffle(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2)
+{
+#ifdef TARGET_SPARC64
+ gen_helper_bshuffle(dst, cpu_gsr, src1, src2);
+#else
+ g_assert_not_reached();
+#endif
+}
+
// 1
static void gen_op_eval_ba(TCGv dst)
{
@@ -1663,22 +1708,6 @@ static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
gen_store_fpr_D(dc, rd, dst);
}
-#ifdef TARGET_SPARC64
-static void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
- void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
-{
- TCGv_i64 dst, src1, src2;
-
- src1 = gen_load_fpr_D(dc, rs1);
- src2 = gen_load_fpr_D(dc, rs2);
- dst = gen_dest_fpr_D(dc, rd);
-
- gen(dst, cpu_gsr, src1, src2);
-
- gen_store_fpr_D(dc, rd, dst);
-}
-#endif
-
static void gen_fop_QQ(DisasContext *dc, int rd, int rs,
void (*gen)(TCGv_ptr))
{
@@ -2700,27 +2729,6 @@ static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr)
tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp);
}
}
-
-static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
-{
- TCGv t1, t2, shift;
-
- t1 = tcg_temp_new();
- t2 = tcg_temp_new();
- shift = tcg_temp_new();
-
- tcg_gen_andi_tl(shift, gsr, 7);
- tcg_gen_shli_tl(shift, shift, 3);
- tcg_gen_shl_tl(t1, s1, shift);
-
- /* A shift of 64 does not produce 0 in TCG. Divide this into a
- shift of (up to 63) followed by a constant shift of 1. */
- tcg_gen_xori_tl(shift, shift, 63);
- tcg_gen_shr_tl(t2, s2, shift);
- tcg_gen_shri_tl(t2, t2, 1);
-
- tcg_gen_or_tl(dst, t1, t2);
-}
#endif
static int extract_dfpreg(DisasContext *dc, int x)
@@ -5006,6 +5014,10 @@ TRANS(FXNORd, VIS1, do_ddd, a, tcg_gen_eqv_i64)
TRANS(FORNOTd, VIS1, do_ddd, a, tcg_gen_orc_i64)
TRANS(FORd, VIS1, do_ddd, a, tcg_gen_or_i64)
+TRANS(FPACK32, VIS1, do_ddd, a, gen_op_fpack32)
+TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata)
+TRANS(BSHUFFLE, VIS2, do_ddd, a, gen_op_bshuffle)
+
static bool do_dddd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
{
@@ -5436,6 +5448,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x04b: /* VIS I fpmerge */
case 0x04d: /* VIS I fexpand */
case 0x03e: /* VIS I pdist */
+ case 0x03a: /* VIS I fpack32 */
+ case 0x048: /* VIS I faligndata */
+ case 0x04c: /* VIS II bshuffle */
g_assert_not_reached(); /* in decodetree */
case 0x020: /* VIS I fcmple16 */
CHECK_FPU_FEATURE(dc, VIS1);
@@ -5493,10 +5508,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
gen_store_gpr(dc, rd, cpu_dst);
break;
- case 0x03a: /* VIS I fpack32 */
- CHECK_FPU_FEATURE(dc, VIS1);
- gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32);
- break;
case 0x03b: /* VIS I fpack16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
@@ -5511,14 +5522,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
- case 0x048: /* VIS I faligndata */
- CHECK_FPU_FEATURE(dc, VIS1);
- gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata);
- break;
- case 0x04c: /* VIS II bshuffle */
- CHECK_FPU_FEATURE(dc, VIS2);
- gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle);
- break;
case 0x060: /* VIS I fzero */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_dst_64 = gen_dest_fpr_D(dc, rd);
--
2.34.1
next prev parent reply other threads:[~2023-10-21 5:45 UTC|newest]
Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-21 5:30 [PATCH v3 00/90] target/sparc: Convert to decodetree Richard Henderson
2023-10-21 5:30 ` [PATCH v3 01/90] target/sparc: Clear may_lookup for npc == DYNAMIC_PC Richard Henderson
2023-10-21 5:30 ` [PATCH v3 02/90] target/sparc: Implement check_align inline Richard Henderson
2023-10-21 5:30 ` [PATCH v3 03/90] target/sparc: Avoid helper_raise_exception in helper_st_asi Richard Henderson
2023-10-21 5:30 ` [PATCH v3 04/90] target/sparc: Set TCG_GUEST_DEFAULT_MO Richard Henderson
2023-10-21 5:30 ` [PATCH v3 05/90] configs: Enable MTTCG for sparc, sparc64 Richard Henderson
2023-10-21 5:30 ` [PATCH v3 06/90] target/sparc: Define features via cpu-feature.h.inc Richard Henderson
2023-10-21 5:30 ` [PATCH v3 07/90] target/sparc: Use CPU_FEATURE_BIT_* for cpu properties Richard Henderson
2023-10-21 5:30 ` [PATCH v3 08/90] target/sparc: Remove sparcv7 cpu features Richard Henderson
2023-10-21 5:30 ` [PATCH v3 09/90] target/sparc: Add decodetree infrastructure Richard Henderson
2023-10-21 5:30 ` [PATCH v3 10/90] target/sparc: Define AM_CHECK for sparc32 Richard Henderson
2023-10-21 5:30 ` [PATCH v3 11/90] target/sparc: Move CALL to decodetree Richard Henderson
2023-10-21 5:30 ` [PATCH v3 12/90] target/sparc: Move BPcc and Bicc " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 13/90] target/sparc: Move BPr " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 14/90] target/sparc: Move FBPfcc and FBfcc " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 15/90] target/sparc: Merge gen_cond with only caller Richard Henderson
2023-10-21 5:30 ` [PATCH v3 16/90] target/sparc: Merge gen_fcond " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 17/90] target/sparc: Merge gen_branch_[an] " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 18/90] target/sparc: Pass DisasCompare to advance_jump_cond Richard Henderson
2023-10-21 5:30 ` [PATCH v3 19/90] target/sparc: Move SETHI to decodetree Richard Henderson
2023-10-21 5:30 ` [PATCH v3 20/90] target/sparc: Move Tcc " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 21/90] target/sparc: Move RDASR, STBAR, MEMBAR " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 22/90] target/sparc: Move RDPSR, RDHPR " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 23/90] target/sparc: Move RDWIM, RDPR " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 24/90] target/sparc: Move RDTBR, FLUSHW " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 25/90] target/sparc: Move WRASR " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 26/90] target/sparc: Move WRPSR, SAVED, RESTORED " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 27/90] target/sparc: Move WRWIM, WRPR " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 28/90] target/sparc: Move WRTBR, WRHPR " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 29/90] target/sparc: Move basic arithmetic " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 30/90] target/sparc: Move ADDC " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 31/90] target/sparc: Move MULX " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 32/90] target/sparc: Move UMUL, SMUL " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 33/90] target/sparc: Move SUBC " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 34/90] target/sparc: Move UDIVX, SDIVX " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 35/90] target/sparc: Move UDIV, SDIV " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 36/90] target/sparc: Move TADD, TSUB, MULS " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 37/90] target/sparc: Move SLL, SRL, SRA " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 38/90] target/sparc: Move MOVcc, MOVR " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 39/90] target/sparc: Move POPC " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 40/90] target/sparc: Convert remaining v8 coproc insns " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 41/90] target/sparc: Move JMPL, RETT, RETURN " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 42/90] target/sparc: Move FLUSH, SAVE, RESTORE " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 43/90] target/sparc: Move DONE, RETRY " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 44/90] target/sparc: Split out resolve_asi Richard Henderson
2023-10-21 5:31 ` [PATCH v3 45/90] target/sparc: Drop ifdef around get_asi and friends Richard Henderson
2023-10-21 5:31 ` [PATCH v3 46/90] target/sparc: Split out ldst functions with asi pre-computed Richard Henderson
2023-10-21 5:31 ` [PATCH v3 47/90] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX Richard Henderson
2023-10-21 5:31 ` [PATCH v3 48/90] target/sparc: Move simple integer load/store to decodetree Richard Henderson
2023-10-21 5:31 ` [PATCH v3 49/90] target/sparc: Move asi " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 50/90] target/sparc: Move LDSTUB, LDSTUBA " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 51/90] target/sparc: Move SWAP, SWAPA " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 52/90] target/sparc: Move CASA, CASXA " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 53/90] target/sparc: Move PREFETCH, PREFETCHA " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 54/90] target/sparc: Split out fp ldst functions with asi precomputed Richard Henderson
2023-10-21 5:31 ` [PATCH v3 55/90] target/sparc: Move simple fp load/store to decodetree Richard Henderson
2023-10-21 5:31 ` [PATCH v3 56/90] target/sparc: Move asi " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 57/90] target/sparc: Move LDFSR, STFSR " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 58/90] target/sparc: Merge LDFSR, LDXFSR implementations Richard Henderson
2023-10-21 5:31 ` [PATCH v3 59/90] target/sparc: Move EDGE* to decodetree Richard Henderson
2023-10-21 5:31 ` [PATCH v3 60/90] target/sparc: Move ARRAY* " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 61/90] target/sparc: Move ADDRALIGN* " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 62/90] target/sparc: Move BMASK " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 63/90] target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 64/90] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 65/90] target/sparc: Use tcg_gen_vec_{add,sub}* Richard Henderson
2023-10-21 5:31 ` [PATCH v3 66/90] target/sparc: Move gen_ne_fop_FFF insns to decodetree Richard Henderson
2023-10-21 5:31 ` [PATCH v3 67/90] target/sparc: Move gen_ne_fop_DDD " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 68/90] target/sparc: Move PDIST " Richard Henderson
2023-10-21 5:31 ` Richard Henderson [this message]
2023-10-21 5:31 ` [PATCH v3 70/90] target/sparc: Move gen_fop_FF insns " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 71/90] target/sparc: Move gen_fop_DD " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 72/90] target/sparc: Move FSQRTq " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 73/90] target/sparc: Move gen_fop_FFF insns " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 74/90] target/sparc: Move gen_fop_DDD " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 75/90] target/sparc: Move gen_fop_QQQ " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 76/90] target/sparc: Move FSMULD " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 77/90] target/sparc: Move FDMULQ " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 78/90] target/sparc: Move gen_fop_FD insns " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 79/90] target/sparc: Move FiTOd, FsTOd, FsTOx " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 80/90] target/sparc: Move FqTOs, FqTOi " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 81/90] target/sparc: Move FqTOd, FqTOx " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 82/90] target/sparc: Move FiTOq, FsTOq " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 83/90] target/sparc: Move FdTOq, FxTOq " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 84/90] target/sparc: Move FMOVq, FNEGq, FABSq " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 85/90] target/sparc: Move FMOVR, FMOVcc, FMOVfcc " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 86/90] target/sparc: Convert FCMP, FCMPE " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 87/90] target/sparc: Move FPCMP* " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 88/90] target/sparc: Move FPACK16, FPACKFIX " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 89/90] target/sparc: Convert FZERO, FONE " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 90/90] target/sparc: Remove disas_sparc_legacy Richard Henderson
2023-10-21 14:07 ` [PATCH v3 00/90] target/sparc: Convert to decodetree Mark Cave-Ayland
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