From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk
Subject: [PATCH v3 85/90] target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree
Date: Fri, 20 Oct 2023 22:31:53 -0700 [thread overview]
Message-ID: <20231021053158.278135-86-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231021053158.278135-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 12 +++
target/sparc/translate.c | 192 ++++++++++++++++----------------------
2 files changed, 91 insertions(+), 113 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 1b14a49850..646acad75d 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -284,6 +284,18 @@ FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2
FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2
FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2
+FMOVscc 10 rd:5 110101 0 cond:4 1 cc:1 0 000001 rs2:5
+FMOVdcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000010 rs2:5
+FMOVqcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000011 rs2:5
+
+FMOVsfcc 10 rd:5 110101 0 cond:4 0 cc:2 000001 rs2:5
+FMOVdfcc 10 rd:5 110101 0 cond:4 0 cc:2 000010 rs2:5
+FMOVqfcc 10 rd:5 110101 0 cond:4 0 cc:2 000011 rs2:5
+
+FMOVRs 10 rd:5 110101 rs1:5 0 cond:3 00101 rs2:5
+FMOVRd 10 rd:5 110101 rs1:5 0 cond:3 00110 rs2:5
+FMOVRq 10 rd:5 110101 rs1:5 0 cond:3 00111 rs2:5
+
{
[
EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 1e506e8366..4fdfa46f5f 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2423,15 +2423,9 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
}
}
-#ifdef TARGET_SPARC64
-static TCGv get_src1(DisasContext *dc, unsigned int insn)
-{
- unsigned int rs1 = GET_FIELD(insn, 13, 17);
- return gen_load_gpr(dc, rs1);
-}
-
static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
{
+#ifdef TARGET_SPARC64
TCGv_i32 c32, zero, dst, s1, s2;
/* We have two choices here: extend the 32 bit data and use movcond_i64,
@@ -2454,19 +2448,27 @@ static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
gen_store_fpr_F(dc, rd, dst);
+#else
+ qemu_build_not_reached();
+#endif
}
static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
{
+#ifdef TARGET_SPARC64
TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
gen_load_fpr_D(dc, rs),
gen_load_fpr_D(dc, rd));
gen_store_fpr_D(dc, rd, dst);
+#else
+ qemu_build_not_reached();
+#endif
}
static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
{
+#ifdef TARGET_SPARC64
int qd = QFPREG(rd);
int qs = QFPREG(rs);
@@ -2476,8 +2478,12 @@ static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
gen_update_fprs_dirty(dc, qd);
+#else
+ qemu_build_not_reached();
+#endif
}
+#ifdef TARGET_SPARC64
static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr)
{
TCGv_i32 r_tl = tcg_temp_new_i32();
@@ -5171,6 +5177,72 @@ static bool trans_FdMULq(DisasContext *dc, arg_r_r_r *a)
return advance_pc(dc);
}
+static bool do_fmovr(DisasContext *dc, arg_FMOVRs *a, bool is_128,
+ void (*func)(DisasContext *, DisasCompare *, int, int))
+{
+ DisasCompare cmp;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+ if (is_128 && gen_trap_float128(dc)) {
+ return true;
+ }
+
+ gen_op_clear_ieee_excp_and_FTT();
+ gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1));
+ func(dc, &cmp, a->rd, a->rs2);
+ return advance_pc(dc);
+}
+
+TRANS(FMOVRs, 64, do_fmovr, a, false, gen_fmovs)
+TRANS(FMOVRd, 64, do_fmovr, a, false, gen_fmovd)
+TRANS(FMOVRq, 64, do_fmovr, a, true, gen_fmovq)
+
+static bool do_fmovcc(DisasContext *dc, arg_FMOVscc *a, bool is_128,
+ void (*func)(DisasContext *, DisasCompare *, int, int))
+{
+ DisasCompare cmp;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+ if (is_128 && gen_trap_float128(dc)) {
+ return true;
+ }
+
+ gen_op_clear_ieee_excp_and_FTT();
+ gen_compare(&cmp, a->cc, a->cond, dc);
+ func(dc, &cmp, a->rd, a->rs2);
+ return advance_pc(dc);
+}
+
+TRANS(FMOVscc, 64, do_fmovcc, a, false, gen_fmovs)
+TRANS(FMOVdcc, 64, do_fmovcc, a, false, gen_fmovd)
+TRANS(FMOVqcc, 64, do_fmovcc, a, true, gen_fmovq)
+
+static bool do_fmovfcc(DisasContext *dc, arg_FMOVsfcc *a, bool is_128,
+ void (*func)(DisasContext *, DisasCompare *, int, int))
+{
+ DisasCompare cmp;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+ if (is_128 && gen_trap_float128(dc)) {
+ return true;
+ }
+
+ gen_op_clear_ieee_excp_and_FTT();
+ gen_fcompare(&cmp, a->cc, a->cond);
+ func(dc, &cmp, a->rd, a->rs2);
+ return advance_pc(dc);
+}
+
+TRANS(FMOVsfcc, 64, do_fmovfcc, a, false, gen_fmovs)
+TRANS(FMOVdfcc, 64, do_fmovfcc, a, false, gen_fmovd)
+TRANS(FMOVqfcc, 64, do_fmovfcc, a, true, gen_fmovq)
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -5204,9 +5276,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
if (xop == 0x34) { /* FPU Operations */
goto illegal_insn; /* in decodetree */
} else if (xop == 0x35) { /* FPU Operations */
-#ifdef TARGET_SPARC64
- int cond;
-#endif
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
@@ -5215,110 +5284,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
rs2 = GET_FIELD(insn, 27, 31);
xop = GET_FIELD(insn, 18, 26);
-#ifdef TARGET_SPARC64
-#define FMOVR(sz) \
- do { \
- DisasCompare cmp; \
- cond = GET_FIELD_SP(insn, 10, 12); \
- cpu_src1 = get_src1(dc, insn); \
- gen_compare_reg(&cmp, cond, cpu_src1); \
- gen_fmov##sz(dc, &cmp, rd, rs2); \
- } while (0)
-
- if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
- FMOVR(s);
- break;
- } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
- FMOVR(d);
- break;
- } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
- CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVR(q);
- break;
- }
-#undef FMOVR
-#endif
switch (xop) {
-#ifdef TARGET_SPARC64
-#define FMOVCC(fcc, sz) \
- do { \
- DisasCompare cmp; \
- cond = GET_FIELD_SP(insn, 14, 17); \
- gen_fcompare(&cmp, fcc, cond); \
- gen_fmov##sz(dc, &cmp, rd, rs2); \
- } while (0)
-
- case 0x001: /* V9 fmovscc %fcc0 */
- FMOVCC(0, s);
- break;
- case 0x002: /* V9 fmovdcc %fcc0 */
- FMOVCC(0, d);
- break;
- case 0x003: /* V9 fmovqcc %fcc0 */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(0, q);
- break;
- case 0x041: /* V9 fmovscc %fcc1 */
- FMOVCC(1, s);
- break;
- case 0x042: /* V9 fmovdcc %fcc1 */
- FMOVCC(1, d);
- break;
- case 0x043: /* V9 fmovqcc %fcc1 */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(1, q);
- break;
- case 0x081: /* V9 fmovscc %fcc2 */
- FMOVCC(2, s);
- break;
- case 0x082: /* V9 fmovdcc %fcc2 */
- FMOVCC(2, d);
- break;
- case 0x083: /* V9 fmovqcc %fcc2 */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(2, q);
- break;
- case 0x0c1: /* V9 fmovscc %fcc3 */
- FMOVCC(3, s);
- break;
- case 0x0c2: /* V9 fmovdcc %fcc3 */
- FMOVCC(3, d);
- break;
- case 0x0c3: /* V9 fmovqcc %fcc3 */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(3, q);
- break;
-#undef FMOVCC
-#define FMOVCC(xcc, sz) \
- do { \
- DisasCompare cmp; \
- cond = GET_FIELD_SP(insn, 14, 17); \
- gen_compare(&cmp, xcc, cond, dc); \
- gen_fmov##sz(dc, &cmp, rd, rs2); \
- } while (0)
-
- case 0x101: /* V9 fmovscc %icc */
- FMOVCC(0, s);
- break;
- case 0x102: /* V9 fmovdcc %icc */
- FMOVCC(0, d);
- break;
- case 0x103: /* V9 fmovqcc %icc */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(0, q);
- break;
- case 0x181: /* V9 fmovscc %xcc */
- FMOVCC(1, s);
- break;
- case 0x182: /* V9 fmovdcc %xcc */
- FMOVCC(1, d);
- break;
- case 0x183: /* V9 fmovqcc %xcc */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(1, q);
- break;
-#undef FMOVCC
-#endif
case 0x51: /* fcmps, V9 %fcc */
cpu_src1_32 = gen_load_fpr_F(dc, rs1);
cpu_src2_32 = gen_load_fpr_F(dc, rs2);
--
2.34.1
next prev parent reply other threads:[~2023-10-21 5:45 UTC|newest]
Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-21 5:30 [PATCH v3 00/90] target/sparc: Convert to decodetree Richard Henderson
2023-10-21 5:30 ` [PATCH v3 01/90] target/sparc: Clear may_lookup for npc == DYNAMIC_PC Richard Henderson
2023-10-21 5:30 ` [PATCH v3 02/90] target/sparc: Implement check_align inline Richard Henderson
2023-10-21 5:30 ` [PATCH v3 03/90] target/sparc: Avoid helper_raise_exception in helper_st_asi Richard Henderson
2023-10-21 5:30 ` [PATCH v3 04/90] target/sparc: Set TCG_GUEST_DEFAULT_MO Richard Henderson
2023-10-21 5:30 ` [PATCH v3 05/90] configs: Enable MTTCG for sparc, sparc64 Richard Henderson
2023-10-21 5:30 ` [PATCH v3 06/90] target/sparc: Define features via cpu-feature.h.inc Richard Henderson
2023-10-21 5:30 ` [PATCH v3 07/90] target/sparc: Use CPU_FEATURE_BIT_* for cpu properties Richard Henderson
2023-10-21 5:30 ` [PATCH v3 08/90] target/sparc: Remove sparcv7 cpu features Richard Henderson
2023-10-21 5:30 ` [PATCH v3 09/90] target/sparc: Add decodetree infrastructure Richard Henderson
2023-10-21 5:30 ` [PATCH v3 10/90] target/sparc: Define AM_CHECK for sparc32 Richard Henderson
2023-10-21 5:30 ` [PATCH v3 11/90] target/sparc: Move CALL to decodetree Richard Henderson
2023-10-21 5:30 ` [PATCH v3 12/90] target/sparc: Move BPcc and Bicc " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 13/90] target/sparc: Move BPr " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 14/90] target/sparc: Move FBPfcc and FBfcc " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 15/90] target/sparc: Merge gen_cond with only caller Richard Henderson
2023-10-21 5:30 ` [PATCH v3 16/90] target/sparc: Merge gen_fcond " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 17/90] target/sparc: Merge gen_branch_[an] " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 18/90] target/sparc: Pass DisasCompare to advance_jump_cond Richard Henderson
2023-10-21 5:30 ` [PATCH v3 19/90] target/sparc: Move SETHI to decodetree Richard Henderson
2023-10-21 5:30 ` [PATCH v3 20/90] target/sparc: Move Tcc " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 21/90] target/sparc: Move RDASR, STBAR, MEMBAR " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 22/90] target/sparc: Move RDPSR, RDHPR " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 23/90] target/sparc: Move RDWIM, RDPR " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 24/90] target/sparc: Move RDTBR, FLUSHW " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 25/90] target/sparc: Move WRASR " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 26/90] target/sparc: Move WRPSR, SAVED, RESTORED " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 27/90] target/sparc: Move WRWIM, WRPR " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 28/90] target/sparc: Move WRTBR, WRHPR " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 29/90] target/sparc: Move basic arithmetic " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 30/90] target/sparc: Move ADDC " Richard Henderson
2023-10-21 5:30 ` [PATCH v3 31/90] target/sparc: Move MULX " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 32/90] target/sparc: Move UMUL, SMUL " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 33/90] target/sparc: Move SUBC " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 34/90] target/sparc: Move UDIVX, SDIVX " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 35/90] target/sparc: Move UDIV, SDIV " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 36/90] target/sparc: Move TADD, TSUB, MULS " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 37/90] target/sparc: Move SLL, SRL, SRA " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 38/90] target/sparc: Move MOVcc, MOVR " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 39/90] target/sparc: Move POPC " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 40/90] target/sparc: Convert remaining v8 coproc insns " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 41/90] target/sparc: Move JMPL, RETT, RETURN " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 42/90] target/sparc: Move FLUSH, SAVE, RESTORE " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 43/90] target/sparc: Move DONE, RETRY " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 44/90] target/sparc: Split out resolve_asi Richard Henderson
2023-10-21 5:31 ` [PATCH v3 45/90] target/sparc: Drop ifdef around get_asi and friends Richard Henderson
2023-10-21 5:31 ` [PATCH v3 46/90] target/sparc: Split out ldst functions with asi pre-computed Richard Henderson
2023-10-21 5:31 ` [PATCH v3 47/90] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX Richard Henderson
2023-10-21 5:31 ` [PATCH v3 48/90] target/sparc: Move simple integer load/store to decodetree Richard Henderson
2023-10-21 5:31 ` [PATCH v3 49/90] target/sparc: Move asi " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 50/90] target/sparc: Move LDSTUB, LDSTUBA " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 51/90] target/sparc: Move SWAP, SWAPA " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 52/90] target/sparc: Move CASA, CASXA " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 53/90] target/sparc: Move PREFETCH, PREFETCHA " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 54/90] target/sparc: Split out fp ldst functions with asi precomputed Richard Henderson
2023-10-21 5:31 ` [PATCH v3 55/90] target/sparc: Move simple fp load/store to decodetree Richard Henderson
2023-10-21 5:31 ` [PATCH v3 56/90] target/sparc: Move asi " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 57/90] target/sparc: Move LDFSR, STFSR " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 58/90] target/sparc: Merge LDFSR, LDXFSR implementations Richard Henderson
2023-10-21 5:31 ` [PATCH v3 59/90] target/sparc: Move EDGE* to decodetree Richard Henderson
2023-10-21 5:31 ` [PATCH v3 60/90] target/sparc: Move ARRAY* " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 61/90] target/sparc: Move ADDRALIGN* " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 62/90] target/sparc: Move BMASK " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 63/90] target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 64/90] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 65/90] target/sparc: Use tcg_gen_vec_{add,sub}* Richard Henderson
2023-10-21 5:31 ` [PATCH v3 66/90] target/sparc: Move gen_ne_fop_FFF insns to decodetree Richard Henderson
2023-10-21 5:31 ` [PATCH v3 67/90] target/sparc: Move gen_ne_fop_DDD " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 68/90] target/sparc: Move PDIST " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 69/90] target/sparc: Move gen_gsr_fop_DDD insns " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 70/90] target/sparc: Move gen_fop_FF " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 71/90] target/sparc: Move gen_fop_DD " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 72/90] target/sparc: Move FSQRTq " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 73/90] target/sparc: Move gen_fop_FFF insns " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 74/90] target/sparc: Move gen_fop_DDD " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 75/90] target/sparc: Move gen_fop_QQQ " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 76/90] target/sparc: Move FSMULD " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 77/90] target/sparc: Move FDMULQ " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 78/90] target/sparc: Move gen_fop_FD insns " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 79/90] target/sparc: Move FiTOd, FsTOd, FsTOx " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 80/90] target/sparc: Move FqTOs, FqTOi " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 81/90] target/sparc: Move FqTOd, FqTOx " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 82/90] target/sparc: Move FiTOq, FsTOq " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 83/90] target/sparc: Move FdTOq, FxTOq " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 84/90] target/sparc: Move FMOVq, FNEGq, FABSq " Richard Henderson
2023-10-21 5:31 ` Richard Henderson [this message]
2023-10-21 5:31 ` [PATCH v3 86/90] target/sparc: Convert FCMP, FCMPE " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 87/90] target/sparc: Move FPCMP* " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 88/90] target/sparc: Move FPACK16, FPACKFIX " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 89/90] target/sparc: Convert FZERO, FONE " Richard Henderson
2023-10-21 5:31 ` [PATCH v3 90/90] target/sparc: Remove disas_sparc_legacy Richard Henderson
2023-10-21 14:07 ` [PATCH v3 00/90] target/sparc: Convert to decodetree Mark Cave-Ayland
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