From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk
Subject: [PATCH v4 56/90] target/sparc: Move asi fp load/store to decodetree
Date: Sat, 21 Oct 2023 22:59:57 -0700 [thread overview]
Message-ID: <20231022060031.490251-57-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231022060031.490251-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 51 +++++++++--
target/sparc/translate.c | 173 ++++++++------------------------------
2 files changed, 81 insertions(+), 143 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 1150890e44..45eb6a967f 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -251,6 +251,14 @@ NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
@r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm=0
@r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \
&r_r_ri_asi imm=1 asi=-2
+@d_r_r_asi .. ..... ...... rs1:5 0 asi:8 rs2_or_imm:5 \
+ &r_r_ri_asi rd=%dfp_rd imm=0
+@d_r_i_asi .. ..... ...... rs1:5 1 rs2_or_imm:s13 \
+ &r_r_ri_asi rd=%dfp_rd imm=1 asi=-2
+@q_r_r_asi .. ..... ...... rs1:5 0 asi:8 rs2_or_imm:5 \
+ &r_r_ri_asi rd=%qfp_rd imm=0
+@q_r_i_asi .. ..... ...... rs1:5 1 rs2_or_imm:s13 \
+ &r_r_ri_asi rd=%qfp_rd imm=1 asi=-2
@casa_imm .. rd:5 ...... rs1:5 1 00000000 rs2_or_imm:5 \
&r_r_ri_asi imm=1 asi=-2
@@ -325,10 +333,43 @@ NOP_v9 11 ----- 101101 ----- 0 00000000 ----- # PREFETCH
NOP_v9 11 ----- 101101 ----- 1 ------------- # PREFETCH
NOP_v9 11 ----- 111101 ----- - ------------- # PREFETCHA
-NCP 11 ----- 110000 ----- --------- ----- # v8 LDC
+{
+ [
+ LDFA 11 ..... 110000 ..... . ............. @r_r_r_asi
+ LDFA 11 ..... 110000 ..... . ............. @r_r_i_asi
+ ]
+ NCP 11 ----- 110000 ----- --------- ----- # v8 LDC
+}
NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR
-NCP 11 ----- 110011 ----- --------- ----- # v8 LDDC
-NCP 11 ----- 110100 ----- --------- ----- # v8 STC
+LDQFA 11 ..... 110010 ..... . ............. @q_r_r_asi
+LDQFA 11 ..... 110010 ..... . ............. @q_r_i_asi
+{
+ [
+ LDDFA 11 ..... 110011 ..... . ............. @d_r_r_asi
+ LDDFA 11 ..... 110011 ..... . ............. @d_r_i_asi
+ ]
+ NCP 11 ----- 110011 ----- --------- ----- # v8 LDDC
+}
+
+{
+ [
+ STFA 11 ..... 110100 ..... . ............. @r_r_r_asi
+ STFA 11 ..... 110100 ..... . ............. @r_r_i_asi
+ ]
+ NCP 11 ----- 110100 ----- --------- ----- # v8 STC
+}
NCP 11 ----- 110101 ----- --------- ----- # v8 STCSR
-NCP 11 ----- 110110 ----- --------- ----- # v8 STDCQ
-NCP 11 ----- 110111 ----- --------- ----- # v8 STDC
+{
+ [
+ STQFA 11 ..... 110110 ..... . ............. @q_r_r_asi
+ STQFA 11 ..... 110110 ..... . ............. @q_r_i_asi
+ ]
+ NCP 11 ----- 110110 ----- --------- ----- # v8 STDCQ
+}
+{
+ [
+ STDFA 11 ..... 110111 ..... . ............. @d_r_r_asi
+ STDFA 11 ..... 110111 ..... . ............. @d_r_i_asi
+ ]
+ NCP 11 ----- 110111 ----- --------- ----- # v8 STDC
+}
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 2770d4d84f..5710d1e381 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2105,12 +2105,6 @@ static DisasASI resolve_asi(DisasContext *dc, int asi, MemOp memop)
return (DisasASI){ type, asi, mem_idx, memop };
}
-static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop)
-{
- int asi = IS_IMM ? -2 : GET_FIELD(insn, 19, 26);
- return resolve_asi(dc, asi, memop);
-}
-
static void gen_ld_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr)
{
switch (da->type) {
@@ -2283,13 +2277,14 @@ static void gen_ldstub_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr)
}
}
-static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size,
- TCGv addr, int rd)
+static void gen_ldf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
+ TCGv addr, int rd)
{
MemOp memop = da->memop;
MemOp size = memop & MO_SIZE;
TCGv_i32 d32;
TCGv_i64 d64;
+ TCGv addr_tmp;
/* TODO: Use 128-bit load/store below. */
if (size == MO_128) {
@@ -2316,8 +2311,9 @@ static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size,
case MO_128:
d64 = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop);
- tcg_gen_addi_tl(addr, addr, 8);
- tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, memop);
+ addr_tmp = tcg_temp_new();
+ tcg_gen_addi_tl(addr_tmp, addr, 8);
+ tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx, memop);
tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
break;
default:
@@ -2328,18 +2324,16 @@ static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size,
case GET_ASI_BLOCK:
/* Valid for lddfa on aligned registers only. */
if (orig_size == MO_64 && (rd & 7) == 0) {
- TCGv eight;
- int i;
-
/* The first operation checks required alignment. */
- eight = tcg_constant_tl(8);
- for (i = 0; ; ++i) {
+ addr_tmp = tcg_temp_new();
+ for (int i = 0; ; ++i) {
tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx,
memop | (i == 0 ? MO_ALIGN_64 : 0));
if (i == 7) {
break;
}
- tcg_gen_add_tl(addr, addr, eight);
+ tcg_gen_addi_tl(addr_tmp, addr, 8);
+ addr = addr_tmp;
}
} else {
gen_exception(dc, TT_ILL_INSN);
@@ -2381,8 +2375,9 @@ static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size,
case MO_128:
d64 = tcg_temp_new_i64();
gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
- tcg_gen_addi_tl(addr, addr, 8);
- gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr,
+ addr_tmp = tcg_temp_new();
+ tcg_gen_addi_tl(addr_tmp, addr, 8);
+ gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr_tmp,
r_asi, r_mop);
tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
break;
@@ -2394,22 +2389,13 @@ static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size,
}
}
-static void __attribute__((unused))
-gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
-{
- MemOp sz = ctz32(size);
- DisasASI da = get_asi(dc, insn, MO_TE | sz);
-
- gen_address_mask(dc, addr);
- gen_ldf_asi0(dc, &da, sz, addr, rd);
-}
-
-static void gen_stf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size,
- TCGv addr, int rd)
+static void gen_stf_asi(DisasContext *dc, DisasASI *da, MemOp orig_size,
+ TCGv addr, int rd)
{
MemOp memop = da->memop;
MemOp size = memop & MO_SIZE;
TCGv_i32 d32;
+ TCGv addr_tmp;
/* TODO: Use 128-bit load/store below. */
if (size == MO_128) {
@@ -2439,8 +2425,9 @@ static void gen_stf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size,
write. */
tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
memop | MO_ALIGN_16);
- tcg_gen_addi_tl(addr, addr, 8);
- tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, memop);
+ addr_tmp = tcg_temp_new();
+ tcg_gen_addi_tl(addr_tmp, addr, 8);
+ tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx, memop);
break;
default:
g_assert_not_reached();
@@ -2450,18 +2437,16 @@ static void gen_stf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size,
case GET_ASI_BLOCK:
/* Valid for stdfa on aligned registers only. */
if (orig_size == MO_64 && (rd & 7) == 0) {
- TCGv eight;
- int i;
-
/* The first operation checks required alignment. */
- eight = tcg_constant_tl(8);
- for (i = 0; ; ++i) {
+ addr_tmp = tcg_temp_new();
+ for (int i = 0; ; ++i) {
tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx,
memop | (i == 0 ? MO_ALIGN_64 : 0));
if (i == 7) {
break;
}
- tcg_gen_add_tl(addr, addr, eight);
+ tcg_gen_addi_tl(addr_tmp, addr, 8);
+ addr = addr_tmp;
}
} else {
gen_exception(dc, TT_ILL_INSN);
@@ -2487,16 +2472,6 @@ static void gen_stf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size,
}
}
-static void __attribute__((unused))
-gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
-{
- MemOp sz = ctz32(size);
- DisasASI da = get_asi(dc, insn, MO_TE | sz);
-
- gen_address_mask(dc, addr);
- gen_stf_asi0(dc, &da, sz, addr, rd);
-}
-
static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
{
TCGv hi = gen_dest_gpr(dc, rd);
@@ -4815,7 +4790,7 @@ static bool do_ld_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz)
return true;
}
da = resolve_asi(dc, a->asi, MO_TE | sz);
- gen_ldf_asi0(dc, &da, sz, addr, a->rd);
+ gen_ldf_asi(dc, &da, sz, addr, a->rd);
gen_update_fprs_dirty(dc, a->rd);
return advance_pc(dc);
}
@@ -4824,6 +4799,10 @@ TRANS(LDF, ALL, do_ld_fpr, a, MO_32)
TRANS(LDDF, ALL, do_ld_fpr, a, MO_64)
TRANS(LDQF, ALL, do_ld_fpr, a, MO_128)
+TRANS(LDFA, 64, do_ld_fpr, a, MO_32)
+TRANS(LDDFA, 64, do_ld_fpr, a, MO_64)
+TRANS(LDQFA, 64, do_ld_fpr, a, MO_128)
+
static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz)
{
TCGv addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
@@ -4839,7 +4818,7 @@ static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp sz)
return true;
}
da = resolve_asi(dc, a->asi, MO_TE | sz);
- gen_stf_asi0(dc, &da, sz, addr, a->rd);
+ gen_stf_asi(dc, &da, sz, addr, a->rd);
return advance_pc(dc);
}
@@ -4847,6 +4826,10 @@ TRANS(STF, ALL, do_st_fpr, a, MO_32)
TRANS(STDF, ALL, do_st_fpr, a, MO_64)
TRANS(STQF, ALL, do_st_fpr, a, MO_128)
+TRANS(STFA, 64, do_st_fpr, a, MO_32)
+TRANS(STDFA, 64, do_st_fpr, a, MO_64)
+TRANS(STQFA, 64, do_st_fpr, a, MO_128)
+
static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a)
{
if (!avail_32(dc)) {
@@ -5680,64 +5663,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
(xop > 0x17 && xop <= 0x1d ) ||
(xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
- TCGv cpu_val = gen_dest_gpr(dc, rd);
-
- switch (xop) {
- case 0x0: /* ld, V9 lduw, load unsigned word */
- case 0x1: /* ldub, load unsigned byte */
- case 0x2: /* lduh, load unsigned halfword */
- case 0x3: /* ldd, load double word */
- case 0x9: /* ldsb, load signed byte */
- case 0xa: /* ldsh, load signed halfword */
- case 0xd: /* ldstub */
- case 0x0f: /* swap */
- case 0x10: /* lda, V9 lduwa, load word alternate */
- case 0x11: /* lduba, load unsigned byte alternate */
- case 0x12: /* lduha, load unsigned halfword alternate */
- case 0x13: /* ldda, load double word alternate */
- case 0x19: /* ldsba, load signed byte alternate */
- case 0x1a: /* ldsha, load signed halfword alternate */
- case 0x1d: /* ldstuba */
- case 0x1f: /* swapa */
- g_assert_not_reached(); /* in decodetree */
- case 0x08: /* V9 ldsw */
- case 0x0b: /* V9 ldx */
- case 0x18: /* V9 ldswa */
- case 0x1b: /* V9 ldxa */
- case 0x2d: /* V9 prefetch */
- case 0x3d: /* V9 prefetcha */
- goto illegal_insn; /* in decodetree */
-#ifdef TARGET_SPARC64
- case 0x30: /* V9 ldfa */
- if (gen_trap_ifnofpu(dc)) {
- goto jmp_insn;
- }
- gen_ldf_asi(dc, cpu_addr, insn, 4, rd);
- gen_update_fprs_dirty(dc, rd);
- goto skip_move;
- case 0x33: /* V9 lddfa */
- if (gen_trap_ifnofpu(dc)) {
- goto jmp_insn;
- }
- gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
- gen_update_fprs_dirty(dc, DFPREG(rd));
- goto skip_move;
- case 0x32: /* V9 ldqfa */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- if (gen_trap_ifnofpu(dc)) {
- goto jmp_insn;
- }
- gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
- gen_update_fprs_dirty(dc, QFPREG(rd));
- goto skip_move;
-#endif
- default:
- goto illegal_insn;
- }
- gen_store_gpr(dc, rd, cpu_val);
-#if defined(TARGET_SPARC64)
- skip_move: ;
-#endif
+ goto illegal_insn; /* in decodetree */
} else if (xop >= 0x20 && xop < 0x24) {
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
@@ -5793,36 +5719,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
goto illegal_insn;
}
} else if (xop > 0x33 && xop < 0x3f) {
- switch (xop) {
-#ifdef TARGET_SPARC64
- case 0x34: /* V9 stfa */
- if (gen_trap_ifnofpu(dc)) {
- goto jmp_insn;
- }
- gen_stf_asi(dc, cpu_addr, insn, 4, rd);
- break;
- case 0x36: /* V9 stqfa */
- {
- CHECK_FPU_FEATURE(dc, FLOAT128);
- if (gen_trap_ifnofpu(dc)) {
- goto jmp_insn;
- }
- gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
- }
- break;
- case 0x37: /* V9 stdfa */
- if (gen_trap_ifnofpu(dc)) {
- goto jmp_insn;
- }
- gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
- break;
-#endif
- case 0x3e: /* V9 casxa */
- case 0x3c: /* V9 or LEON3 casa */
- goto illegal_insn; /* in decodetree */
- default:
- goto illegal_insn;
- }
+ goto illegal_insn; /* in decodetree */
} else {
goto illegal_insn;
}
--
2.34.1
next prev parent reply other threads:[~2023-10-22 6:13 UTC|newest]
Thread overview: 93+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-22 5:59 [PATCH v4 00/90] target/sparc: Convert to decodetree Richard Henderson
2023-10-22 5:59 ` [PATCH v4 01/90] target/sparc: Clear may_lookup for npc == DYNAMIC_PC Richard Henderson
2023-10-22 5:59 ` [PATCH v4 02/90] target/sparc: Implement check_align inline Richard Henderson
2023-10-22 5:59 ` [PATCH v4 03/90] target/sparc: Avoid helper_raise_exception in helper_st_asi Richard Henderson
2023-10-22 5:59 ` [PATCH v4 04/90] target/sparc: Set TCG_GUEST_DEFAULT_MO Richard Henderson
2023-10-22 5:59 ` [PATCH v4 05/90] configs: Enable MTTCG for sparc, sparc64 Richard Henderson
2023-10-22 5:59 ` [PATCH v4 06/90] target/sparc: Define features via cpu-feature.h.inc Richard Henderson
2023-10-22 5:59 ` [PATCH v4 07/90] target/sparc: Use CPU_FEATURE_BIT_* for cpu properties Richard Henderson
2023-10-22 5:59 ` [PATCH v4 08/90] target/sparc: Remove sparcv7 cpu features Richard Henderson
2023-10-22 5:59 ` [PATCH v4 09/90] target/sparc: Add decodetree infrastructure Richard Henderson
2023-10-22 5:59 ` [PATCH v4 10/90] target/sparc: Define AM_CHECK for sparc32 Richard Henderson
2023-10-22 5:59 ` [PATCH v4 11/90] target/sparc: Move CALL to decodetree Richard Henderson
2023-10-22 5:59 ` [PATCH v4 12/90] target/sparc: Move BPcc and Bicc " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 13/90] target/sparc: Move BPr " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 14/90] target/sparc: Move FBPfcc and FBfcc " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 15/90] target/sparc: Merge gen_cond with only caller Richard Henderson
2023-10-22 5:59 ` [PATCH v4 16/90] target/sparc: Merge gen_fcond " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 17/90] target/sparc: Merge gen_branch_[an] " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 18/90] target/sparc: Pass DisasCompare to advance_jump_cond Richard Henderson
2023-10-22 5:59 ` [PATCH v4 19/90] target/sparc: Move SETHI to decodetree Richard Henderson
2023-10-22 5:59 ` [PATCH v4 20/90] target/sparc: Move Tcc " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 21/90] target/sparc: Move RDASR, STBAR, MEMBAR " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 22/90] target/sparc: Move RDPSR, RDHPR " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 23/90] target/sparc: Move RDWIM, RDPR " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 24/90] target/sparc: Move RDTBR, FLUSHW " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 25/90] target/sparc: Move WRASR " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 26/90] target/sparc: Move WRPSR, SAVED, RESTORED " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 27/90] target/sparc: Move WRWIM, WRPR " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 28/90] target/sparc: Move WRTBR, WRHPR " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 29/90] target/sparc: Move basic arithmetic " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 30/90] target/sparc: Move ADDC " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 31/90] target/sparc: Move MULX " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 32/90] target/sparc: Move UMUL, SMUL " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 33/90] target/sparc: Move SUBC " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 34/90] target/sparc: Move UDIVX, SDIVX " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 35/90] target/sparc: Move UDIV, SDIV " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 36/90] target/sparc: Move TADD, TSUB, MULS " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 37/90] target/sparc: Move SLL, SRL, SRA " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 38/90] target/sparc: Move MOVcc, MOVR " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 39/90] target/sparc: Move POPC " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 40/90] target/sparc: Convert remaining v8 coproc insns " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 41/90] target/sparc: Move JMPL, RETT, RETURN " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 42/90] target/sparc: Move FLUSH, SAVE, RESTORE " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 43/90] target/sparc: Move DONE, RETRY " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 44/90] target/sparc: Split out resolve_asi Richard Henderson
2023-10-22 5:59 ` [PATCH v4 45/90] target/sparc: Drop ifdef around get_asi and friends Richard Henderson
2023-10-22 5:59 ` [PATCH v4 46/90] target/sparc: Split out ldst functions with asi pre-computed Richard Henderson
2023-10-22 5:59 ` [PATCH v4 47/90] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX Richard Henderson
2023-10-22 5:59 ` [PATCH v4 48/90] target/sparc: Move simple integer load/store to decodetree Richard Henderson
2023-10-22 5:59 ` [PATCH v4 49/90] target/sparc: Move asi " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 50/90] target/sparc: Move LDSTUB, LDSTUBA " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 51/90] target/sparc: Move SWAP, SWAPA " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 52/90] target/sparc: Move CASA, CASXA " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 53/90] target/sparc: Move PREFETCH, PREFETCHA " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 54/90] target/sparc: Split out fp ldst functions with asi precomputed Richard Henderson
2023-10-22 5:59 ` [PATCH v4 55/90] target/sparc: Move simple fp load/store to decodetree Richard Henderson
2023-10-22 5:59 ` Richard Henderson [this message]
2023-10-22 5:59 ` [PATCH v4 57/90] target/sparc: Move LDFSR, STFSR " Richard Henderson
2023-10-22 5:59 ` [PATCH v4 58/90] target/sparc: Merge LDFSR, LDXFSR implementations Richard Henderson
2023-10-22 6:00 ` [PATCH v4 59/90] target/sparc: Move EDGE* to decodetree Richard Henderson
2023-10-22 6:00 ` [PATCH v4 60/90] target/sparc: Move ARRAY* " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 61/90] target/sparc: Move ADDRALIGN* " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 62/90] target/sparc: Move BMASK " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 63/90] target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 64/90] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 65/90] target/sparc: Use tcg_gen_vec_{add,sub}* Richard Henderson
2023-10-22 6:00 ` [PATCH v4 66/90] target/sparc: Move gen_ne_fop_FFF insns to decodetree Richard Henderson
2023-10-22 6:00 ` [PATCH v4 67/90] target/sparc: Move gen_ne_fop_DDD " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 68/90] target/sparc: Move PDIST " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 69/90] target/sparc: Move gen_gsr_fop_DDD insns " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 70/90] target/sparc: Move gen_fop_FF " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 71/90] target/sparc: Move gen_fop_DD " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 72/90] target/sparc: Move FSQRTq " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 73/90] target/sparc: Move gen_fop_FFF insns " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 74/90] target/sparc: Move gen_fop_DDD " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 75/90] target/sparc: Move gen_fop_QQQ " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 76/90] target/sparc: Move FSMULD " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 77/90] target/sparc: Move FDMULQ " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 78/90] target/sparc: Move gen_fop_FD insns " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 79/90] target/sparc: Move FiTOd, FsTOd, FsTOx " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 80/90] target/sparc: Move FqTOs, FqTOi " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 81/90] target/sparc: Move FqTOd, FqTOx " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 82/90] target/sparc: Move FiTOq, FsTOq " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 83/90] target/sparc: Move FdTOq, FxTOq " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 84/90] target/sparc: Move FMOVq, FNEGq, FABSq " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 85/90] target/sparc: Move FMOVR, FMOVcc, FMOVfcc " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 86/90] target/sparc: Convert FCMP, FCMPE " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 87/90] target/sparc: Move FPCMP* " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 88/90] target/sparc: Move FPACK16, FPACKFIX " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 89/90] target/sparc: Convert FZERO, FONE " Richard Henderson
2023-10-22 6:00 ` [PATCH v4 90/90] target/sparc: Remove disas_sparc_legacy Richard Henderson
2023-10-22 12:44 ` [PATCH v4 00/90] target/sparc: Convert to decodetree Mark Cave-Ayland
2023-10-22 17:10 ` Richard Henderson
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