* [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT
@ 2023-10-19 13:26 Sunil V L
2023-10-19 13:26 ` [PATCH v3 01/12] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location Sunil V L
` (11 more replies)
0 siblings, 12 replies; 30+ messages in thread
From: Sunil V L @ 2023-10-19 13:26 UTC (permalink / raw)
To: qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Andrew Jones, Atish Kumar Patra, Haibo Xu, Sunil V L
This series primarily enables external interrupt controllers (AIA and PLIC)
in ACPI tables for RISC-V virt platform. It also updates RHCT with CMO and
MMU related information.
Below ECRs for these changes are approved by ASWG and will be
available in next ACPI spec release.
1) MADT (AIA) - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view?usp=sharing
2) RHCT - https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view?usp=sharing
First two patches in this series are to migrate a couple of functions from
ARM architecture to common code so that RISC-V doesn't need to duplicate
the same.
The patch set is based on Alistair's riscv-to-apply.next branch.
These changes are also available in riscv_acpi_b2_v3 branch at:
https://github.com/vlsunil/qemu/
Changes since v2:
1) Rebased to latest riscv-to-apply.next branch which needed
changing ext_icboz to ext_zicboz in CMO patch.
2) Fixed node type in MMU node.
3) Added latest tags.
Changes since v1:
1) As per Igor's suggestion, migrated fw_cfg and virtio creation
functions to device specific file instead of generic aml-build.c.
Since ACPI is optional, new files are created and enabled for
build only when CONFIG_ACPI is enabled.
2) As per Igor's suggestion, properties are added to the GPEX PCI
host to indicate MMIO ranges. The platform fw can initialize
these to appropriate values and the DSDT generator can fetch
the information from the host bus itself. This makes the code
generic instead of machine specific.
3) Added PLIC patch from Haibo.
4) Rebased to latest riscv-to-apply.next and added RB tags as
appropriate.
Sunil V L (12):
hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location
hw/arm/virt-acpi-build.c: Migrate virtio creation to common location
hw/riscv: virt: Make few IMSIC macros and functions public
hw/riscv/virt-acpi-build.c: Add AIA support in RINTC
hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT
hw/riscv/virt-acpi-build.c: Add APLIC in the MADT
hw/riscv/virt-acpi-build.c: Add CMO information in RHCT
hw/riscv/virt-acpi-build.c: Add MMU node in RHCT
hw/pci-host/gpex: Define properties for MMIO ranges
hw/riscv/virt: Update GPEX MMIO related properties
hw/riscv/virt-acpi-build.c: Add IO controllers and devices
hw/riscv/virt-acpi-build.c: Add PLIC in MADT
hw/arm/virt-acpi-build.c | 48 +----
hw/nvram/fw_cfg-acpi.c | 17 ++
hw/nvram/meson.build | 1 +
hw/pci-host/gpex-acpi.c | 13 ++
hw/pci-host/gpex.c | 12 ++
hw/riscv/Kconfig | 1 +
hw/riscv/virt-acpi-build.c | 342 +++++++++++++++++++++++++++++---
hw/riscv/virt.c | 72 +++----
hw/virtio/meson.build | 1 +
hw/virtio/virtio-acpi.c | 28 +++
include/hw/nvram/fw_cfg_acpi.h | 9 +
include/hw/pci-host/gpex.h | 28 ++-
include/hw/riscv/virt.h | 26 +++
include/hw/virtio/virtio-acpi.h | 11 +
14 files changed, 492 insertions(+), 117 deletions(-)
create mode 100644 hw/nvram/fw_cfg-acpi.c
create mode 100644 hw/virtio/virtio-acpi.c
create mode 100644 include/hw/nvram/fw_cfg_acpi.h
create mode 100644 include/hw/virtio/virtio-acpi.h
--
2.34.1
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v3 01/12] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location
2023-10-19 13:26 [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
@ 2023-10-19 13:26 ` Sunil V L
2023-10-23 12:22 ` Andrew Jones
2023-10-19 13:26 ` [PATCH v3 02/12] hw/arm/virt-acpi-build.c: Migrate virtio " Sunil V L
` (10 subsequent siblings)
11 siblings, 1 reply; 30+ messages in thread
From: Sunil V L @ 2023-10-19 13:26 UTC (permalink / raw)
To: qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Andrew Jones, Atish Kumar Patra, Haibo Xu, Sunil V L
RISC-V also needs to use the same code to create fw_cfg in DSDT. So, avoid
code duplication by moving the code in arm and riscv to a device specific
file.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/arm/virt-acpi-build.c | 19 ++-----------------
hw/nvram/fw_cfg-acpi.c | 17 +++++++++++++++++
hw/nvram/meson.build | 1 +
hw/riscv/virt-acpi-build.c | 19 ++-----------------
include/hw/nvram/fw_cfg_acpi.h | 9 +++++++++
5 files changed, 31 insertions(+), 34 deletions(-)
create mode 100644 hw/nvram/fw_cfg-acpi.c
create mode 100644 include/hw/nvram/fw_cfg_acpi.h
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 6b674231c2..b8e725d953 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -35,7 +35,7 @@
#include "target/arm/cpu.h"
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
-#include "hw/nvram/fw_cfg.h"
+#include "hw/nvram/fw_cfg_acpi.h"
#include "hw/acpi/bios-linker-loader.h"
#include "hw/acpi/aml-build.h"
#include "hw/acpi/utils.h"
@@ -94,21 +94,6 @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
aml_append(scope, dev);
}
-static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
-{
- Aml *dev = aml_device("FWCF");
- aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
- /* device present, functioning, decoding, not shown in UI */
- aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
- aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
- Aml *crs = aml_resource_template();
- aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
- fw_cfg_memmap->size, AML_READ_WRITE));
- aml_append(dev, aml_name_decl("_CRS", crs));
- aml_append(scope, dev);
-}
-
static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
{
Aml *dev, *crs;
@@ -864,7 +849,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
if (vmc->acpi_expose_flash) {
acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
}
- acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
+ fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
diff --git a/hw/nvram/fw_cfg-acpi.c b/hw/nvram/fw_cfg-acpi.c
new file mode 100644
index 0000000000..4eeb81bc36
--- /dev/null
+++ b/hw/nvram/fw_cfg-acpi.c
@@ -0,0 +1,17 @@
+#include "hw/nvram/fw_cfg_acpi.h"
+#include "hw/acpi/aml-build.h"
+
+void fw_cfg_acpi_dsdt_add(Aml *scope, const MemMapEntry *fw_cfg_memmap)
+{
+ Aml *dev = aml_device("FWCF");
+ aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
+ /* device present, functioning, decoding, not shown in UI */
+ aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
+ aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+
+ Aml *crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
+ fw_cfg_memmap->size, AML_READ_WRITE));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+}
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
index 75e415b1a0..4996c72456 100644
--- a/hw/nvram/meson.build
+++ b/hw/nvram/meson.build
@@ -17,3 +17,4 @@ system_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files(
system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
+specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c'))
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 7331248f59..d8772c2821 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -28,6 +28,7 @@
#include "hw/acpi/acpi.h"
#include "hw/acpi/aml-build.h"
#include "hw/acpi/utils.h"
+#include "hw/nvram/fw_cfg_acpi.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/reset.h"
@@ -97,22 +98,6 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
}
}
-static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
-{
- Aml *dev = aml_device("FWCF");
- aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
-
- /* device present, functioning, decoding, not shown in UI */
- aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
- aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
- Aml *crs = aml_resource_template();
- aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
- fw_cfg_memmap->size, AML_READ_WRITE));
- aml_append(dev, aml_name_decl("_CRS", crs));
- aml_append(scope, dev);
-}
-
/* RHCT Node[N] starts at offset 56 */
#define RHCT_NODE_ARRAY_OFFSET 56
@@ -226,7 +211,7 @@ static void build_dsdt(GArray *table_data,
scope = aml_scope("\\_SB");
acpi_dsdt_add_cpus(scope, s);
- acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
+ fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
aml_append(dsdt, scope);
diff --git a/include/hw/nvram/fw_cfg_acpi.h b/include/hw/nvram/fw_cfg_acpi.h
new file mode 100644
index 0000000000..6e2c5f04b7
--- /dev/null
+++ b/include/hw/nvram/fw_cfg_acpi.h
@@ -0,0 +1,9 @@
+#ifndef FW_CFG_ACPI_H
+#define FW_CFG_ACPI_H
+
+#include "qemu/osdep.h"
+#include "exec/hwaddr.h"
+
+void fw_cfg_acpi_dsdt_add(Aml *scope, const MemMapEntry *fw_cfg_memmap);
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 02/12] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location
2023-10-19 13:26 [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
2023-10-19 13:26 ` [PATCH v3 01/12] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location Sunil V L
@ 2023-10-19 13:26 ` Sunil V L
2023-10-20 11:42 ` Daniel Henrique Barboza
2023-10-23 12:28 ` Andrew Jones
2023-10-19 13:26 ` [PATCH v3 03/12] hw/riscv: virt: Make few IMSIC macros and functions public Sunil V L
` (9 subsequent siblings)
11 siblings, 2 replies; 30+ messages in thread
From: Sunil V L @ 2023-10-19 13:26 UTC (permalink / raw)
To: qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Andrew Jones, Atish Kumar Patra, Haibo Xu, Sunil V L
RISC-V also needs to create the virtio in DSDT in the same way as ARM. So,
instead of duplicating the code, move this function to the device specific
file which is common across architectures.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/arm/virt-acpi-build.c | 29 ++---------------------------
hw/virtio/meson.build | 1 +
hw/virtio/virtio-acpi.c | 28 ++++++++++++++++++++++++++++
include/hw/virtio/virtio-acpi.h | 11 +++++++++++
4 files changed, 42 insertions(+), 27 deletions(-)
create mode 100644 hw/virtio/virtio-acpi.c
create mode 100644 include/hw/virtio/virtio-acpi.h
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index b8e725d953..69733f6663 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -58,6 +58,7 @@
#include "migration/vmstate.h"
#include "hw/acpi/ghes.h"
#include "hw/acpi/viot.h"
+#include "hw/virtio/virtio-acpi.h"
#define ARM_SPI_BASE 32
@@ -118,32 +119,6 @@ static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
aml_append(scope, dev);
}
-static void acpi_dsdt_add_virtio(Aml *scope,
- const MemMapEntry *virtio_mmio_memmap,
- uint32_t mmio_irq, int num)
-{
- hwaddr base = virtio_mmio_memmap->base;
- hwaddr size = virtio_mmio_memmap->size;
- int i;
-
- for (i = 0; i < num; i++) {
- uint32_t irq = mmio_irq + i;
- Aml *dev = aml_device("VR%02u", i);
- aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
- aml_append(dev, aml_name_decl("_UID", aml_int(i)));
- aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
-
- Aml *crs = aml_resource_template();
- aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
- aml_append(crs,
- aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
- AML_EXCLUSIVE, &irq, 1));
- aml_append(dev, aml_name_decl("_CRS", crs));
- aml_append(scope, dev);
- base += size;
- }
-}
-
static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
uint32_t irq, VirtMachineState *vms)
{
@@ -850,7 +825,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
}
fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
- acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
+ virtio_acpi_dsdt_add(scope, &memmap[VIRT_MMIO],
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
if (vms->acpi_dev) {
diff --git a/hw/virtio/meson.build b/hw/virtio/meson.build
index c0055a7832..9d62097a21 100644
--- a/hw/virtio/meson.build
+++ b/hw/virtio/meson.build
@@ -79,3 +79,4 @@ system_ss.add(when: 'CONFIG_ALL', if_true: files('virtio-stub.c'))
system_ss.add(files('virtio-hmp-cmds.c'))
specific_ss.add_all(when: 'CONFIG_VIRTIO', if_true: specific_virtio_ss)
+system_ss.add(when: 'CONFIG_ACPI', if_true: files('virtio-acpi.c'))
diff --git a/hw/virtio/virtio-acpi.c b/hw/virtio/virtio-acpi.c
new file mode 100644
index 0000000000..977499defd
--- /dev/null
+++ b/hw/virtio/virtio-acpi.c
@@ -0,0 +1,28 @@
+#include "hw/virtio/virtio-acpi.h"
+#include "hw/acpi/aml-build.h"
+
+void virtio_acpi_dsdt_add(Aml *scope,
+ const MemMapEntry *virtio_mmio_memmap,
+ uint32_t mmio_irq, int num)
+{
+ hwaddr base = virtio_mmio_memmap->base;
+ hwaddr size = virtio_mmio_memmap->size;
+ int i;
+
+ for (i = 0; i < num; i++) {
+ uint32_t irq = mmio_irq + i;
+ Aml *dev = aml_device("VR%02u", i);
+ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(i)));
+ aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
+
+ Aml *crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
+ aml_append(crs,
+ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, &irq, 1));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+ base += size;
+ }
+}
diff --git a/include/hw/virtio/virtio-acpi.h b/include/hw/virtio/virtio-acpi.h
new file mode 100644
index 0000000000..b8687b1b42
--- /dev/null
+++ b/include/hw/virtio/virtio-acpi.h
@@ -0,0 +1,11 @@
+#ifndef VIRTIO_ACPI_H
+#define VIRTIO_ACPI_H
+
+#include "qemu/osdep.h"
+#include "exec/hwaddr.h"
+
+void virtio_acpi_dsdt_add(Aml *scope, const MemMapEntry *virtio_mmio_memmap,
+ uint32_t mmio_irq, int num);
+
+#endif
+
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 03/12] hw/riscv: virt: Make few IMSIC macros and functions public
2023-10-19 13:26 [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
2023-10-19 13:26 ` [PATCH v3 01/12] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location Sunil V L
2023-10-19 13:26 ` [PATCH v3 02/12] hw/arm/virt-acpi-build.c: Migrate virtio " Sunil V L
@ 2023-10-19 13:26 ` Sunil V L
2023-10-23 12:31 ` Andrew Jones
2023-10-19 13:26 ` [PATCH v3 04/12] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC Sunil V L
` (8 subsequent siblings)
11 siblings, 1 reply; 30+ messages in thread
From: Sunil V L @ 2023-10-19 13:26 UTC (permalink / raw)
To: qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Andrew Jones, Atish Kumar Patra, Haibo Xu, Sunil V L
Some macros and static function related to IMSIC are defined in virt.c.
They are required in virt-acpi-build.c. So, make them public.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 25 +------------------------
include/hw/riscv/virt.h | 25 +++++++++++++++++++++++++
2 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 1732c42915..085654ab2f 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -38,7 +38,6 @@
#include "kvm/kvm_riscv.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/intc/riscv_aplic.h"
-#include "hw/intc/riscv_imsic.h"
#include "hw/intc/sifive_plic.h"
#include "hw/misc/sifive_test.h"
#include "hw/platform-bus.h"
@@ -54,28 +53,6 @@
#include "hw/acpi/aml-build.h"
#include "qapi/qapi-visit-common.h"
-/*
- * The virt machine physical address space used by some of the devices
- * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
- * number of CPUs, and number of IMSIC guest files.
- *
- * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
- * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
- * of virt machine physical address space.
- */
-
-#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
-#if VIRT_IMSIC_GROUP_MAX_SIZE < \
- IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
-#error "Can't accommodate single IMSIC group in address space"
-#endif
-
-#define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \
- VIRT_IMSIC_GROUP_MAX_SIZE)
-#if 0x4000000 < VIRT_IMSIC_MAX_SIZE
-#error "Can't accommodate all IMSIC groups in address space"
-#endif
-
/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
static bool virt_use_kvm_aia(RISCVVirtState *s)
{
@@ -512,7 +489,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
g_free(plic_cells);
}
-static uint32_t imsic_num_bits(uint32_t count)
+uint32_t imsic_num_bits(uint32_t count)
{
uint32_t ret = 0;
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index e5c474b26e..5b03575ed3 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -23,6 +23,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/sysbus.h"
#include "hw/block/flash.h"
+#include "hw/intc/riscv_imsic.h"
#define VIRT_CPUS_MAX_BITS 9
#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
@@ -127,4 +128,28 @@ enum {
bool virt_is_acpi_enabled(RISCVVirtState *s);
void virt_acpi_setup(RISCVVirtState *vms);
+uint32_t imsic_num_bits(uint32_t count);
+
+/*
+ * The virt machine physical address space used by some of the devices
+ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
+ * number of CPUs, and number of IMSIC guest files.
+ *
+ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
+ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
+ * of virt machine physical address space.
+ */
+
+#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
+#if VIRT_IMSIC_GROUP_MAX_SIZE < \
+ IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
+#error "Can't accomodate single IMSIC group in address space"
+#endif
+
+#define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \
+ VIRT_IMSIC_GROUP_MAX_SIZE)
+#if 0x4000000 < VIRT_IMSIC_MAX_SIZE
+#error "Can't accomodate all IMSIC groups in address space"
+#endif
+
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 04/12] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC
2023-10-19 13:26 [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
` (2 preceding siblings ...)
2023-10-19 13:26 ` [PATCH v3 03/12] hw/riscv: virt: Make few IMSIC macros and functions public Sunil V L
@ 2023-10-19 13:26 ` Sunil V L
2023-10-24 0:07 ` Alistair Francis
2023-10-19 13:26 ` [PATCH v3 05/12] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT Sunil V L
` (7 subsequent siblings)
11 siblings, 1 reply; 30+ messages in thread
From: Sunil V L @ 2023-10-19 13:26 UTC (permalink / raw)
To: qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Andrew Jones, Atish Kumar Patra, Haibo Xu, Sunil V L
Update the RINTC structure in MADT with AIA related fields.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
hw/riscv/virt-acpi-build.c | 66 +++++++++++++++++++++++++++++++++++---
1 file changed, 62 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index d8772c2821..073c85f327 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -38,6 +38,7 @@
#include "hw/intc/riscv_aclint.h"
#define ACPI_BUILD_TABLE_SIZE 0x20000
+#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
typedef struct AcpiBuildState {
/* Copy of table in RAM (for patching) */
@@ -58,18 +59,42 @@ static void acpi_align_size(GArray *blob, unsigned align)
}
static void riscv_acpi_madt_add_rintc(uint32_t uid,
+ uint32_t local_cpu_id,
const CPUArchIdList *arch_ids,
- GArray *entry)
+ GArray *entry,
+ RISCVVirtAIAType aia_type,
+ uint64_t imsic_addr,
+ uint32_t imsic_size)
{
uint64_t hart_id = arch_ids->cpus[uid].arch_id;
build_append_int_noprefix(entry, 0x18, 1); /* Type */
- build_append_int_noprefix(entry, 20, 1); /* Length */
+ build_append_int_noprefix(entry, 36, 1); /* Length */
build_append_int_noprefix(entry, 1, 1); /* Version */
build_append_int_noprefix(entry, 0, 1); /* Reserved */
build_append_int_noprefix(entry, 0x1, 4); /* Flags */
build_append_int_noprefix(entry, hart_id, 8); /* Hart ID */
build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */
+ /* External Interrupt Controller ID */
+ if (aia_type == VIRT_AIA_TYPE_APLIC) {
+ build_append_int_noprefix(entry,
+ ACPI_BUILD_INTC_ID(
+ arch_ids->cpus[uid].props.node_id,
+ local_cpu_id),
+ 4);
+ } else {
+ build_append_int_noprefix(entry, 0, 4);
+ }
+
+ if (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+ /* IMSIC Base address */
+ build_append_int_noprefix(entry, imsic_addr, 8);
+ /* IMSIC Size */
+ build_append_int_noprefix(entry, imsic_size, 4);
+ } else {
+ build_append_int_noprefix(entry, 0, 8);
+ build_append_int_noprefix(entry, 0, 4);
+ }
}
static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
@@ -77,6 +102,11 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
MachineClass *mc = MACHINE_GET_CLASS(s);
MachineState *ms = MACHINE(s);
const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
+ uint64_t imsic_socket_addr, imsic_addr;
+ uint8_t guest_index_bits;
+ uint32_t imsic_size, local_cpu_id, socket_id;
+
+ guest_index_bits = imsic_num_bits(s->aia_guests + 1);
for (int i = 0; i < arch_ids->len; i++) {
Aml *dev;
@@ -87,8 +117,19 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
aml_append(dev, aml_name_decl("_UID",
aml_int(arch_ids->cpus[i].arch_id)));
+ socket_id = arch_ids->cpus[i].props.node_id;
+ local_cpu_id = (arch_ids->cpus[i].arch_id -
+ riscv_socket_first_hartid(ms, socket_id)) %
+ riscv_socket_hart_count(ms, socket_id);
/* build _MAT object */
- riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf);
+ imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base +
+ (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE);
+ imsic_addr = imsic_socket_addr +
+ local_cpu_id * IMSIC_HART_SIZE(guest_index_bits);
+ imsic_size = IMSIC_HART_SIZE(guest_index_bits);
+
+ riscv_acpi_madt_add_rintc(i, local_cpu_id, arch_ids, madt_buf,
+ s->aia_type, imsic_addr, imsic_size);
aml_append(dev, aml_name_decl("_MAT",
aml_buffer(madt_buf->len,
(uint8_t *)madt_buf->data)));
@@ -227,6 +268,7 @@ static void build_dsdt(GArray *table_data,
* 5.2.12 Multiple APIC Description Table (MADT)
* REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15
* https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
+ * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view
*/
static void build_madt(GArray *table_data,
BIOSLinker *linker,
@@ -235,6 +277,12 @@ static void build_madt(GArray *table_data,
MachineClass *mc = MACHINE_GET_CLASS(s);
MachineState *ms = MACHINE(s);
const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
+ uint64_t imsic_socket_addr, imsic_addr;
+ uint8_t guest_index_bits;
+ uint32_t imsic_size;
+ uint32_t local_cpu_id, socket_id;
+
+ guest_index_bits = imsic_num_bits(s->aia_guests + 1);
AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id,
.oem_table_id = s->oem_table_id };
@@ -246,7 +294,17 @@ static void build_madt(GArray *table_data,
/* RISC-V Local INTC structures per HART */
for (int i = 0; i < arch_ids->len; i++) {
- riscv_acpi_madt_add_rintc(i, arch_ids, table_data);
+ socket_id = arch_ids->cpus[i].props.node_id;
+ local_cpu_id = (arch_ids->cpus[i].arch_id -
+ riscv_socket_first_hartid(ms, socket_id)) %
+ riscv_socket_hart_count(ms, socket_id);
+ imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base +
+ (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE);
+ imsic_addr = imsic_socket_addr +
+ local_cpu_id * IMSIC_HART_SIZE(guest_index_bits);
+ imsic_size = IMSIC_HART_SIZE(guest_index_bits);
+ riscv_acpi_madt_add_rintc(i, local_cpu_id, arch_ids, table_data,
+ s->aia_type, imsic_addr, imsic_size);
}
acpi_table_end(linker, &table);
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 05/12] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT
2023-10-19 13:26 [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
` (3 preceding siblings ...)
2023-10-19 13:26 ` [PATCH v3 04/12] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC Sunil V L
@ 2023-10-19 13:26 ` Sunil V L
2023-10-23 12:42 ` Andrew Jones
2023-10-24 0:10 ` Alistair Francis
2023-10-19 13:26 ` [PATCH v3 06/12] hw/riscv/virt-acpi-build.c: Add APLIC " Sunil V L
` (6 subsequent siblings)
11 siblings, 2 replies; 30+ messages in thread
From: Sunil V L @ 2023-10-19 13:26 UTC (permalink / raw)
To: qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Andrew Jones, Atish Kumar Patra, Haibo Xu, Sunil V L
Add IMSIC structure in MADT when IMSIC is configured.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
hw/riscv/virt-acpi-build.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 073c85f327..7f1a370e54 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -281,8 +281,20 @@ static void build_madt(GArray *table_data,
uint8_t guest_index_bits;
uint32_t imsic_size;
uint32_t local_cpu_id, socket_id;
+ uint8_t hart_index_bits, group_index_bits, group_index_shift;
+ uint16_t imsic_max_hart_per_socket = 0;
+ uint8_t socket;
+
+ for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+ if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
+ imsic_max_hart_per_socket = s->soc[socket].num_harts;
+ }
+ }
guest_index_bits = imsic_num_bits(s->aia_guests + 1);
+ hart_index_bits = imsic_num_bits(imsic_max_hart_per_socket);
+ group_index_bits = imsic_num_bits(riscv_socket_count(ms));
+ group_index_shift = IMSIC_MMIO_GROUP_MIN_SHIFT;
AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id,
.oem_table_id = s->oem_table_id };
@@ -307,6 +319,28 @@ static void build_madt(GArray *table_data,
s->aia_type, imsic_addr, imsic_size);
}
+ /* IMSIC */
+ if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
+ /* IMSIC */
+ build_append_int_noprefix(table_data, 0x19, 1); /* Type */
+ build_append_int_noprefix(table_data, 16, 1); /* Length */
+ build_append_int_noprefix(table_data, 1, 1); /* Version */
+ build_append_int_noprefix(table_data, 0, 1); /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4); /* Flags */
+ /* Number of supervisor mode Interrupt Identities */
+ build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
+ /* Number of guest mode Interrupt Identities */
+ build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
+ /* Guest Index Bits */
+ build_append_int_noprefix(table_data, guest_index_bits, 1);
+ /* Hart Index Bits */
+ build_append_int_noprefix(table_data, hart_index_bits, 1);
+ /* Group Index Bits */
+ build_append_int_noprefix(table_data, group_index_bits, 1);
+ /* Group Index Shift */
+ build_append_int_noprefix(table_data, group_index_shift, 1);
+ }
+
acpi_table_end(linker, &table);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 06/12] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT
2023-10-19 13:26 [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
` (4 preceding siblings ...)
2023-10-19 13:26 ` [PATCH v3 05/12] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT Sunil V L
@ 2023-10-19 13:26 ` Sunil V L
2023-10-23 12:46 ` Andrew Jones
2023-10-24 0:10 ` Alistair Francis
2023-10-19 13:26 ` [PATCH v3 07/12] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT Sunil V L
` (5 subsequent siblings)
11 siblings, 2 replies; 30+ messages in thread
From: Sunil V L @ 2023-10-19 13:26 UTC (permalink / raw)
To: qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Andrew Jones, Atish Kumar Patra, Haibo Xu, Sunil V L
Add APLIC structures for each socket in the MADT when system is configured
with APLIC as the external wired interrupt controller.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
hw/riscv/virt-acpi-build.c | 36 ++++++++++++++++++++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 7f1a370e54..8fa358d034 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -277,9 +277,9 @@ static void build_madt(GArray *table_data,
MachineClass *mc = MACHINE_GET_CLASS(s);
MachineState *ms = MACHINE(s);
const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
- uint64_t imsic_socket_addr, imsic_addr;
+ uint64_t imsic_socket_addr, imsic_addr, aplic_addr;
+ uint32_t imsic_size, gsi_base;
uint8_t guest_index_bits;
- uint32_t imsic_size;
uint32_t local_cpu_id, socket_id;
uint8_t hart_index_bits, group_index_bits, group_index_shift;
uint16_t imsic_max_hart_per_socket = 0;
@@ -341,6 +341,38 @@ static void build_madt(GArray *table_data,
build_append_int_noprefix(table_data, group_index_shift, 1);
}
+ if (s->aia_type != VIRT_AIA_TYPE_NONE) {
+ /* APLICs */
+ for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+ aplic_addr = s->memmap[VIRT_APLIC_S].base +
+ s->memmap[VIRT_APLIC_S].size * socket;
+ gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+ build_append_int_noprefix(table_data, 0x1A, 1); /* Type */
+ build_append_int_noprefix(table_data, 36, 1); /* Length */
+ build_append_int_noprefix(table_data, 1, 1); /* Version */
+ build_append_int_noprefix(table_data, socket, 1); /* APLIC ID */
+ build_append_int_noprefix(table_data, 0, 4); /* Flags */
+ build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */
+ /* Number of IDCs */
+ if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
+ build_append_int_noprefix(table_data,
+ s->soc[socket].num_harts,
+ 2);
+ } else {
+ build_append_int_noprefix(table_data, 0, 2);
+ }
+ /* Total External Interrupt Sources Supported */
+ build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_SOURCES, 2);
+ /* Global System Interrupt Base */
+ build_append_int_noprefix(table_data, gsi_base, 4);
+ /* APLIC Address */
+ build_append_int_noprefix(table_data, aplic_addr, 8);
+ /* APLIC size */
+ build_append_int_noprefix(table_data,
+ s->memmap[VIRT_APLIC_S].size, 4);
+ }
+ }
+
acpi_table_end(linker, &table);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 07/12] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT
2023-10-19 13:26 [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
` (5 preceding siblings ...)
2023-10-19 13:26 ` [PATCH v3 06/12] hw/riscv/virt-acpi-build.c: Add APLIC " Sunil V L
@ 2023-10-19 13:26 ` Sunil V L
2023-10-23 12:51 ` Andrew Jones
` (2 more replies)
2023-10-19 13:26 ` [PATCH v3 08/12] hw/riscv/virt-acpi-build.c: Add MMU node " Sunil V L
` (4 subsequent siblings)
11 siblings, 3 replies; 30+ messages in thread
From: Sunil V L @ 2023-10-19 13:26 UTC (permalink / raw)
To: qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Andrew Jones, Atish Kumar Patra, Haibo Xu, Sunil V L
When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the
block size for those extensions need to be communicated via CMO node in
RHCT. Add CMO node in RHCT if any of those CMO extensions are detected.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
hw/riscv/virt-acpi-build.c | 64 +++++++++++++++++++++++++++++++++-----
1 file changed, 56 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 8fa358d034..bf47eef792 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -147,6 +147,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
* 5.2.36 RISC-V Hart Capabilities Table (RHCT)
* REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16
* https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
+ * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view
*/
static void build_rhct(GArray *table_data,
BIOSLinker *linker,
@@ -156,8 +157,8 @@ static void build_rhct(GArray *table_data,
MachineState *ms = MACHINE(s);
const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
size_t len, aligned_len;
- uint32_t isa_offset, num_rhct_nodes;
- RISCVCPU *cpu;
+ uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
+ RISCVCPU *cpu = &s->soc[0].harts[0];
char *isa;
AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
@@ -173,6 +174,9 @@ static void build_rhct(GArray *table_data,
/* ISA + N hart info */
num_rhct_nodes = 1 + ms->smp.cpus;
+ if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
+ num_rhct_nodes++;
+ }
/* Number of RHCT nodes*/
build_append_int_noprefix(table_data, num_rhct_nodes, 4);
@@ -184,7 +188,6 @@ static void build_rhct(GArray *table_data,
isa_offset = table_data->len - table.table_offset;
build_append_int_noprefix(table_data, 0, 2); /* Type 0 */
- cpu = &s->soc[0].harts[0];
isa = riscv_isa_string(cpu);
len = 8 + strlen(isa) + 1;
aligned_len = (len % 2) ? (len + 1) : len;
@@ -200,14 +203,59 @@ static void build_rhct(GArray *table_data,
build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */
}
+ /* CMO node */
+ if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
+ cmo_offset = table_data->len - table.table_offset;
+ build_append_int_noprefix(table_data, 1, 2); /* Type */
+ build_append_int_noprefix(table_data, 10, 2); /* Total Length */
+ build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+ build_append_int_noprefix(table_data, 0, 1); /* Reserved */
+
+ /* CBOM block size */
+ if (cpu->cfg.cbom_blocksize) {
+ build_append_int_noprefix(table_data,
+ __builtin_ctz(cpu->cfg.cbom_blocksize),
+ 1);
+ } else {
+ build_append_int_noprefix(table_data, 0, 1);
+ }
+
+ /* CBOP block size */
+ build_append_int_noprefix(table_data, 0, 1);
+
+ /* CBOZ block size */
+ if (cpu->cfg.cboz_blocksize) {
+ build_append_int_noprefix(table_data,
+ __builtin_ctz(cpu->cfg.cboz_blocksize),
+ 1);
+ } else {
+ build_append_int_noprefix(table_data, 0, 1);
+ }
+ }
+
/* Hart Info Node */
for (int i = 0; i < arch_ids->len; i++) {
+ len = 16;
+ int num_offsets = 1;
build_append_int_noprefix(table_data, 0xFFFF, 2); /* Type */
- build_append_int_noprefix(table_data, 16, 2); /* Length */
- build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
- build_append_int_noprefix(table_data, 1, 2); /* Number of offsets */
- build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
- build_append_int_noprefix(table_data, isa_offset, 4); /* Offsets[0] */
+
+ /* Length */
+ if (cmo_offset) {
+ len += 4;
+ num_offsets++;
+ }
+
+ build_append_int_noprefix(table_data, len, 2);
+ build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+ /* Number of offsets */
+ build_append_int_noprefix(table_data, num_offsets, 2);
+ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
+
+ /* Offsets */
+ build_append_int_noprefix(table_data, isa_offset, 4);
+ if (cmo_offset) {
+ build_append_int_noprefix(table_data, cmo_offset, 4);
+ }
}
acpi_table_end(linker, &table);
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 08/12] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT
2023-10-19 13:26 [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
` (6 preceding siblings ...)
2023-10-19 13:26 ` [PATCH v3 07/12] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT Sunil V L
@ 2023-10-19 13:26 ` Sunil V L
2023-10-23 13:15 ` Andrew Jones
2023-10-19 13:26 ` [PATCH v3 09/12] hw/pci-host/gpex: Define properties for MMIO ranges Sunil V L
` (3 subsequent siblings)
11 siblings, 1 reply; 30+ messages in thread
From: Sunil V L @ 2023-10-19 13:26 UTC (permalink / raw)
To: qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Andrew Jones, Atish Kumar Patra, Haibo Xu, Sunil V L
MMU type information is available via MMU node in RHCT. Add this node in
RHCT.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
hw/riscv/virt-acpi-build.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index bf47eef792..4895c9669d 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -159,6 +159,8 @@ static void build_rhct(GArray *table_data,
size_t len, aligned_len;
uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
RISCVCPU *cpu = &s->soc[0].harts[0];
+ uint32_t mmu_offset = 0;
+ uint8_t satp_mode_max;
char *isa;
AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
@@ -178,6 +180,10 @@ static void build_rhct(GArray *table_data,
num_rhct_nodes++;
}
+ if (cpu->cfg.satp_mode.supported != 0) {
+ num_rhct_nodes++;
+ }
+
/* Number of RHCT nodes*/
build_append_int_noprefix(table_data, num_rhct_nodes, 4);
@@ -203,6 +209,26 @@ static void build_rhct(GArray *table_data,
build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */
}
+ /* MMU node structure */
+ if (cpu->cfg.satp_mode.supported != 0) {
+ satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
+ mmu_offset = table_data->len - table.table_offset;
+ build_append_int_noprefix(table_data, 2, 2); /* Type */
+ build_append_int_noprefix(table_data, 8, 2); /* Total Length */
+ build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
+ build_append_int_noprefix(table_data, 0, 1); /* Reserved */
+ /* Virtual Address Scheme */
+ if (satp_mode_max == VM_1_10_SV57) {
+ build_append_int_noprefix(table_data, 2, 1); /* Sv57 */
+ } else if (satp_mode_max == VM_1_10_SV48) {
+ build_append_int_noprefix(table_data, 1, 1); /* Sv48 */
+ } else if (satp_mode_max == VM_1_10_SV39) {
+ build_append_int_noprefix(table_data, 0, 1); /* Sv39 */
+ } else {
+ assert(1);
+ }
+ }
+
/* CMO node */
if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
cmo_offset = table_data->len - table.table_offset;
@@ -245,6 +271,11 @@ static void build_rhct(GArray *table_data,
num_offsets++;
}
+ if (mmu_offset) {
+ len += 4;
+ num_offsets++;
+ }
+
build_append_int_noprefix(table_data, len, 2);
build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
/* Number of offsets */
@@ -253,9 +284,14 @@ static void build_rhct(GArray *table_data,
/* Offsets */
build_append_int_noprefix(table_data, isa_offset, 4);
+
if (cmo_offset) {
build_append_int_noprefix(table_data, cmo_offset, 4);
}
+
+ if (mmu_offset) {
+ build_append_int_noprefix(table_data, mmu_offset, 4);
+ }
}
acpi_table_end(linker, &table);
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 09/12] hw/pci-host/gpex: Define properties for MMIO ranges
2023-10-19 13:26 [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
` (7 preceding siblings ...)
2023-10-19 13:26 ` [PATCH v3 08/12] hw/riscv/virt-acpi-build.c: Add MMU node " Sunil V L
@ 2023-10-19 13:26 ` Sunil V L
2023-10-19 13:26 ` [PATCH v3 10/12] hw/riscv/virt: Update GPEX MMIO related properties Sunil V L
` (2 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Sunil V L @ 2023-10-19 13:26 UTC (permalink / raw)
To: qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Andrew Jones, Atish Kumar Patra, Haibo Xu, Sunil V L
ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit
and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of
making these values machine specific, create properties for the GPEX host
bridge with default value 0. During initialization, the firmware can
initialize these properties with correct values for the platform. This
basically allows DSDT generator code independent of the machine specific
memory map accesses.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
hw/pci-host/gpex-acpi.c | 13 +++++++++++++
hw/pci-host/gpex.c | 12 ++++++++++++
include/hw/pci-host/gpex.h | 28 ++++++++++++++++++++--------
3 files changed, 45 insertions(+), 8 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index 1092dc3b70..f69413ea2c 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -281,3 +281,16 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
crs_range_set_free(&crs_range_set);
}
+
+void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq)
+{
+ bool ambig;
+ Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, &ambig);
+
+ if (!obj || ambig) {
+ return;
+ }
+
+ GPEX_HOST(obj)->gpex_cfg.irq = irq;
+ acpi_dsdt_add_gpex(scope, &GPEX_HOST(obj)->gpex_cfg);
+}
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
index a6752fac5e..41f4e73f6e 100644
--- a/hw/pci-host/gpex.c
+++ b/hw/pci-host/gpex.c
@@ -154,6 +154,18 @@ static Property gpex_host_properties[] = {
*/
DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost,
allow_unmapped_accesses, true),
+ DEFINE_PROP_UINT64(PCI_HOST_ECAM_BASE, GPEXHost, gpex_cfg.ecam.base, 0),
+ DEFINE_PROP_SIZE(PCI_HOST_ECAM_SIZE, GPEXHost, gpex_cfg.ecam.size, 0),
+ DEFINE_PROP_UINT64(PCI_HOST_PIO_BASE, GPEXHost, gpex_cfg.pio.base, 0),
+ DEFINE_PROP_SIZE(PCI_HOST_PIO_SIZE, GPEXHost, gpex_cfg.pio.size, 0),
+ DEFINE_PROP_UINT64(PCI_HOST_BELOW_4G_MMIO_BASE, GPEXHost,
+ gpex_cfg.mmio32.base, 0),
+ DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MMIO_SIZE, GPEXHost,
+ gpex_cfg.mmio32.size, 0),
+ DEFINE_PROP_UINT64(PCI_HOST_ABOVE_4G_MMIO_BASE, GPEXHost,
+ gpex_cfg.mmio64.base, 0),
+ DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost,
+ gpex_cfg.mmio64.size, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h
index b0240bd768..441c6b8b20 100644
--- a/include/hw/pci-host/gpex.h
+++ b/include/hw/pci-host/gpex.h
@@ -40,6 +40,15 @@ struct GPEXRootState {
/*< public >*/
};
+struct GPEXConfig {
+ MemMapEntry ecam;
+ MemMapEntry mmio32;
+ MemMapEntry mmio64;
+ MemMapEntry pio;
+ int irq;
+ PCIBus *bus;
+};
+
struct GPEXHost {
/*< private >*/
PCIExpressHost parent_obj;
@@ -55,19 +64,22 @@ struct GPEXHost {
int irq_num[GPEX_NUM_IRQS];
bool allow_unmapped_accesses;
-};
-struct GPEXConfig {
- MemMapEntry ecam;
- MemMapEntry mmio32;
- MemMapEntry mmio64;
- MemMapEntry pio;
- int irq;
- PCIBus *bus;
+ struct GPEXConfig gpex_cfg;
};
int gpex_set_irq_num(GPEXHost *s, int index, int gsi);
void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg);
+void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq);
+
+#define PCI_HOST_PIO_BASE "pio-base"
+#define PCI_HOST_PIO_SIZE "pio-size"
+#define PCI_HOST_ECAM_BASE "ecam-base"
+#define PCI_HOST_ECAM_SIZE "ecam-size"
+#define PCI_HOST_BELOW_4G_MMIO_BASE "below-4g-mmio-base"
+#define PCI_HOST_BELOW_4G_MMIO_SIZE "below-4g-mmio-size"
+#define PCI_HOST_ABOVE_4G_MMIO_BASE "above-4g-mmio-base"
+#define PCI_HOST_ABOVE_4G_MMIO_SIZE "above-4g-mmio-size"
#endif /* HW_GPEX_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 10/12] hw/riscv/virt: Update GPEX MMIO related properties
2023-10-19 13:26 [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
` (8 preceding siblings ...)
2023-10-19 13:26 ` [PATCH v3 09/12] hw/pci-host/gpex: Define properties for MMIO ranges Sunil V L
@ 2023-10-19 13:26 ` Sunil V L
2023-10-20 11:47 ` Daniel Henrique Barboza
2023-10-19 13:26 ` [PATCH v3 11/12] hw/riscv/virt-acpi-build.c: Add IO controllers and devices Sunil V L
2023-10-19 13:26 ` [PATCH v3 12/12] hw/riscv/virt-acpi-build.c: Add PLIC in MADT Sunil V L
11 siblings, 1 reply; 30+ messages in thread
From: Sunil V L @ 2023-10-19 13:26 UTC (permalink / raw)
To: qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Andrew Jones, Atish Kumar Patra, Haibo Xu, Sunil V L
Update the GPEX host bridge properties related to MMIO ranges with values
set for the virt machine.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
hw/riscv/virt.c | 47 ++++++++++++++++++++++++++++-------------
include/hw/riscv/virt.h | 1 +
2 files changed, 33 insertions(+), 15 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 085654ab2f..e64886a4d8 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1049,21 +1049,45 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
}
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
- hwaddr ecam_base, hwaddr ecam_size,
- hwaddr mmio_base, hwaddr mmio_size,
- hwaddr high_mmio_base,
- hwaddr high_mmio_size,
- hwaddr pio_base,
- DeviceState *irqchip)
+ DeviceState *irqchip,
+ RISCVVirtState *s)
{
DeviceState *dev;
MemoryRegion *ecam_alias, *ecam_reg;
MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
+ hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base;
+ hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size;
+ hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base;
+ hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size;
+ hwaddr high_mmio_base = virt_high_pcie_memmap.base;
+ hwaddr high_mmio_size = virt_high_pcie_memmap.size;
+ hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base;
+ hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size;
qemu_irq irq;
int i;
dev = qdev_new(TYPE_GPEX_HOST);
+ /* Set GPEX object properties for the virt machine */
+ object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE,
+ ecam_base, NULL);
+ object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE,
+ ecam_size, NULL);
+ object_property_set_uint(OBJECT(GPEX_HOST(dev)),
+ PCI_HOST_BELOW_4G_MMIO_BASE,
+ mmio_base, NULL);
+ object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE,
+ mmio_size, NULL);
+ object_property_set_uint(OBJECT(GPEX_HOST(dev)),
+ PCI_HOST_ABOVE_4G_MMIO_BASE,
+ high_mmio_base, NULL);
+ object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE,
+ high_mmio_size, NULL);
+ object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE,
+ pio_base, NULL);
+ object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE,
+ pio_size, NULL);
+
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ecam_alias = g_new0(MemoryRegion, 1);
@@ -1094,6 +1118,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
}
+ GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus;
return dev;
}
@@ -1492,15 +1517,7 @@ static void virt_machine_init(MachineState *machine)
qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i));
}
- gpex_pcie_init(system_memory,
- memmap[VIRT_PCIE_ECAM].base,
- memmap[VIRT_PCIE_ECAM].size,
- memmap[VIRT_PCIE_MMIO].base,
- memmap[VIRT_PCIE_MMIO].size,
- virt_high_pcie_memmap.base,
- virt_high_pcie_memmap.size,
- memmap[VIRT_PCIE_PIO].base,
- pcie_irqchip);
+ gpex_pcie_init(system_memory, pcie_irqchip, s);
create_platform_bus(s, mmio_irqchip);
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 5b03575ed3..f89790fd58 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -61,6 +61,7 @@ struct RISCVVirtState {
char *oem_table_id;
OnOffAuto acpi;
const MemMapEntry *memmap;
+ struct GPEXHost *gpex_host;
};
enum {
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 11/12] hw/riscv/virt-acpi-build.c: Add IO controllers and devices
2023-10-19 13:26 [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
` (9 preceding siblings ...)
2023-10-19 13:26 ` [PATCH v3 10/12] hw/riscv/virt: Update GPEX MMIO related properties Sunil V L
@ 2023-10-19 13:26 ` Sunil V L
2023-10-19 13:26 ` [PATCH v3 12/12] hw/riscv/virt-acpi-build.c: Add PLIC in MADT Sunil V L
11 siblings, 0 replies; 30+ messages in thread
From: Sunil V L @ 2023-10-19 13:26 UTC (permalink / raw)
To: qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Andrew Jones, Atish Kumar Patra, Haibo Xu, Sunil V L
Add basic IO controllers and devices like PCI, VirtIO and UART in the ACPI
namespace.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
hw/riscv/Kconfig | 1 +
hw/riscv/virt-acpi-build.c | 76 ++++++++++++++++++++++++++++++++++++--
2 files changed, 73 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index b6a5eb4452..a50717be87 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -45,6 +45,7 @@ config RISCV_VIRT
select FW_CFG_DMA
select PLATFORM_BUS
select ACPI
+ select ACPI_PCI
config SHAKTI_C
bool
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 4895c9669d..2f1cc92f75 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -27,15 +27,18 @@
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/aml-build.h"
+#include "hw/acpi/pci.h"
#include "hw/acpi/utils.h"
+#include "hw/intc/riscv_aclint.h"
#include "hw/nvram/fw_cfg_acpi.h"
+#include "hw/pci-host/gpex.h"
+#include "hw/riscv/virt.h"
+#include "hw/riscv/numa.h"
+#include "hw/virtio/virtio-acpi.h"
+#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/reset.h"
-#include "migration/vmstate.h"
-#include "hw/riscv/virt.h"
-#include "hw/riscv/numa.h"
-#include "hw/intc/riscv_aclint.h"
#define ACPI_BUILD_TABLE_SIZE 0x20000
#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
@@ -139,6 +142,39 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
}
}
+static void
+acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
+ uint32_t uart_irq)
+{
+ Aml *dev = aml_device("COM0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+ Aml *crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(uart_memmap->base,
+ uart_memmap->size, AML_READ_WRITE));
+ aml_append(crs,
+ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, &uart_irq, 1));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+
+ Aml *pkg = aml_package(2);
+ aml_append(pkg, aml_string("clock-frequency"));
+ aml_append(pkg, aml_int(3686400));
+
+ Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301");
+
+ Aml *pkg1 = aml_package(1);
+ aml_append(pkg1, pkg);
+
+ Aml *package = aml_package(2);
+ aml_append(package, UUID);
+ aml_append(package, pkg1);
+
+ aml_append(dev, aml_name_decl("_DSD", package));
+ aml_append(scope, dev);
+}
+
/* RHCT Node[N] starts at offset 56 */
#define RHCT_NODE_ARRAY_OFFSET 56
@@ -319,6 +355,8 @@ static void build_dsdt(GArray *table_data,
RISCVVirtState *s)
{
Aml *scope, *dsdt;
+ MachineState *ms = MACHINE(s);
+ uint8_t socket_count;
const MemMapEntry *memmap = s->memmap;
AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id,
.oem_table_id = s->oem_table_id };
@@ -338,6 +376,26 @@ static void build_dsdt(GArray *table_data,
fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
+ socket_count = riscv_socket_count(ms);
+
+ acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ);
+
+ if (socket_count == 1) {
+ virtio_acpi_dsdt_add(scope, &memmap[VIRT_VIRTIO],
+ VIRTIO_IRQ, VIRTIO_COUNT);
+ acpi_dsdt_add_gpex_host(scope, PCIE_IRQ);
+ } else if (socket_count == 2) {
+ virtio_acpi_dsdt_add(scope, &memmap[VIRT_VIRTIO],
+ VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES,
+ VIRTIO_COUNT);
+ acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES);
+ } else {
+ virtio_acpi_dsdt_add(scope, &memmap[VIRT_VIRTIO],
+ VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES,
+ VIRTIO_COUNT);
+ acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES * 2);
+ }
+
aml_append(dsdt, scope);
/* copy AML table into ACPI tables blob and patch header there */
@@ -487,6 +545,16 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_rhct(tables_blob, tables->linker, s);
+ acpi_add_table(table_offsets, tables_blob);
+ {
+ AcpiMcfgInfo mcfg = {
+ .base = s->memmap[VIRT_PCIE_MMIO].base,
+ .size = s->memmap[VIRT_PCIE_MMIO].size,
+ };
+ build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id,
+ s->oem_table_id);
+ }
+
/* XSDT is pointed to by RSDP */
xsdt = tables_blob->len;
build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v3 12/12] hw/riscv/virt-acpi-build.c: Add PLIC in MADT
2023-10-19 13:26 [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
` (10 preceding siblings ...)
2023-10-19 13:26 ` [PATCH v3 11/12] hw/riscv/virt-acpi-build.c: Add IO controllers and devices Sunil V L
@ 2023-10-19 13:26 ` Sunil V L
2023-10-20 11:49 ` Daniel Henrique Barboza
2023-10-23 13:22 ` Andrew Jones
11 siblings, 2 replies; 30+ messages in thread
From: Sunil V L @ 2023-10-19 13:26 UTC (permalink / raw)
To: qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Andrew Jones, Atish Kumar Patra, Haibo Xu, Sunil V L
Add PLIC structures for each socket in the MADT when system is configured
with PLIC as the external interrupt controller.
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
hw/riscv/virt-acpi-build.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 2f1cc92f75..d1761ddddf 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -85,6 +85,12 @@ static void riscv_acpi_madt_add_rintc(uint32_t uid,
arch_ids->cpus[uid].props.node_id,
local_cpu_id),
4);
+ } else if (aia_type == VIRT_AIA_TYPE_NONE) {
+ build_append_int_noprefix(entry,
+ ACPI_BUILD_INTC_ID(
+ arch_ids->cpus[uid].props.node_id,
+ 2 * local_cpu_id + 1),
+ 4);
} else {
build_append_int_noprefix(entry, 0, 4);
}
@@ -513,6 +519,29 @@ static void build_madt(GArray *table_data,
build_append_int_noprefix(table_data,
s->memmap[VIRT_APLIC_S].size, 4);
}
+ } else {
+ /* PLICs */
+ for (socket = 0; socket < riscv_socket_count(ms); socket++) {
+ aplic_addr = s->memmap[VIRT_PLIC].base +
+ s->memmap[VIRT_PLIC].size * socket;
+ gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
+ build_append_int_noprefix(table_data, 0x1B, 1); /* Type */
+ build_append_int_noprefix(table_data, 36, 1); /* Length */
+ build_append_int_noprefix(table_data, 1, 1); /* Version */
+ build_append_int_noprefix(table_data, socket, 1); /* PLIC ID */
+ build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */
+ /* Total External Interrupt Sources Supported */
+ build_append_int_noprefix(table_data,
+ VIRT_IRQCHIP_NUM_SOURCES - 1, 2);
+ build_append_int_noprefix(table_data, 0, 2); /* Max priority */
+ build_append_int_noprefix(table_data, 0, 4); /* Flags */
+ /* PLIC Size */
+ build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size, 4);
+ /* PLIC Address */
+ build_append_int_noprefix(table_data, aplic_addr, 8);
+ /* Global System Interrupt Vector Base */
+ build_append_int_noprefix(table_data, gsi_base, 4);
+ }
}
acpi_table_end(linker, &table);
--
2.34.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH v3 02/12] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location
2023-10-19 13:26 ` [PATCH v3 02/12] hw/arm/virt-acpi-build.c: Migrate virtio " Sunil V L
@ 2023-10-20 11:42 ` Daniel Henrique Barboza
2023-10-23 12:28 ` Andrew Jones
1 sibling, 0 replies; 30+ messages in thread
From: Daniel Henrique Barboza @ 2023-10-20 11:42 UTC (permalink / raw)
To: Sunil V L, qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Liu Zhiwei, Anup Patel, Andrew Jones,
Atish Kumar Patra, Haibo Xu
Nit: this will give a whitespace error when applying:
Applying: hw/arm/virt-acpi-build.c: Migrate virtio creation to common location
.git/rebase-apply/patch:123: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
Thanks,
Daniel
On 10/19/23 10:26, Sunil V L wrote:
> RISC-V also needs to create the virtio in DSDT in the same way as ARM. So,
> instead of duplicating the code, move this function to the device specific
> file which is common across architectures.
>
> Suggested-by: Igor Mammedov <imammedo@redhat.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/arm/virt-acpi-build.c | 29 ++---------------------------
> hw/virtio/meson.build | 1 +
> hw/virtio/virtio-acpi.c | 28 ++++++++++++++++++++++++++++
> include/hw/virtio/virtio-acpi.h | 11 +++++++++++
> 4 files changed, 42 insertions(+), 27 deletions(-)
> create mode 100644 hw/virtio/virtio-acpi.c
> create mode 100644 include/hw/virtio/virtio-acpi.h
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index b8e725d953..69733f6663 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -58,6 +58,7 @@
> #include "migration/vmstate.h"
> #include "hw/acpi/ghes.h"
> #include "hw/acpi/viot.h"
> +#include "hw/virtio/virtio-acpi.h"
>
> #define ARM_SPI_BASE 32
>
> @@ -118,32 +119,6 @@ static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
> aml_append(scope, dev);
> }
>
> -static void acpi_dsdt_add_virtio(Aml *scope,
> - const MemMapEntry *virtio_mmio_memmap,
> - uint32_t mmio_irq, int num)
> -{
> - hwaddr base = virtio_mmio_memmap->base;
> - hwaddr size = virtio_mmio_memmap->size;
> - int i;
> -
> - for (i = 0; i < num; i++) {
> - uint32_t irq = mmio_irq + i;
> - Aml *dev = aml_device("VR%02u", i);
> - aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
> - aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> - aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> -
> - Aml *crs = aml_resource_template();
> - aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
> - aml_append(crs,
> - aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
> - AML_EXCLUSIVE, &irq, 1));
> - aml_append(dev, aml_name_decl("_CRS", crs));
> - aml_append(scope, dev);
> - base += size;
> - }
> -}
> -
> static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
> uint32_t irq, VirtMachineState *vms)
> {
> @@ -850,7 +825,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
> acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
> }
> fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
> - acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
> + virtio_acpi_dsdt_add(scope, &memmap[VIRT_MMIO],
> (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
> acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
> if (vms->acpi_dev) {
> diff --git a/hw/virtio/meson.build b/hw/virtio/meson.build
> index c0055a7832..9d62097a21 100644
> --- a/hw/virtio/meson.build
> +++ b/hw/virtio/meson.build
> @@ -79,3 +79,4 @@ system_ss.add(when: 'CONFIG_ALL', if_true: files('virtio-stub.c'))
> system_ss.add(files('virtio-hmp-cmds.c'))
>
> specific_ss.add_all(when: 'CONFIG_VIRTIO', if_true: specific_virtio_ss)
> +system_ss.add(when: 'CONFIG_ACPI', if_true: files('virtio-acpi.c'))
> diff --git a/hw/virtio/virtio-acpi.c b/hw/virtio/virtio-acpi.c
> new file mode 100644
> index 0000000000..977499defd
> --- /dev/null
> +++ b/hw/virtio/virtio-acpi.c
> @@ -0,0 +1,28 @@
> +#include "hw/virtio/virtio-acpi.h"
> +#include "hw/acpi/aml-build.h"
> +
> +void virtio_acpi_dsdt_add(Aml *scope,
> + const MemMapEntry *virtio_mmio_memmap,
> + uint32_t mmio_irq, int num)
> +{
> + hwaddr base = virtio_mmio_memmap->base;
> + hwaddr size = virtio_mmio_memmap->size;
> + int i;
> +
> + for (i = 0; i < num; i++) {
> + uint32_t irq = mmio_irq + i;
> + Aml *dev = aml_device("VR%02u", i);
> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
> + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> + aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> +
> + Aml *crs = aml_resource_template();
> + aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
> + aml_append(crs,
> + aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
> + AML_EXCLUSIVE, &irq, 1));
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> + base += size;
> + }
> +}
> diff --git a/include/hw/virtio/virtio-acpi.h b/include/hw/virtio/virtio-acpi.h
> new file mode 100644
> index 0000000000..b8687b1b42
> --- /dev/null
> +++ b/include/hw/virtio/virtio-acpi.h
> @@ -0,0 +1,11 @@
> +#ifndef VIRTIO_ACPI_H
> +#define VIRTIO_ACPI_H
> +
> +#include "qemu/osdep.h"
> +#include "exec/hwaddr.h"
> +
> +void virtio_acpi_dsdt_add(Aml *scope, const MemMapEntry *virtio_mmio_memmap,
> + uint32_t mmio_irq, int num);
> +
> +#endif
> +
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 10/12] hw/riscv/virt: Update GPEX MMIO related properties
2023-10-19 13:26 ` [PATCH v3 10/12] hw/riscv/virt: Update GPEX MMIO related properties Sunil V L
@ 2023-10-20 11:47 ` Daniel Henrique Barboza
0 siblings, 0 replies; 30+ messages in thread
From: Daniel Henrique Barboza @ 2023-10-20 11:47 UTC (permalink / raw)
To: Sunil V L, qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Liu Zhiwei, Anup Patel, Andrew Jones,
Atish Kumar Patra, Haibo Xu
On 10/19/23 10:26, Sunil V L wrote:
> Update the GPEX host bridge properties related to MMIO ranges with values
> set for the virt machine.
>
> Suggested-by: Igor Mammedov <imammedo@redhat.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> hw/riscv/virt.c | 47 ++++++++++++++++++++++++++++-------------
> include/hw/riscv/virt.h | 1 +
> 2 files changed, 33 insertions(+), 15 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 085654ab2f..e64886a4d8 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -1049,21 +1049,45 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
> }
>
> static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
> - hwaddr ecam_base, hwaddr ecam_size,
> - hwaddr mmio_base, hwaddr mmio_size,
> - hwaddr high_mmio_base,
> - hwaddr high_mmio_size,
> - hwaddr pio_base,
> - DeviceState *irqchip)
> + DeviceState *irqchip,
> + RISCVVirtState *s)
> {
> DeviceState *dev;
> MemoryRegion *ecam_alias, *ecam_reg;
> MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
> + hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base;
> + hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size;
> + hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base;
> + hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size;
> + hwaddr high_mmio_base = virt_high_pcie_memmap.base;
> + hwaddr high_mmio_size = virt_high_pcie_memmap.size;
> + hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base;
> + hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size;
> qemu_irq irq;
> int i;
>
> dev = qdev_new(TYPE_GPEX_HOST);
>
> + /* Set GPEX object properties for the virt machine */
> + object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE,
> + ecam_base, NULL);
> + object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE,
> + ecam_size, NULL);
> + object_property_set_uint(OBJECT(GPEX_HOST(dev)),
> + PCI_HOST_BELOW_4G_MMIO_BASE,
> + mmio_base, NULL);
> + object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE,
> + mmio_size, NULL);
> + object_property_set_uint(OBJECT(GPEX_HOST(dev)),
> + PCI_HOST_ABOVE_4G_MMIO_BASE,
> + high_mmio_base, NULL);
> + object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE,
> + high_mmio_size, NULL);
> + object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE,
> + pio_base, NULL);
> + object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE,
> + pio_size, NULL);
> +
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> ecam_alias = g_new0(MemoryRegion, 1);
> @@ -1094,6 +1118,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
> gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
> }
>
> + GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus;
> return dev;
> }
>
> @@ -1492,15 +1517,7 @@ static void virt_machine_init(MachineState *machine)
> qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i));
> }
>
> - gpex_pcie_init(system_memory,
> - memmap[VIRT_PCIE_ECAM].base,
> - memmap[VIRT_PCIE_ECAM].size,
> - memmap[VIRT_PCIE_MMIO].base,
> - memmap[VIRT_PCIE_MMIO].size,
> - virt_high_pcie_memmap.base,
> - virt_high_pcie_memmap.size,
> - memmap[VIRT_PCIE_PIO].base,
> - pcie_irqchip);
> + gpex_pcie_init(system_memory, pcie_irqchip, s);
>
> create_platform_bus(s, mmio_irqchip);
>
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index 5b03575ed3..f89790fd58 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -61,6 +61,7 @@ struct RISCVVirtState {
> char *oem_table_id;
> OnOffAuto acpi;
> const MemMapEntry *memmap;
> + struct GPEXHost *gpex_host;
> };
>
> enum {
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 12/12] hw/riscv/virt-acpi-build.c: Add PLIC in MADT
2023-10-19 13:26 ` [PATCH v3 12/12] hw/riscv/virt-acpi-build.c: Add PLIC in MADT Sunil V L
@ 2023-10-20 11:49 ` Daniel Henrique Barboza
2023-10-23 13:22 ` Andrew Jones
1 sibling, 0 replies; 30+ messages in thread
From: Daniel Henrique Barboza @ 2023-10-20 11:49 UTC (permalink / raw)
To: Sunil V L, qemu-riscv, qemu-arm, qemu-devel
Cc: Shannon Zhao, Peter Maydell, Michael S . Tsirkin, Igor Mammedov,
Ani Sinha, Philippe Mathieu-Daudé, Gerd Hoffmann,
Paolo Bonzini, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Liu Zhiwei, Anup Patel, Andrew Jones,
Atish Kumar Patra, Haibo Xu
On 10/19/23 10:26, Sunil V L wrote:
> Add PLIC structures for each socket in the MADT when system is configured
> with PLIC as the external interrupt controller.
>
> Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> hw/riscv/virt-acpi-build.c | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 2f1cc92f75..d1761ddddf 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -85,6 +85,12 @@ static void riscv_acpi_madt_add_rintc(uint32_t uid,
> arch_ids->cpus[uid].props.node_id,
> local_cpu_id),
> 4);
> + } else if (aia_type == VIRT_AIA_TYPE_NONE) {
> + build_append_int_noprefix(entry,
> + ACPI_BUILD_INTC_ID(
> + arch_ids->cpus[uid].props.node_id,
> + 2 * local_cpu_id + 1),
> + 4);
> } else {
> build_append_int_noprefix(entry, 0, 4);
> }
> @@ -513,6 +519,29 @@ static void build_madt(GArray *table_data,
> build_append_int_noprefix(table_data,
> s->memmap[VIRT_APLIC_S].size, 4);
> }
> + } else {
> + /* PLICs */
> + for (socket = 0; socket < riscv_socket_count(ms); socket++) {
> + aplic_addr = s->memmap[VIRT_PLIC].base +
> + s->memmap[VIRT_PLIC].size * socket;
> + gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
> + build_append_int_noprefix(table_data, 0x1B, 1); /* Type */
> + build_append_int_noprefix(table_data, 36, 1); /* Length */
> + build_append_int_noprefix(table_data, 1, 1); /* Version */
> + build_append_int_noprefix(table_data, socket, 1); /* PLIC ID */
> + build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */
> + /* Total External Interrupt Sources Supported */
> + build_append_int_noprefix(table_data,
> + VIRT_IRQCHIP_NUM_SOURCES - 1, 2);
> + build_append_int_noprefix(table_data, 0, 2); /* Max priority */
> + build_append_int_noprefix(table_data, 0, 4); /* Flags */
> + /* PLIC Size */
> + build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size, 4);
> + /* PLIC Address */
> + build_append_int_noprefix(table_data, aplic_addr, 8);
> + /* Global System Interrupt Vector Base */
> + build_append_int_noprefix(table_data, gsi_base, 4);
> + }
> }
>
> acpi_table_end(linker, &table);
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 01/12] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location
2023-10-19 13:26 ` [PATCH v3 01/12] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location Sunil V L
@ 2023-10-23 12:22 ` Andrew Jones
0 siblings, 0 replies; 30+ messages in thread
From: Andrew Jones @ 2023-10-23 12:22 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-riscv, qemu-arm, qemu-devel, Shannon Zhao, Peter Maydell,
Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Philippe Mathieu-Daudé, Gerd Hoffmann, Paolo Bonzini,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Atish Kumar Patra, Haibo Xu
On Thu, Oct 19, 2023 at 06:56:37PM +0530, Sunil V L wrote:
> RISC-V also needs to use the same code to create fw_cfg in DSDT. So, avoid
> code duplication by moving the code in arm and riscv to a device specific
> file.
>
> Suggested-by: Igor Mammedov <imammedo@redhat.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/arm/virt-acpi-build.c | 19 ++-----------------
> hw/nvram/fw_cfg-acpi.c | 17 +++++++++++++++++
> hw/nvram/meson.build | 1 +
> hw/riscv/virt-acpi-build.c | 19 ++-----------------
> include/hw/nvram/fw_cfg_acpi.h | 9 +++++++++
> 5 files changed, 31 insertions(+), 34 deletions(-)
> create mode 100644 hw/nvram/fw_cfg-acpi.c
> create mode 100644 include/hw/nvram/fw_cfg_acpi.h
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 6b674231c2..b8e725d953 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -35,7 +35,7 @@
> #include "target/arm/cpu.h"
> #include "hw/acpi/acpi-defs.h"
> #include "hw/acpi/acpi.h"
> -#include "hw/nvram/fw_cfg.h"
> +#include "hw/nvram/fw_cfg_acpi.h"
> #include "hw/acpi/bios-linker-loader.h"
> #include "hw/acpi/aml-build.h"
> #include "hw/acpi/utils.h"
> @@ -94,21 +94,6 @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
> aml_append(scope, dev);
> }
>
> -static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
> -{
> - Aml *dev = aml_device("FWCF");
> - aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
> - /* device present, functioning, decoding, not shown in UI */
> - aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
> - aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> -
> - Aml *crs = aml_resource_template();
> - aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
> - fw_cfg_memmap->size, AML_READ_WRITE));
> - aml_append(dev, aml_name_decl("_CRS", crs));
> - aml_append(scope, dev);
> -}
> -
> static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
> {
> Aml *dev, *crs;
> @@ -864,7 +849,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
> if (vmc->acpi_expose_flash) {
> acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
> }
> - acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
> + fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
> acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
> (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
> acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
> diff --git a/hw/nvram/fw_cfg-acpi.c b/hw/nvram/fw_cfg-acpi.c
> new file mode 100644
> index 0000000000..4eeb81bc36
> --- /dev/null
> +++ b/hw/nvram/fw_cfg-acpi.c
> @@ -0,0 +1,17 @@
Should add an SPDX.
> +#include "hw/nvram/fw_cfg_acpi.h"
> +#include "hw/acpi/aml-build.h"
> +
> +void fw_cfg_acpi_dsdt_add(Aml *scope, const MemMapEntry *fw_cfg_memmap)
> +{
> + Aml *dev = aml_device("FWCF");
> + aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
> + /* device present, functioning, decoding, not shown in UI */
> + aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
> + aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> +
> + Aml *crs = aml_resource_template();
> + aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
> + fw_cfg_memmap->size, AML_READ_WRITE));
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> +}
> diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
> index 75e415b1a0..4996c72456 100644
> --- a/hw/nvram/meson.build
> +++ b/hw/nvram/meson.build
> @@ -17,3 +17,4 @@ system_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files(
> system_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
>
> specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
> +specific_ss.add(when: 'CONFIG_ACPI', if_true: files('fw_cfg-acpi.c'))
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 7331248f59..d8772c2821 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -28,6 +28,7 @@
> #include "hw/acpi/acpi.h"
> #include "hw/acpi/aml-build.h"
> #include "hw/acpi/utils.h"
> +#include "hw/nvram/fw_cfg_acpi.h"
> #include "qapi/error.h"
> #include "qemu/error-report.h"
> #include "sysemu/reset.h"
> @@ -97,22 +98,6 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
> }
> }
>
> -static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
> -{
> - Aml *dev = aml_device("FWCF");
> - aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
> -
> - /* device present, functioning, decoding, not shown in UI */
> - aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
> - aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> -
> - Aml *crs = aml_resource_template();
> - aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
> - fw_cfg_memmap->size, AML_READ_WRITE));
> - aml_append(dev, aml_name_decl("_CRS", crs));
> - aml_append(scope, dev);
> -}
> -
> /* RHCT Node[N] starts at offset 56 */
> #define RHCT_NODE_ARRAY_OFFSET 56
>
> @@ -226,7 +211,7 @@ static void build_dsdt(GArray *table_data,
> scope = aml_scope("\\_SB");
> acpi_dsdt_add_cpus(scope, s);
>
> - acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
> + fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
>
> aml_append(dsdt, scope);
>
> diff --git a/include/hw/nvram/fw_cfg_acpi.h b/include/hw/nvram/fw_cfg_acpi.h
> new file mode 100644
> index 0000000000..6e2c5f04b7
> --- /dev/null
> +++ b/include/hw/nvram/fw_cfg_acpi.h
> @@ -0,0 +1,9 @@
And an SPDX here too.
> +#ifndef FW_CFG_ACPI_H
> +#define FW_CFG_ACPI_H
> +
> +#include "qemu/osdep.h"
> +#include "exec/hwaddr.h"
> +
> +void fw_cfg_acpi_dsdt_add(Aml *scope, const MemMapEntry *fw_cfg_memmap);
> +
> +#endif
> --
> 2.34.1
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 02/12] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location
2023-10-19 13:26 ` [PATCH v3 02/12] hw/arm/virt-acpi-build.c: Migrate virtio " Sunil V L
2023-10-20 11:42 ` Daniel Henrique Barboza
@ 2023-10-23 12:28 ` Andrew Jones
2023-10-25 20:03 ` Sunil V L
1 sibling, 1 reply; 30+ messages in thread
From: Andrew Jones @ 2023-10-23 12:28 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-riscv, qemu-arm, qemu-devel, Shannon Zhao, Peter Maydell,
Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Philippe Mathieu-Daudé, Gerd Hoffmann, Paolo Bonzini,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Atish Kumar Patra, Haibo Xu
On Thu, Oct 19, 2023 at 06:56:38PM +0530, Sunil V L wrote:
> RISC-V also needs to create the virtio in DSDT in the same way as ARM. So,
> instead of duplicating the code, move this function to the device specific
> file which is common across architectures.
>
> Suggested-by: Igor Mammedov <imammedo@redhat.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/arm/virt-acpi-build.c | 29 ++---------------------------
> hw/virtio/meson.build | 1 +
> hw/virtio/virtio-acpi.c | 28 ++++++++++++++++++++++++++++
> include/hw/virtio/virtio-acpi.h | 11 +++++++++++
Need SPDX for these new files as well.
> 4 files changed, 42 insertions(+), 27 deletions(-)
> create mode 100644 hw/virtio/virtio-acpi.c
> create mode 100644 include/hw/virtio/virtio-acpi.h
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index b8e725d953..69733f6663 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -58,6 +58,7 @@
> #include "migration/vmstate.h"
> #include "hw/acpi/ghes.h"
> #include "hw/acpi/viot.h"
> +#include "hw/virtio/virtio-acpi.h"
>
> #define ARM_SPI_BASE 32
>
> @@ -118,32 +119,6 @@ static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
> aml_append(scope, dev);
> }
>
> -static void acpi_dsdt_add_virtio(Aml *scope,
> - const MemMapEntry *virtio_mmio_memmap,
> - uint32_t mmio_irq, int num)
> -{
> - hwaddr base = virtio_mmio_memmap->base;
> - hwaddr size = virtio_mmio_memmap->size;
> - int i;
> -
> - for (i = 0; i < num; i++) {
> - uint32_t irq = mmio_irq + i;
> - Aml *dev = aml_device("VR%02u", i);
> - aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
> - aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> - aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> -
> - Aml *crs = aml_resource_template();
> - aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
> - aml_append(crs,
> - aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
> - AML_EXCLUSIVE, &irq, 1));
> - aml_append(dev, aml_name_decl("_CRS", crs));
> - aml_append(scope, dev);
> - base += size;
> - }
> -}
> -
> static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
> uint32_t irq, VirtMachineState *vms)
> {
> @@ -850,7 +825,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
> acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
> }
> fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
> - acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
> + virtio_acpi_dsdt_add(scope, &memmap[VIRT_MMIO],
> (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
> acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
> if (vms->acpi_dev) {
> diff --git a/hw/virtio/meson.build b/hw/virtio/meson.build
> index c0055a7832..9d62097a21 100644
> --- a/hw/virtio/meson.build
> +++ b/hw/virtio/meson.build
> @@ -79,3 +79,4 @@ system_ss.add(when: 'CONFIG_ALL', if_true: files('virtio-stub.c'))
> system_ss.add(files('virtio-hmp-cmds.c'))
>
> specific_ss.add_all(when: 'CONFIG_VIRTIO', if_true: specific_virtio_ss)
> +system_ss.add(when: 'CONFIG_ACPI', if_true: files('virtio-acpi.c'))
> diff --git a/hw/virtio/virtio-acpi.c b/hw/virtio/virtio-acpi.c
> new file mode 100644
> index 0000000000..977499defd
> --- /dev/null
> +++ b/hw/virtio/virtio-acpi.c
> @@ -0,0 +1,28 @@
> +#include "hw/virtio/virtio-acpi.h"
> +#include "hw/acpi/aml-build.h"
> +
> +void virtio_acpi_dsdt_add(Aml *scope,
> + const MemMapEntry *virtio_mmio_memmap,
> + uint32_t mmio_irq, int num)
> +{
> + hwaddr base = virtio_mmio_memmap->base;
> + hwaddr size = virtio_mmio_memmap->size;
> + int i;
> +
> + for (i = 0; i < num; i++) {
> + uint32_t irq = mmio_irq + i;
> + Aml *dev = aml_device("VR%02u", i);
> + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
> + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> + aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> +
> + Aml *crs = aml_resource_template();
> + aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
> + aml_append(crs,
> + aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
> + AML_EXCLUSIVE, &irq, 1));
> + aml_append(dev, aml_name_decl("_CRS", crs));
> + aml_append(scope, dev);
> + base += size;
> + }
> +}
> diff --git a/include/hw/virtio/virtio-acpi.h b/include/hw/virtio/virtio-acpi.h
> new file mode 100644
> index 0000000000..b8687b1b42
> --- /dev/null
> +++ b/include/hw/virtio/virtio-acpi.h
> @@ -0,0 +1,11 @@
> +#ifndef VIRTIO_ACPI_H
> +#define VIRTIO_ACPI_H
> +
> +#include "qemu/osdep.h"
> +#include "exec/hwaddr.h"
> +
> +void virtio_acpi_dsdt_add(Aml *scope, const MemMapEntry *virtio_mmio_memmap,
> + uint32_t mmio_irq, int num);
> +
> +#endif
> +
> --
> 2.34.1
>
Shouldn't we also try to apply this to microvm which has nearly the same
code?
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 03/12] hw/riscv: virt: Make few IMSIC macros and functions public
2023-10-19 13:26 ` [PATCH v3 03/12] hw/riscv: virt: Make few IMSIC macros and functions public Sunil V L
@ 2023-10-23 12:31 ` Andrew Jones
0 siblings, 0 replies; 30+ messages in thread
From: Andrew Jones @ 2023-10-23 12:31 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-riscv, qemu-arm, qemu-devel, Shannon Zhao, Peter Maydell,
Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Philippe Mathieu-Daudé, Gerd Hoffmann, Paolo Bonzini,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Atish Kumar Patra, Haibo Xu
On Thu, Oct 19, 2023 at 06:56:39PM +0530, Sunil V L wrote:
> Some macros and static function related to IMSIC are defined in virt.c.
> They are required in virt-acpi-build.c. So, make them public.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/virt.c | 25 +------------------------
> include/hw/riscv/virt.h | 25 +++++++++++++++++++++++++
> 2 files changed, 26 insertions(+), 24 deletions(-)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 05/12] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT
2023-10-19 13:26 ` [PATCH v3 05/12] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT Sunil V L
@ 2023-10-23 12:42 ` Andrew Jones
2023-10-24 0:10 ` Alistair Francis
1 sibling, 0 replies; 30+ messages in thread
From: Andrew Jones @ 2023-10-23 12:42 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-riscv, qemu-arm, qemu-devel, Shannon Zhao, Peter Maydell,
Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Philippe Mathieu-Daudé, Gerd Hoffmann, Paolo Bonzini,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Atish Kumar Patra, Haibo Xu
On Thu, Oct 19, 2023 at 06:56:41PM +0530, Sunil V L wrote:
> Add IMSIC structure in MADT when IMSIC is configured.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> hw/riscv/virt-acpi-build.c | 34 ++++++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 06/12] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT
2023-10-19 13:26 ` [PATCH v3 06/12] hw/riscv/virt-acpi-build.c: Add APLIC " Sunil V L
@ 2023-10-23 12:46 ` Andrew Jones
2023-10-24 0:10 ` Alistair Francis
1 sibling, 0 replies; 30+ messages in thread
From: Andrew Jones @ 2023-10-23 12:46 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-riscv, qemu-arm, qemu-devel, Shannon Zhao, Peter Maydell,
Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Philippe Mathieu-Daudé, Gerd Hoffmann, Paolo Bonzini,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Atish Kumar Patra, Haibo Xu
On Thu, Oct 19, 2023 at 06:56:42PM +0530, Sunil V L wrote:
> Add APLIC structures for each socket in the MADT when system is configured
> with APLIC as the external wired interrupt controller.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> hw/riscv/virt-acpi-build.c | 36 ++++++++++++++++++++++++++++++++++--
> 1 file changed, 34 insertions(+), 2 deletions(-)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 07/12] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT
2023-10-19 13:26 ` [PATCH v3 07/12] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT Sunil V L
@ 2023-10-23 12:51 ` Andrew Jones
2023-10-23 13:17 ` Andrew Jones
2023-10-24 0:12 ` Alistair Francis
2 siblings, 0 replies; 30+ messages in thread
From: Andrew Jones @ 2023-10-23 12:51 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-riscv, qemu-arm, qemu-devel, Shannon Zhao, Peter Maydell,
Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Philippe Mathieu-Daudé, Gerd Hoffmann, Paolo Bonzini,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Atish Kumar Patra, Haibo Xu
On Thu, Oct 19, 2023 at 06:56:43PM +0530, Sunil V L wrote:
> When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the
> block size for those extensions need to be communicated via CMO node in
> RHCT. Add CMO node in RHCT if any of those CMO extensions are detected.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> hw/riscv/virt-acpi-build.c | 64 +++++++++++++++++++++++++++++++++-----
> 1 file changed, 56 insertions(+), 8 deletions(-)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 08/12] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT
2023-10-19 13:26 ` [PATCH v3 08/12] hw/riscv/virt-acpi-build.c: Add MMU node " Sunil V L
@ 2023-10-23 13:15 ` Andrew Jones
0 siblings, 0 replies; 30+ messages in thread
From: Andrew Jones @ 2023-10-23 13:15 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-riscv, qemu-arm, qemu-devel, Shannon Zhao, Peter Maydell,
Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Philippe Mathieu-Daudé, Gerd Hoffmann, Paolo Bonzini,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Atish Kumar Patra, Haibo Xu
On Thu, Oct 19, 2023 at 06:56:44PM +0530, Sunil V L wrote:
> MMU type information is available via MMU node in RHCT. Add this node in
> RHCT.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> hw/riscv/virt-acpi-build.c | 36 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index bf47eef792..4895c9669d 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -159,6 +159,8 @@ static void build_rhct(GArray *table_data,
> size_t len, aligned_len;
> uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
> RISCVCPU *cpu = &s->soc[0].harts[0];
> + uint32_t mmu_offset = 0;
> + uint8_t satp_mode_max;
> char *isa;
>
> AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
> @@ -178,6 +180,10 @@ static void build_rhct(GArray *table_data,
> num_rhct_nodes++;
> }
>
> + if (cpu->cfg.satp_mode.supported != 0) {
> + num_rhct_nodes++;
> + }
> +
> /* Number of RHCT nodes*/
> build_append_int_noprefix(table_data, num_rhct_nodes, 4);
>
> @@ -203,6 +209,26 @@ static void build_rhct(GArray *table_data,
> build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */
> }
>
> + /* MMU node structure */
> + if (cpu->cfg.satp_mode.supported != 0) {
> + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
> + mmu_offset = table_data->len - table.table_offset;
> + build_append_int_noprefix(table_data, 2, 2); /* Type */
> + build_append_int_noprefix(table_data, 8, 2); /* Total Length */
The comment for the above line should be "Length"
> + build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
> + build_append_int_noprefix(table_data, 0, 1); /* Reserved */
> + /* Virtual Address Scheme */
The above comment should be "MMU Type"
> + if (satp_mode_max == VM_1_10_SV57) {
> + build_append_int_noprefix(table_data, 2, 1); /* Sv57 */
> + } else if (satp_mode_max == VM_1_10_SV48) {
> + build_append_int_noprefix(table_data, 1, 1); /* Sv48 */
> + } else if (satp_mode_max == VM_1_10_SV39) {
> + build_append_int_noprefix(table_data, 0, 1); /* Sv39 */
> + } else {
> + assert(1);
> + }
> + }
> +
> /* CMO node */
> if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
> cmo_offset = table_data->len - table.table_offset;
> @@ -245,6 +271,11 @@ static void build_rhct(GArray *table_data,
> num_offsets++;
> }
>
> + if (mmu_offset) {
> + len += 4;
> + num_offsets++;
> + }
> +
> build_append_int_noprefix(table_data, len, 2);
> build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
> /* Number of offsets */
> @@ -253,9 +284,14 @@ static void build_rhct(GArray *table_data,
>
> /* Offsets */
> build_append_int_noprefix(table_data, isa_offset, 4);
> +
> if (cmo_offset) {
> build_append_int_noprefix(table_data, cmo_offset, 4);
> }
> +
> + if (mmu_offset) {
> + build_append_int_noprefix(table_data, mmu_offset, 4);
> + }
I'd put the mmu_offset above the cmo_offset so the offsets are in
ascending order.
> }
>
> acpi_table_end(linker, &table);
> --
> 2.34.1
>
Thanks,
drew
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 07/12] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT
2023-10-19 13:26 ` [PATCH v3 07/12] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT Sunil V L
2023-10-23 12:51 ` Andrew Jones
@ 2023-10-23 13:17 ` Andrew Jones
2023-10-24 0:12 ` Alistair Francis
2 siblings, 0 replies; 30+ messages in thread
From: Andrew Jones @ 2023-10-23 13:17 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-riscv, qemu-arm, qemu-devel, Shannon Zhao, Peter Maydell,
Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Philippe Mathieu-Daudé, Gerd Hoffmann, Paolo Bonzini,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Atish Kumar Patra, Haibo Xu
On Thu, Oct 19, 2023 at 06:56:43PM +0530, Sunil V L wrote:
> When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the
> block size for those extensions need to be communicated via CMO node in
> RHCT. Add CMO node in RHCT if any of those CMO extensions are detected.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> hw/riscv/virt-acpi-build.c | 64 +++++++++++++++++++++++++++++++++-----
> 1 file changed, 56 insertions(+), 8 deletions(-)
>
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 8fa358d034..bf47eef792 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -147,6 +147,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
> * 5.2.36 RISC-V Hart Capabilities Table (RHCT)
> * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16
> * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
> + * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view
> */
> static void build_rhct(GArray *table_data,
> BIOSLinker *linker,
> @@ -156,8 +157,8 @@ static void build_rhct(GArray *table_data,
> MachineState *ms = MACHINE(s);
> const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
> size_t len, aligned_len;
> - uint32_t isa_offset, num_rhct_nodes;
> - RISCVCPU *cpu;
> + uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
> + RISCVCPU *cpu = &s->soc[0].harts[0];
> char *isa;
>
> AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
> @@ -173,6 +174,9 @@ static void build_rhct(GArray *table_data,
>
> /* ISA + N hart info */
> num_rhct_nodes = 1 + ms->smp.cpus;
> + if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
> + num_rhct_nodes++;
> + }
>
> /* Number of RHCT nodes*/
> build_append_int_noprefix(table_data, num_rhct_nodes, 4);
> @@ -184,7 +188,6 @@ static void build_rhct(GArray *table_data,
> isa_offset = table_data->len - table.table_offset;
> build_append_int_noprefix(table_data, 0, 2); /* Type 0 */
>
> - cpu = &s->soc[0].harts[0];
> isa = riscv_isa_string(cpu);
> len = 8 + strlen(isa) + 1;
> aligned_len = (len % 2) ? (len + 1) : len;
> @@ -200,14 +203,59 @@ static void build_rhct(GArray *table_data,
> build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */
> }
>
> + /* CMO node */
> + if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
> + cmo_offset = table_data->len - table.table_offset;
> + build_append_int_noprefix(table_data, 1, 2); /* Type */
> + build_append_int_noprefix(table_data, 10, 2); /* Total Length */
Comment should be "Length"
> + build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
> + build_append_int_noprefix(table_data, 0, 1); /* Reserved */
> +
> + /* CBOM block size */
> + if (cpu->cfg.cbom_blocksize) {
> + build_append_int_noprefix(table_data,
> + __builtin_ctz(cpu->cfg.cbom_blocksize),
> + 1);
> + } else {
> + build_append_int_noprefix(table_data, 0, 1);
> + }
> +
> + /* CBOP block size */
> + build_append_int_noprefix(table_data, 0, 1);
> +
> + /* CBOZ block size */
> + if (cpu->cfg.cboz_blocksize) {
> + build_append_int_noprefix(table_data,
> + __builtin_ctz(cpu->cfg.cboz_blocksize),
> + 1);
> + } else {
> + build_append_int_noprefix(table_data, 0, 1);
> + }
> + }
> +
> /* Hart Info Node */
> for (int i = 0; i < arch_ids->len; i++) {
> + len = 16;
> + int num_offsets = 1;
> build_append_int_noprefix(table_data, 0xFFFF, 2); /* Type */
> - build_append_int_noprefix(table_data, 16, 2); /* Length */
> - build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
> - build_append_int_noprefix(table_data, 1, 2); /* Number of offsets */
> - build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
> - build_append_int_noprefix(table_data, isa_offset, 4); /* Offsets[0] */
> +
> + /* Length */
> + if (cmo_offset) {
> + len += 4;
> + num_offsets++;
> + }
> +
> + build_append_int_noprefix(table_data, len, 2);
Missing "Length" comment
> + build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
> + /* Number of offsets */
> + build_append_int_noprefix(table_data, num_offsets, 2);
> + build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
> +
> + /* Offsets */
> + build_append_int_noprefix(table_data, isa_offset, 4);
> + if (cmo_offset) {
> + build_append_int_noprefix(table_data, cmo_offset, 4);
> + }
> }
>
> acpi_table_end(linker, &table);
> --
> 2.34.1
>
Thanks,
drew
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 12/12] hw/riscv/virt-acpi-build.c: Add PLIC in MADT
2023-10-19 13:26 ` [PATCH v3 12/12] hw/riscv/virt-acpi-build.c: Add PLIC in MADT Sunil V L
2023-10-20 11:49 ` Daniel Henrique Barboza
@ 2023-10-23 13:22 ` Andrew Jones
1 sibling, 0 replies; 30+ messages in thread
From: Andrew Jones @ 2023-10-23 13:22 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-riscv, qemu-arm, qemu-devel, Shannon Zhao, Peter Maydell,
Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Philippe Mathieu-Daudé, Gerd Hoffmann, Paolo Bonzini,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Atish Kumar Patra, Haibo Xu
On Thu, Oct 19, 2023 at 06:56:48PM +0530, Sunil V L wrote:
> Add PLIC structures for each socket in the MADT when system is configured
> with PLIC as the external interrupt controller.
>
> Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
> hw/riscv/virt-acpi-build.c | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 2f1cc92f75..d1761ddddf 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -85,6 +85,12 @@ static void riscv_acpi_madt_add_rintc(uint32_t uid,
> arch_ids->cpus[uid].props.node_id,
> local_cpu_id),
> 4);
> + } else if (aia_type == VIRT_AIA_TYPE_NONE) {
> + build_append_int_noprefix(entry,
> + ACPI_BUILD_INTC_ID(
> + arch_ids->cpus[uid].props.node_id,
> + 2 * local_cpu_id + 1),
> + 4);
> } else {
> build_append_int_noprefix(entry, 0, 4);
> }
> @@ -513,6 +519,29 @@ static void build_madt(GArray *table_data,
> build_append_int_noprefix(table_data,
> s->memmap[VIRT_APLIC_S].size, 4);
> }
> + } else {
> + /* PLICs */
> + for (socket = 0; socket < riscv_socket_count(ms); socket++) {
> + aplic_addr = s->memmap[VIRT_PLIC].base +
> + s->memmap[VIRT_PLIC].size * socket;
> + gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
> + build_append_int_noprefix(table_data, 0x1B, 1); /* Type */
> + build_append_int_noprefix(table_data, 36, 1); /* Length */
> + build_append_int_noprefix(table_data, 1, 1); /* Version */
> + build_append_int_noprefix(table_data, socket, 1); /* PLIC ID */
> + build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */
> + /* Total External Interrupt Sources Supported */
> + build_append_int_noprefix(table_data,
> + VIRT_IRQCHIP_NUM_SOURCES - 1, 2);
> + build_append_int_noprefix(table_data, 0, 2); /* Max priority */
"Max Priority"
> + build_append_int_noprefix(table_data, 0, 4); /* Flags */
> + /* PLIC Size */
> + build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size, 4);
> + /* PLIC Address */
> + build_append_int_noprefix(table_data, aplic_addr, 8);
> + /* Global System Interrupt Vector Base */
> + build_append_int_noprefix(table_data, gsi_base, 4);
> + }
> }
>
> acpi_table_end(linker, &table);
> --
> 2.34.1
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 04/12] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC
2023-10-19 13:26 ` [PATCH v3 04/12] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC Sunil V L
@ 2023-10-24 0:07 ` Alistair Francis
0 siblings, 0 replies; 30+ messages in thread
From: Alistair Francis @ 2023-10-24 0:07 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-riscv, qemu-arm, qemu-devel, Shannon Zhao, Peter Maydell,
Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Philippe Mathieu-Daudé, Gerd Hoffmann, Paolo Bonzini,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anup Patel, Andrew Jones,
Atish Kumar Patra, Haibo Xu
On Thu, Oct 19, 2023 at 11:28 PM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> Update the RINTC structure in MADT with AIA related fields.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/virt-acpi-build.c | 66 +++++++++++++++++++++++++++++++++++---
> 1 file changed, 62 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index d8772c2821..073c85f327 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -38,6 +38,7 @@
> #include "hw/intc/riscv_aclint.h"
>
> #define ACPI_BUILD_TABLE_SIZE 0x20000
> +#define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index))
>
> typedef struct AcpiBuildState {
> /* Copy of table in RAM (for patching) */
> @@ -58,18 +59,42 @@ static void acpi_align_size(GArray *blob, unsigned align)
> }
>
> static void riscv_acpi_madt_add_rintc(uint32_t uid,
> + uint32_t local_cpu_id,
> const CPUArchIdList *arch_ids,
> - GArray *entry)
> + GArray *entry,
> + RISCVVirtAIAType aia_type,
> + uint64_t imsic_addr,
> + uint32_t imsic_size)
> {
> uint64_t hart_id = arch_ids->cpus[uid].arch_id;
>
> build_append_int_noprefix(entry, 0x18, 1); /* Type */
> - build_append_int_noprefix(entry, 20, 1); /* Length */
> + build_append_int_noprefix(entry, 36, 1); /* Length */
> build_append_int_noprefix(entry, 1, 1); /* Version */
> build_append_int_noprefix(entry, 0, 1); /* Reserved */
> build_append_int_noprefix(entry, 0x1, 4); /* Flags */
> build_append_int_noprefix(entry, hart_id, 8); /* Hart ID */
> build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */
> + /* External Interrupt Controller ID */
> + if (aia_type == VIRT_AIA_TYPE_APLIC) {
> + build_append_int_noprefix(entry,
> + ACPI_BUILD_INTC_ID(
> + arch_ids->cpus[uid].props.node_id,
> + local_cpu_id),
> + 4);
> + } else {
> + build_append_int_noprefix(entry, 0, 4);
> + }
> +
> + if (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
> + /* IMSIC Base address */
> + build_append_int_noprefix(entry, imsic_addr, 8);
> + /* IMSIC Size */
> + build_append_int_noprefix(entry, imsic_size, 4);
> + } else {
> + build_append_int_noprefix(entry, 0, 8);
> + build_append_int_noprefix(entry, 0, 4);
> + }
> }
>
> static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
> @@ -77,6 +102,11 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
> MachineClass *mc = MACHINE_GET_CLASS(s);
> MachineState *ms = MACHINE(s);
> const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
> + uint64_t imsic_socket_addr, imsic_addr;
> + uint8_t guest_index_bits;
> + uint32_t imsic_size, local_cpu_id, socket_id;
> +
> + guest_index_bits = imsic_num_bits(s->aia_guests + 1);
>
> for (int i = 0; i < arch_ids->len; i++) {
> Aml *dev;
> @@ -87,8 +117,19 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
> aml_append(dev, aml_name_decl("_UID",
> aml_int(arch_ids->cpus[i].arch_id)));
>
> + socket_id = arch_ids->cpus[i].props.node_id;
> + local_cpu_id = (arch_ids->cpus[i].arch_id -
> + riscv_socket_first_hartid(ms, socket_id)) %
> + riscv_socket_hart_count(ms, socket_id);
> /* build _MAT object */
> - riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf);
> + imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base +
> + (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE);
> + imsic_addr = imsic_socket_addr +
> + local_cpu_id * IMSIC_HART_SIZE(guest_index_bits);
> + imsic_size = IMSIC_HART_SIZE(guest_index_bits);
> +
> + riscv_acpi_madt_add_rintc(i, local_cpu_id, arch_ids, madt_buf,
> + s->aia_type, imsic_addr, imsic_size);
> aml_append(dev, aml_name_decl("_MAT",
> aml_buffer(madt_buf->len,
> (uint8_t *)madt_buf->data)));
> @@ -227,6 +268,7 @@ static void build_dsdt(GArray *table_data,
> * 5.2.12 Multiple APIC Description Table (MADT)
> * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15
> * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view
> + * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view
> */
> static void build_madt(GArray *table_data,
> BIOSLinker *linker,
> @@ -235,6 +277,12 @@ static void build_madt(GArray *table_data,
> MachineClass *mc = MACHINE_GET_CLASS(s);
> MachineState *ms = MACHINE(s);
> const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
> + uint64_t imsic_socket_addr, imsic_addr;
> + uint8_t guest_index_bits;
> + uint32_t imsic_size;
> + uint32_t local_cpu_id, socket_id;
> +
> + guest_index_bits = imsic_num_bits(s->aia_guests + 1);
>
> AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id,
> .oem_table_id = s->oem_table_id };
> @@ -246,7 +294,17 @@ static void build_madt(GArray *table_data,
>
> /* RISC-V Local INTC structures per HART */
> for (int i = 0; i < arch_ids->len; i++) {
> - riscv_acpi_madt_add_rintc(i, arch_ids, table_data);
> + socket_id = arch_ids->cpus[i].props.node_id;
> + local_cpu_id = (arch_ids->cpus[i].arch_id -
> + riscv_socket_first_hartid(ms, socket_id)) %
> + riscv_socket_hart_count(ms, socket_id);
> + imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base +
> + (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE);
> + imsic_addr = imsic_socket_addr +
> + local_cpu_id * IMSIC_HART_SIZE(guest_index_bits);
> + imsic_size = IMSIC_HART_SIZE(guest_index_bits);
> + riscv_acpi_madt_add_rintc(i, local_cpu_id, arch_ids, table_data,
> + s->aia_type, imsic_addr, imsic_size);
> }
>
> acpi_table_end(linker, &table);
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 05/12] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT
2023-10-19 13:26 ` [PATCH v3 05/12] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT Sunil V L
2023-10-23 12:42 ` Andrew Jones
@ 2023-10-24 0:10 ` Alistair Francis
1 sibling, 0 replies; 30+ messages in thread
From: Alistair Francis @ 2023-10-24 0:10 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-riscv, qemu-arm, qemu-devel, Shannon Zhao, Peter Maydell,
Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Philippe Mathieu-Daudé, Gerd Hoffmann, Paolo Bonzini,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anup Patel, Andrew Jones,
Atish Kumar Patra, Haibo Xu
On Thu, Oct 19, 2023 at 11:28 PM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> Add IMSIC structure in MADT when IMSIC is configured.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/virt-acpi-build.c | 34 ++++++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 073c85f327..7f1a370e54 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -281,8 +281,20 @@ static void build_madt(GArray *table_data,
> uint8_t guest_index_bits;
> uint32_t imsic_size;
> uint32_t local_cpu_id, socket_id;
> + uint8_t hart_index_bits, group_index_bits, group_index_shift;
> + uint16_t imsic_max_hart_per_socket = 0;
> + uint8_t socket;
> +
> + for (socket = 0; socket < riscv_socket_count(ms); socket++) {
> + if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
> + imsic_max_hart_per_socket = s->soc[socket].num_harts;
> + }
> + }
>
> guest_index_bits = imsic_num_bits(s->aia_guests + 1);
> + hart_index_bits = imsic_num_bits(imsic_max_hart_per_socket);
> + group_index_bits = imsic_num_bits(riscv_socket_count(ms));
> + group_index_shift = IMSIC_MMIO_GROUP_MIN_SHIFT;
>
> AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id,
> .oem_table_id = s->oem_table_id };
> @@ -307,6 +319,28 @@ static void build_madt(GArray *table_data,
> s->aia_type, imsic_addr, imsic_size);
> }
>
> + /* IMSIC */
> + if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
> + /* IMSIC */
> + build_append_int_noprefix(table_data, 0x19, 1); /* Type */
> + build_append_int_noprefix(table_data, 16, 1); /* Length */
> + build_append_int_noprefix(table_data, 1, 1); /* Version */
> + build_append_int_noprefix(table_data, 0, 1); /* Reserved */
> + build_append_int_noprefix(table_data, 0, 4); /* Flags */
> + /* Number of supervisor mode Interrupt Identities */
> + build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
> + /* Number of guest mode Interrupt Identities */
> + build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2);
> + /* Guest Index Bits */
> + build_append_int_noprefix(table_data, guest_index_bits, 1);
> + /* Hart Index Bits */
> + build_append_int_noprefix(table_data, hart_index_bits, 1);
> + /* Group Index Bits */
> + build_append_int_noprefix(table_data, group_index_bits, 1);
> + /* Group Index Shift */
> + build_append_int_noprefix(table_data, group_index_shift, 1);
> + }
> +
> acpi_table_end(linker, &table);
> }
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 06/12] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT
2023-10-19 13:26 ` [PATCH v3 06/12] hw/riscv/virt-acpi-build.c: Add APLIC " Sunil V L
2023-10-23 12:46 ` Andrew Jones
@ 2023-10-24 0:10 ` Alistair Francis
1 sibling, 0 replies; 30+ messages in thread
From: Alistair Francis @ 2023-10-24 0:10 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-riscv, qemu-arm, qemu-devel, Shannon Zhao, Peter Maydell,
Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Philippe Mathieu-Daudé, Gerd Hoffmann, Paolo Bonzini,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anup Patel, Andrew Jones,
Atish Kumar Patra, Haibo Xu
On Thu, Oct 19, 2023 at 11:29 PM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> Add APLIC structures for each socket in the MADT when system is configured
> with APLIC as the external wired interrupt controller.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/virt-acpi-build.c | 36 ++++++++++++++++++++++++++++++++++--
> 1 file changed, 34 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 7f1a370e54..8fa358d034 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -277,9 +277,9 @@ static void build_madt(GArray *table_data,
> MachineClass *mc = MACHINE_GET_CLASS(s);
> MachineState *ms = MACHINE(s);
> const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
> - uint64_t imsic_socket_addr, imsic_addr;
> + uint64_t imsic_socket_addr, imsic_addr, aplic_addr;
> + uint32_t imsic_size, gsi_base;
> uint8_t guest_index_bits;
> - uint32_t imsic_size;
> uint32_t local_cpu_id, socket_id;
> uint8_t hart_index_bits, group_index_bits, group_index_shift;
> uint16_t imsic_max_hart_per_socket = 0;
> @@ -341,6 +341,38 @@ static void build_madt(GArray *table_data,
> build_append_int_noprefix(table_data, group_index_shift, 1);
> }
>
> + if (s->aia_type != VIRT_AIA_TYPE_NONE) {
> + /* APLICs */
> + for (socket = 0; socket < riscv_socket_count(ms); socket++) {
> + aplic_addr = s->memmap[VIRT_APLIC_S].base +
> + s->memmap[VIRT_APLIC_S].size * socket;
> + gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket;
> + build_append_int_noprefix(table_data, 0x1A, 1); /* Type */
> + build_append_int_noprefix(table_data, 36, 1); /* Length */
> + build_append_int_noprefix(table_data, 1, 1); /* Version */
> + build_append_int_noprefix(table_data, socket, 1); /* APLIC ID */
> + build_append_int_noprefix(table_data, 0, 4); /* Flags */
> + build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */
> + /* Number of IDCs */
> + if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
> + build_append_int_noprefix(table_data,
> + s->soc[socket].num_harts,
> + 2);
> + } else {
> + build_append_int_noprefix(table_data, 0, 2);
> + }
> + /* Total External Interrupt Sources Supported */
> + build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_SOURCES, 2);
> + /* Global System Interrupt Base */
> + build_append_int_noprefix(table_data, gsi_base, 4);
> + /* APLIC Address */
> + build_append_int_noprefix(table_data, aplic_addr, 8);
> + /* APLIC size */
> + build_append_int_noprefix(table_data,
> + s->memmap[VIRT_APLIC_S].size, 4);
> + }
> + }
> +
> acpi_table_end(linker, &table);
> }
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 07/12] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT
2023-10-19 13:26 ` [PATCH v3 07/12] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT Sunil V L
2023-10-23 12:51 ` Andrew Jones
2023-10-23 13:17 ` Andrew Jones
@ 2023-10-24 0:12 ` Alistair Francis
2 siblings, 0 replies; 30+ messages in thread
From: Alistair Francis @ 2023-10-24 0:12 UTC (permalink / raw)
To: Sunil V L
Cc: qemu-riscv, qemu-arm, qemu-devel, Shannon Zhao, Peter Maydell,
Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Philippe Mathieu-Daudé, Gerd Hoffmann, Paolo Bonzini,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anup Patel, Andrew Jones,
Atish Kumar Patra, Haibo Xu
On Fri, Oct 20, 2023 at 12:59 AM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the
> block size for those extensions need to be communicated via CMO node in
> RHCT. Add CMO node in RHCT if any of those CMO extensions are detected.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/virt-acpi-build.c | 64 +++++++++++++++++++++++++++++++++-----
> 1 file changed, 56 insertions(+), 8 deletions(-)
>
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 8fa358d034..bf47eef792 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -147,6 +147,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
> * 5.2.36 RISC-V Hart Capabilities Table (RHCT)
> * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16
> * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
> + * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view
> */
> static void build_rhct(GArray *table_data,
> BIOSLinker *linker,
> @@ -156,8 +157,8 @@ static void build_rhct(GArray *table_data,
> MachineState *ms = MACHINE(s);
> const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
> size_t len, aligned_len;
> - uint32_t isa_offset, num_rhct_nodes;
> - RISCVCPU *cpu;
> + uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
> + RISCVCPU *cpu = &s->soc[0].harts[0];
> char *isa;
>
> AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
> @@ -173,6 +174,9 @@ static void build_rhct(GArray *table_data,
>
> /* ISA + N hart info */
> num_rhct_nodes = 1 + ms->smp.cpus;
> + if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
> + num_rhct_nodes++;
> + }
>
> /* Number of RHCT nodes*/
> build_append_int_noprefix(table_data, num_rhct_nodes, 4);
> @@ -184,7 +188,6 @@ static void build_rhct(GArray *table_data,
> isa_offset = table_data->len - table.table_offset;
> build_append_int_noprefix(table_data, 0, 2); /* Type 0 */
>
> - cpu = &s->soc[0].harts[0];
> isa = riscv_isa_string(cpu);
> len = 8 + strlen(isa) + 1;
> aligned_len = (len % 2) ? (len + 1) : len;
> @@ -200,14 +203,59 @@ static void build_rhct(GArray *table_data,
> build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */
> }
>
> + /* CMO node */
> + if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
> + cmo_offset = table_data->len - table.table_offset;
> + build_append_int_noprefix(table_data, 1, 2); /* Type */
> + build_append_int_noprefix(table_data, 10, 2); /* Total Length */
> + build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
> + build_append_int_noprefix(table_data, 0, 1); /* Reserved */
> +
> + /* CBOM block size */
> + if (cpu->cfg.cbom_blocksize) {
> + build_append_int_noprefix(table_data,
> + __builtin_ctz(cpu->cfg.cbom_blocksize),
> + 1);
> + } else {
> + build_append_int_noprefix(table_data, 0, 1);
> + }
> +
> + /* CBOP block size */
> + build_append_int_noprefix(table_data, 0, 1);
> +
> + /* CBOZ block size */
> + if (cpu->cfg.cboz_blocksize) {
> + build_append_int_noprefix(table_data,
> + __builtin_ctz(cpu->cfg.cboz_blocksize),
> + 1);
> + } else {
> + build_append_int_noprefix(table_data, 0, 1);
> + }
> + }
> +
> /* Hart Info Node */
> for (int i = 0; i < arch_ids->len; i++) {
> + len = 16;
> + int num_offsets = 1;
> build_append_int_noprefix(table_data, 0xFFFF, 2); /* Type */
> - build_append_int_noprefix(table_data, 16, 2); /* Length */
> - build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
> - build_append_int_noprefix(table_data, 1, 2); /* Number of offsets */
> - build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
> - build_append_int_noprefix(table_data, isa_offset, 4); /* Offsets[0] */
> +
> + /* Length */
> + if (cmo_offset) {
> + len += 4;
> + num_offsets++;
> + }
> +
> + build_append_int_noprefix(table_data, len, 2);
> + build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
> + /* Number of offsets */
> + build_append_int_noprefix(table_data, num_offsets, 2);
> + build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
> +
> + /* Offsets */
> + build_append_int_noprefix(table_data, isa_offset, 4);
> + if (cmo_offset) {
> + build_append_int_noprefix(table_data, cmo_offset, 4);
> + }
> }
>
> acpi_table_end(linker, &table);
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v3 02/12] hw/arm/virt-acpi-build.c: Migrate virtio creation to common location
2023-10-23 12:28 ` Andrew Jones
@ 2023-10-25 20:03 ` Sunil V L
0 siblings, 0 replies; 30+ messages in thread
From: Sunil V L @ 2023-10-25 20:03 UTC (permalink / raw)
To: Andrew Jones
Cc: qemu-riscv, qemu-arm, qemu-devel, Shannon Zhao, Peter Maydell,
Michael S . Tsirkin, Igor Mammedov, Ani Sinha,
Philippe Mathieu-Daudé, Gerd Hoffmann, Paolo Bonzini,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Anup Patel,
Atish Kumar Patra, Haibo Xu
On Mon, Oct 23, 2023 at 02:28:22PM +0200, Andrew Jones wrote:
> On Thu, Oct 19, 2023 at 06:56:38PM +0530, Sunil V L wrote:
> > RISC-V also needs to create the virtio in DSDT in the same way as ARM. So,
> > instead of duplicating the code, move this function to the device specific
> > file which is common across architectures.
> >
> > Suggested-by: Igor Mammedov <imammedo@redhat.com>
> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > hw/arm/virt-acpi-build.c | 29 ++---------------------------
> > hw/virtio/meson.build | 1 +
> > hw/virtio/virtio-acpi.c | 28 ++++++++++++++++++++++++++++
> > include/hw/virtio/virtio-acpi.h | 11 +++++++++++
>
> Need SPDX for these new files as well.
>
> > 4 files changed, 42 insertions(+), 27 deletions(-)
> > create mode 100644 hw/virtio/virtio-acpi.c
> > create mode 100644 include/hw/virtio/virtio-acpi.h
> >
> > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> > index b8e725d953..69733f6663 100644
> > --- a/hw/arm/virt-acpi-build.c
> > +++ b/hw/arm/virt-acpi-build.c
> > @@ -58,6 +58,7 @@
> > #include "migration/vmstate.h"
> > #include "hw/acpi/ghes.h"
> > #include "hw/acpi/viot.h"
> > +#include "hw/virtio/virtio-acpi.h"
> >
> > #define ARM_SPI_BASE 32
> >
> > @@ -118,32 +119,6 @@ static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
> > aml_append(scope, dev);
> > }
> >
> > -static void acpi_dsdt_add_virtio(Aml *scope,
> > - const MemMapEntry *virtio_mmio_memmap,
> > - uint32_t mmio_irq, int num)
> > -{
> > - hwaddr base = virtio_mmio_memmap->base;
> > - hwaddr size = virtio_mmio_memmap->size;
> > - int i;
> > -
> > - for (i = 0; i < num; i++) {
> > - uint32_t irq = mmio_irq + i;
> > - Aml *dev = aml_device("VR%02u", i);
> > - aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
> > - aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> > - aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> > -
> > - Aml *crs = aml_resource_template();
> > - aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
> > - aml_append(crs,
> > - aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
> > - AML_EXCLUSIVE, &irq, 1));
> > - aml_append(dev, aml_name_decl("_CRS", crs));
> > - aml_append(scope, dev);
> > - base += size;
> > - }
> > -}
> > -
> > static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
> > uint32_t irq, VirtMachineState *vms)
> > {
> > @@ -850,7 +825,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
> > acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
> > }
> > fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
> > - acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
> > + virtio_acpi_dsdt_add(scope, &memmap[VIRT_MMIO],
> > (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
> > acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
> > if (vms->acpi_dev) {
> > diff --git a/hw/virtio/meson.build b/hw/virtio/meson.build
> > index c0055a7832..9d62097a21 100644
> > --- a/hw/virtio/meson.build
> > +++ b/hw/virtio/meson.build
> > @@ -79,3 +79,4 @@ system_ss.add(when: 'CONFIG_ALL', if_true: files('virtio-stub.c'))
> > system_ss.add(files('virtio-hmp-cmds.c'))
> >
> > specific_ss.add_all(when: 'CONFIG_VIRTIO', if_true: specific_virtio_ss)
> > +system_ss.add(when: 'CONFIG_ACPI', if_true: files('virtio-acpi.c'))
> > diff --git a/hw/virtio/virtio-acpi.c b/hw/virtio/virtio-acpi.c
> > new file mode 100644
> > index 0000000000..977499defd
> > --- /dev/null
> > +++ b/hw/virtio/virtio-acpi.c
> > @@ -0,0 +1,28 @@
> > +#include "hw/virtio/virtio-acpi.h"
> > +#include "hw/acpi/aml-build.h"
> > +
> > +void virtio_acpi_dsdt_add(Aml *scope,
> > + const MemMapEntry *virtio_mmio_memmap,
> > + uint32_t mmio_irq, int num)
> > +{
> > + hwaddr base = virtio_mmio_memmap->base;
> > + hwaddr size = virtio_mmio_memmap->size;
> > + int i;
> > +
> > + for (i = 0; i < num; i++) {
> > + uint32_t irq = mmio_irq + i;
> > + Aml *dev = aml_device("VR%02u", i);
> > + aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
> > + aml_append(dev, aml_name_decl("_UID", aml_int(i)));
> > + aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
> > +
> > + Aml *crs = aml_resource_template();
> > + aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
> > + aml_append(crs,
> > + aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
> > + AML_EXCLUSIVE, &irq, 1));
> > + aml_append(dev, aml_name_decl("_CRS", crs));
> > + aml_append(scope, dev);
> > + base += size;
> > + }
> > +}
> > diff --git a/include/hw/virtio/virtio-acpi.h b/include/hw/virtio/virtio-acpi.h
> > new file mode 100644
> > index 0000000000..b8687b1b42
> > --- /dev/null
> > +++ b/include/hw/virtio/virtio-acpi.h
> > @@ -0,0 +1,11 @@
> > +#ifndef VIRTIO_ACPI_H
> > +#define VIRTIO_ACPI_H
> > +
> > +#include "qemu/osdep.h"
> > +#include "exec/hwaddr.h"
> > +
> > +void virtio_acpi_dsdt_add(Aml *scope, const MemMapEntry *virtio_mmio_memmap,
> > + uint32_t mmio_irq, int num);
> > +
> > +#endif
> > +
> > --
> > 2.34.1
> >
>
> Shouldn't we also try to apply this to microvm which has nearly the same
> code?
>
Okay. Let me add a patch to update microvm code also. Let me send next
revision with your and Daniel's comments addressed.
Thanks!
Sunil
> Otherwise,
>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2023-10-25 20:04 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-10-19 13:26 [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
2023-10-19 13:26 ` [PATCH v3 01/12] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location Sunil V L
2023-10-23 12:22 ` Andrew Jones
2023-10-19 13:26 ` [PATCH v3 02/12] hw/arm/virt-acpi-build.c: Migrate virtio " Sunil V L
2023-10-20 11:42 ` Daniel Henrique Barboza
2023-10-23 12:28 ` Andrew Jones
2023-10-25 20:03 ` Sunil V L
2023-10-19 13:26 ` [PATCH v3 03/12] hw/riscv: virt: Make few IMSIC macros and functions public Sunil V L
2023-10-23 12:31 ` Andrew Jones
2023-10-19 13:26 ` [PATCH v3 04/12] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC Sunil V L
2023-10-24 0:07 ` Alistair Francis
2023-10-19 13:26 ` [PATCH v3 05/12] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT Sunil V L
2023-10-23 12:42 ` Andrew Jones
2023-10-24 0:10 ` Alistair Francis
2023-10-19 13:26 ` [PATCH v3 06/12] hw/riscv/virt-acpi-build.c: Add APLIC " Sunil V L
2023-10-23 12:46 ` Andrew Jones
2023-10-24 0:10 ` Alistair Francis
2023-10-19 13:26 ` [PATCH v3 07/12] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT Sunil V L
2023-10-23 12:51 ` Andrew Jones
2023-10-23 13:17 ` Andrew Jones
2023-10-24 0:12 ` Alistair Francis
2023-10-19 13:26 ` [PATCH v3 08/12] hw/riscv/virt-acpi-build.c: Add MMU node " Sunil V L
2023-10-23 13:15 ` Andrew Jones
2023-10-19 13:26 ` [PATCH v3 09/12] hw/pci-host/gpex: Define properties for MMIO ranges Sunil V L
2023-10-19 13:26 ` [PATCH v3 10/12] hw/riscv/virt: Update GPEX MMIO related properties Sunil V L
2023-10-20 11:47 ` Daniel Henrique Barboza
2023-10-19 13:26 ` [PATCH v3 11/12] hw/riscv/virt-acpi-build.c: Add IO controllers and devices Sunil V L
2023-10-19 13:26 ` [PATCH v3 12/12] hw/riscv/virt-acpi-build.c: Add PLIC in MADT Sunil V L
2023-10-20 11:49 ` Daniel Henrique Barboza
2023-10-23 13:22 ` Andrew Jones
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