From: Andrew Jones <ajones@ventanamicro.com>
To: Sunil V L <sunilvl@ventanamicro.com>
Cc: qemu-riscv@nongnu.org, qemu-arm@nongnu.org,
qemu-devel@nongnu.org, "Shannon Zhao" <shannon.zhaosl@gmail.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Igor Mammedov" <imammedo@redhat.com>,
"Ani Sinha" <anisinha@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Gerd Hoffmann" <kraxel@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Weiwei Li" <liweiwei@iscas.ac.cn>,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Anup Patel" <apatel@ventanamicro.com>,
"Atish Kumar Patra" <atishp@rivosinc.com>,
"Haibo Xu" <haibo1.xu@intel.com>
Subject: Re: [PATCH v3 07/12] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT
Date: Mon, 23 Oct 2023 15:17:22 +0200 [thread overview]
Message-ID: <20231023-c3b85e7af47edaaba7eedd6e@orel> (raw)
In-Reply-To: <20231019132648.23703-8-sunilvl@ventanamicro.com>
On Thu, Oct 19, 2023 at 06:56:43PM +0530, Sunil V L wrote:
> When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the
> block size for those extensions need to be communicated via CMO node in
> RHCT. Add CMO node in RHCT if any of those CMO extensions are detected.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> hw/riscv/virt-acpi-build.c | 64 +++++++++++++++++++++++++++++++++-----
> 1 file changed, 56 insertions(+), 8 deletions(-)
>
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 8fa358d034..bf47eef792 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -147,6 +147,7 @@ static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)
> * 5.2.36 RISC-V Hart Capabilities Table (RHCT)
> * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16
> * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view
> + * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view
> */
> static void build_rhct(GArray *table_data,
> BIOSLinker *linker,
> @@ -156,8 +157,8 @@ static void build_rhct(GArray *table_data,
> MachineState *ms = MACHINE(s);
> const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);
> size_t len, aligned_len;
> - uint32_t isa_offset, num_rhct_nodes;
> - RISCVCPU *cpu;
> + uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0;
> + RISCVCPU *cpu = &s->soc[0].harts[0];
> char *isa;
>
> AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,
> @@ -173,6 +174,9 @@ static void build_rhct(GArray *table_data,
>
> /* ISA + N hart info */
> num_rhct_nodes = 1 + ms->smp.cpus;
> + if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
> + num_rhct_nodes++;
> + }
>
> /* Number of RHCT nodes*/
> build_append_int_noprefix(table_data, num_rhct_nodes, 4);
> @@ -184,7 +188,6 @@ static void build_rhct(GArray *table_data,
> isa_offset = table_data->len - table.table_offset;
> build_append_int_noprefix(table_data, 0, 2); /* Type 0 */
>
> - cpu = &s->soc[0].harts[0];
> isa = riscv_isa_string(cpu);
> len = 8 + strlen(isa) + 1;
> aligned_len = (len % 2) ? (len + 1) : len;
> @@ -200,14 +203,59 @@ static void build_rhct(GArray *table_data,
> build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */
> }
>
> + /* CMO node */
> + if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) {
> + cmo_offset = table_data->len - table.table_offset;
> + build_append_int_noprefix(table_data, 1, 2); /* Type */
> + build_append_int_noprefix(table_data, 10, 2); /* Total Length */
Comment should be "Length"
> + build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
> + build_append_int_noprefix(table_data, 0, 1); /* Reserved */
> +
> + /* CBOM block size */
> + if (cpu->cfg.cbom_blocksize) {
> + build_append_int_noprefix(table_data,
> + __builtin_ctz(cpu->cfg.cbom_blocksize),
> + 1);
> + } else {
> + build_append_int_noprefix(table_data, 0, 1);
> + }
> +
> + /* CBOP block size */
> + build_append_int_noprefix(table_data, 0, 1);
> +
> + /* CBOZ block size */
> + if (cpu->cfg.cboz_blocksize) {
> + build_append_int_noprefix(table_data,
> + __builtin_ctz(cpu->cfg.cboz_blocksize),
> + 1);
> + } else {
> + build_append_int_noprefix(table_data, 0, 1);
> + }
> + }
> +
> /* Hart Info Node */
> for (int i = 0; i < arch_ids->len; i++) {
> + len = 16;
> + int num_offsets = 1;
> build_append_int_noprefix(table_data, 0xFFFF, 2); /* Type */
> - build_append_int_noprefix(table_data, 16, 2); /* Length */
> - build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
> - build_append_int_noprefix(table_data, 1, 2); /* Number of offsets */
> - build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
> - build_append_int_noprefix(table_data, isa_offset, 4); /* Offsets[0] */
> +
> + /* Length */
> + if (cmo_offset) {
> + len += 4;
> + num_offsets++;
> + }
> +
> + build_append_int_noprefix(table_data, len, 2);
Missing "Length" comment
> + build_append_int_noprefix(table_data, 0x1, 2); /* Revision */
> + /* Number of offsets */
> + build_append_int_noprefix(table_data, num_offsets, 2);
> + build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
> +
> + /* Offsets */
> + build_append_int_noprefix(table_data, isa_offset, 4);
> + if (cmo_offset) {
> + build_append_int_noprefix(table_data, cmo_offset, 4);
> + }
> }
>
> acpi_table_end(linker, &table);
> --
> 2.34.1
>
Thanks,
drew
next prev parent reply other threads:[~2023-10-23 13:18 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-19 13:26 [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Sunil V L
2023-10-19 13:26 ` [PATCH v3 01/12] hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location Sunil V L
2023-10-23 12:22 ` Andrew Jones
2023-10-19 13:26 ` [PATCH v3 02/12] hw/arm/virt-acpi-build.c: Migrate virtio " Sunil V L
2023-10-20 11:42 ` Daniel Henrique Barboza
2023-10-23 12:28 ` Andrew Jones
2023-10-25 20:03 ` Sunil V L
2023-10-19 13:26 ` [PATCH v3 03/12] hw/riscv: virt: Make few IMSIC macros and functions public Sunil V L
2023-10-23 12:31 ` Andrew Jones
2023-10-19 13:26 ` [PATCH v3 04/12] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC Sunil V L
2023-10-24 0:07 ` Alistair Francis
2023-10-19 13:26 ` [PATCH v3 05/12] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT Sunil V L
2023-10-23 12:42 ` Andrew Jones
2023-10-24 0:10 ` Alistair Francis
2023-10-19 13:26 ` [PATCH v3 06/12] hw/riscv/virt-acpi-build.c: Add APLIC " Sunil V L
2023-10-23 12:46 ` Andrew Jones
2023-10-24 0:10 ` Alistair Francis
2023-10-19 13:26 ` [PATCH v3 07/12] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT Sunil V L
2023-10-23 12:51 ` Andrew Jones
2023-10-23 13:17 ` Andrew Jones [this message]
2023-10-24 0:12 ` Alistair Francis
2023-10-19 13:26 ` [PATCH v3 08/12] hw/riscv/virt-acpi-build.c: Add MMU node " Sunil V L
2023-10-23 13:15 ` Andrew Jones
2023-10-19 13:26 ` [PATCH v3 09/12] hw/pci-host/gpex: Define properties for MMIO ranges Sunil V L
2023-10-19 13:26 ` [PATCH v3 10/12] hw/riscv/virt: Update GPEX MMIO related properties Sunil V L
2023-10-20 11:47 ` Daniel Henrique Barboza
2023-10-19 13:26 ` [PATCH v3 11/12] hw/riscv/virt-acpi-build.c: Add IO controllers and devices Sunil V L
2023-10-19 13:26 ` [PATCH v3 12/12] hw/riscv/virt-acpi-build.c: Add PLIC in MADT Sunil V L
2023-10-20 11:49 ` Daniel Henrique Barboza
2023-10-23 13:22 ` Andrew Jones
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