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From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>, <linux-cxl@vger.kernel.org>,
	Michael Tsirkin <mst@redhat.com>,
	Michael Tokarev <mjt@tls.msk.ru>
Cc: linuxarm@huawei.com, "Fan Ni" <fan.ni@samsung.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v5 0/5] hw/cxl: Line length reduction and related
Date: Mon, 23 Oct 2023 15:02:05 +0100	[thread overview]
Message-ID: <20231023140210.3089-1-Jonathan.Cameron@huawei.com> (raw)

v5:
 - As _Static_assert() is a declaration it cannot follow a label (until
   C23).
   Upshot of that is to compile in clang (possibly older GCC) we need
   to add {} to case statements that start with QEMU_BUILD_BUG_ON()
 - Add patch to handle another QEMU_BUILD_BUG_ON() case by dropping the
   unnecessary check.

Suggested-by: Michael S. Tsirkin <mst@redhat.com>

Michael observed that the CXL code regularly went above the 80 character
recommendation and in many cases this was not necessary for readability.

This series is focused on tidying this up for the existing code so that
we can maintain the preferred formatting going forwards.

Jonathan Cameron (5):
  hw/cxl: Use a switch to explicitly check size in caps_reg_read()
  hw/cxl: Use switch statements for read and write of cachemem registers
  hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt
  hw/cxl: Line length reductions
  hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue.

 include/hw/cxl/cxl_component.h |   3 +-
 include/hw/cxl/cxl_device.h    |   5 +-
 include/hw/cxl/cxl_events.h    |   3 +-
 include/hw/cxl/cxl_pci.h       |   6 +-
 hw/cxl/cxl-cdat.c              |   3 +-
 hw/cxl/cxl-component-utils.c   | 130 ++++++++++++++++++++-------------
 hw/cxl/cxl-device-utils.c      |  11 ++-
 hw/cxl/cxl-events.c            |   9 ++-
 hw/cxl/cxl-mailbox-utils.c     |  21 ++++--
 hw/mem/cxl_type3.c             |  31 +++++---
 hw/mem/cxl_type3_stubs.c       |   5 +-
 hw/pci-bridge/cxl_downstream.c |   2 +-
 hw/pci-bridge/cxl_root_port.c  |   2 +-
 hw/pci-bridge/cxl_upstream.c   |   2 +-
 14 files changed, 144 insertions(+), 89 deletions(-)

-- 
2.39.2



WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: <qemu-devel@nongnu.org>, <linux-cxl@vger.kernel.org>,
	Michael Tsirkin <mst@redhat.com>,
	Michael Tokarev <mjt@tls.msk.ru>
Cc: linuxarm@huawei.com, "Fan Ni" <fan.ni@samsung.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v5 0/5] hw/cxl: Line length reduction and related
Date: Mon, 23 Oct 2023 15:02:05 +0100	[thread overview]
Message-ID: <20231023140210.3089-1-Jonathan.Cameron@huawei.com> (raw)
Message-ID: <20231023140205.4pDzfmdBSCLbrsmDmNwKnwqv_mz-fU9QHNMA5Jv478E@z> (raw)

v5:
 - As _Static_assert() is a declaration it cannot follow a label (until
   C23).
   Upshot of that is to compile in clang (possibly older GCC) we need
   to add {} to case statements that start with QEMU_BUILD_BUG_ON()
 - Add patch to handle another QEMU_BUILD_BUG_ON() case by dropping the
   unnecessary check.

Suggested-by: Michael S. Tsirkin <mst@redhat.com>

Michael observed that the CXL code regularly went above the 80 character
recommendation and in many cases this was not necessary for readability.

This series is focused on tidying this up for the existing code so that
we can maintain the preferred formatting going forwards.

Jonathan Cameron (5):
  hw/cxl: Use a switch to explicitly check size in caps_reg_read()
  hw/cxl: Use switch statements for read and write of cachemem registers
  hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt
  hw/cxl: Line length reductions
  hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue.

 include/hw/cxl/cxl_component.h |   3 +-
 include/hw/cxl/cxl_device.h    |   5 +-
 include/hw/cxl/cxl_events.h    |   3 +-
 include/hw/cxl/cxl_pci.h       |   6 +-
 hw/cxl/cxl-cdat.c              |   3 +-
 hw/cxl/cxl-component-utils.c   | 130 ++++++++++++++++++++-------------
 hw/cxl/cxl-device-utils.c      |  11 ++-
 hw/cxl/cxl-events.c            |   9 ++-
 hw/cxl/cxl-mailbox-utils.c     |  21 ++++--
 hw/mem/cxl_type3.c             |  31 +++++---
 hw/mem/cxl_type3_stubs.c       |   5 +-
 hw/pci-bridge/cxl_downstream.c |   2 +-
 hw/pci-bridge/cxl_root_port.c  |   2 +-
 hw/pci-bridge/cxl_upstream.c   |   2 +-
 14 files changed, 144 insertions(+), 89 deletions(-)

-- 
2.39.2



             reply	other threads:[~2023-10-23 14:03 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-23 14:02 Jonathan Cameron via [this message]
2023-10-23 14:02 ` [PATCH v5 0/5] hw/cxl: Line length reduction and related Jonathan Cameron
2023-10-23 14:02 ` [PATCH v5 1/5] hw/cxl: Use a switch to explicitly check size in caps_reg_read() Jonathan Cameron via
2023-10-23 14:02   ` Jonathan Cameron
2023-10-23 14:02 ` [PATCH v5 2/5] hw/cxl: Use switch statements for read and write of cachemem registers Jonathan Cameron via
2023-10-23 14:02   ` Jonathan Cameron
2023-10-23 14:02 ` [PATCH v5 3/5] hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt Jonathan Cameron via
2023-10-23 14:02   ` Jonathan Cameron
2023-10-23 14:02 ` [PATCH v5 4/5] hw/cxl: Line length reductions Jonathan Cameron via
2023-10-23 14:02   ` Jonathan Cameron
2023-10-23 14:02 ` [PATCH v5 5/5] hw/cxl: Fix a QEMU_BUILD_BUG_ON() in switch statement scope issue Jonathan Cameron via
2023-10-23 14:02   ` Jonathan Cameron

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