From: Jonathan Cameron via <qemu-devel@nongnu.org> To: <qemu-devel@nongnu.org>, <linux-cxl@vger.kernel.org>, Michael Tsirkin <mst@redhat.com>, Michael Tokarev <mjt@tls.msk.ru> Cc: linuxarm@huawei.com, "Fan Ni" <fan.ni@samsung.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, "Gregory Price" <gregory.price@memverge.com>, "Davidlohr Bueso" <dave@stgolabs.net>, "Klaus Jensen" <its@irrelevant.dk>, "Corey Minyard" <cminyard@mvista.com> Subject: [PATCH v2 15/17] hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions Date: Mon, 23 Oct 2023 17:08:04 +0100 [thread overview] Message-ID: <20231023160806.13206-16-Jonathan.Cameron@huawei.com> (raw) In-Reply-To: <20231023160806.13206-1-Jonathan.Cameron@huawei.com> From: Gregory Price <gourry.memverge@gmail.com> Call CXL_TYPE3 once at top of function to avoid multiple invocations. Signed-off-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> --- hw/mem/cxl_type3.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index cc8220592f..a766c64575 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -888,17 +888,18 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *ct3d, MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { + CXLType3Dev *ct3d = CXL_TYPE3(d); uint64_t dpa_offset = 0; AddressSpace *as = NULL; int res; - res = cxl_type3_hpa_to_as_and_dpa(CXL_TYPE3(d), host_addr, size, + res = cxl_type3_hpa_to_as_and_dpa(ct3d, host_addr, size, &as, &dpa_offset); if (res) { return MEMTX_ERROR; } - if (sanitize_running(&CXL_TYPE3(d)->cci)) { + if (sanitize_running(&ct3d->cci)) { qemu_guest_getrandom_nofail(data, size); return MEMTX_OK; } @@ -909,17 +910,18 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data, MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data, unsigned size, MemTxAttrs attrs) { + CXLType3Dev *ct3d = CXL_TYPE3(d); uint64_t dpa_offset = 0; AddressSpace *as = NULL; int res; - res = cxl_type3_hpa_to_as_and_dpa(CXL_TYPE3(d), host_addr, size, + res = cxl_type3_hpa_to_as_and_dpa(ct3d, host_addr, size, &as, &dpa_offset); if (res) { return MEMTX_ERROR; } - if (sanitize_running(&CXL_TYPE3(d)->cci)) { + if (sanitize_running(&ct3d->cci)) { return MEMTX_OK; } -- 2.39.2
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron <Jonathan.Cameron@huawei.com> To: <qemu-devel@nongnu.org>, <linux-cxl@vger.kernel.org>, Michael Tsirkin <mst@redhat.com>, Michael Tokarev <mjt@tls.msk.ru> Cc: linuxarm@huawei.com, "Fan Ni" <fan.ni@samsung.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, "Gregory Price" <gregory.price@memverge.com>, "Davidlohr Bueso" <dave@stgolabs.net>, "Klaus Jensen" <its@irrelevant.dk>, "Corey Minyard" <cminyard@mvista.com> Subject: [PATCH v2 15/17] hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions Date: Mon, 23 Oct 2023 17:08:04 +0100 [thread overview] Message-ID: <20231023160806.13206-16-Jonathan.Cameron@huawei.com> (raw) Message-ID: <20231023160804.pPnbPho0qyBP61vapTy-PxwWIQEzIxWqXjCoHT38qrs@z> (raw) In-Reply-To: <20231023160806.13206-1-Jonathan.Cameron@huawei.com> From: Gregory Price <gourry.memverge@gmail.com> Call CXL_TYPE3 once at top of function to avoid multiple invocations. Signed-off-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> --- hw/mem/cxl_type3.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index cc8220592f..a766c64575 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -888,17 +888,18 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *ct3d, MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { + CXLType3Dev *ct3d = CXL_TYPE3(d); uint64_t dpa_offset = 0; AddressSpace *as = NULL; int res; - res = cxl_type3_hpa_to_as_and_dpa(CXL_TYPE3(d), host_addr, size, + res = cxl_type3_hpa_to_as_and_dpa(ct3d, host_addr, size, &as, &dpa_offset); if (res) { return MEMTX_ERROR; } - if (sanitize_running(&CXL_TYPE3(d)->cci)) { + if (sanitize_running(&ct3d->cci)) { qemu_guest_getrandom_nofail(data, size); return MEMTX_OK; } @@ -909,17 +910,18 @@ MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data, MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data, unsigned size, MemTxAttrs attrs) { + CXLType3Dev *ct3d = CXL_TYPE3(d); uint64_t dpa_offset = 0; AddressSpace *as = NULL; int res; - res = cxl_type3_hpa_to_as_and_dpa(CXL_TYPE3(d), host_addr, size, + res = cxl_type3_hpa_to_as_and_dpa(ct3d, host_addr, size, &as, &dpa_offset); if (res) { return MEMTX_ERROR; } - if (sanitize_running(&CXL_TYPE3(d)->cci)) { + if (sanitize_running(&ct3d->cci)) { return MEMTX_OK; } -- 2.39.2
next prev parent reply other threads:[~2023-10-23 16:17 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-10-23 16:07 [PATCH v2 00/17] QEMU: CXL mailbox rework and features (Part 1) Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 01/17] hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 02/17] hw/cxl/mbox: Split mailbox command payload into separate input and output Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-24 16:52 ` fan 2023-10-23 16:07 ` [PATCH v2 03/17] hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-24 17:02 ` fan 2023-10-23 16:07 ` [PATCH v2 04/17] hw/cxl/mbox: Generalize the CCI command processing Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 05/17] hw/pci-bridge/cxl_upstream: Move defintion of device to header Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 06/17] hw/cxl: Add a switch mailbox CCI function Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 07/17] hw/cxl/mbox: Add Information and Status / Identify command Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 08/17] hw/cxl/mbox: Add Physical Switch " Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 09/17] hw/pci-bridge/cxl_downstream: Set default link width and link speed Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 10/17] hw/cxl: Implement Physical Ports status retrieval Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:08 ` [PATCH v2 11/17] hw/cxl/mbox: Add support for background operations Jonathan Cameron via 2023-10-23 16:08 ` Jonathan Cameron 2023-10-23 16:08 ` [PATCH v2 12/17] hw/cxl/mbox: Wire up interrupts for background completion Jonathan Cameron via 2023-10-23 16:08 ` Jonathan Cameron 2023-10-23 16:08 ` [PATCH v2 13/17] hw/cxl: Add support for device sanitation Jonathan Cameron via 2023-10-23 16:08 ` Jonathan Cameron 2023-11-13 23:13 ` Hyeonggon Yoo 2023-10-23 16:08 ` [PATCH v2 14/17] hw/cxl/mbox: Add Get Background Operation Status Command Jonathan Cameron via 2023-10-23 16:08 ` Jonathan Cameron 2023-10-23 16:08 ` Jonathan Cameron via [this message] 2023-10-23 16:08 ` [PATCH v2 15/17] hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions Jonathan Cameron 2023-10-23 16:08 ` [PATCH v2 16/17] hw/cxl: Add dummy security state get Jonathan Cameron via 2023-10-23 16:08 ` Jonathan Cameron 2023-10-23 16:08 ` [PATCH v2 17/17] hw/cxl: Add tunneled command support to mailbox for switch cci Jonathan Cameron via 2023-10-23 16:08 ` Jonathan Cameron 2023-11-07 10:08 ` [PATCH v2 00/17] QEMU: CXL mailbox rework and features (Part 1) Michael S. Tsirkin
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