From: Jonathan Cameron via <qemu-devel@nongnu.org> To: <qemu-devel@nongnu.org>, <linux-cxl@vger.kernel.org>, Michael Tsirkin <mst@redhat.com>, Michael Tokarev <mjt@tls.msk.ru> Cc: linuxarm@huawei.com, "Fan Ni" <fan.ni@samsung.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, "Gregory Price" <gregory.price@memverge.com>, "Davidlohr Bueso" <dave@stgolabs.net>, "Klaus Jensen" <its@irrelevant.dk>, "Corey Minyard" <cminyard@mvista.com> Subject: [PATCH v2 05/17] hw/pci-bridge/cxl_upstream: Move defintion of device to header. Date: Mon, 23 Oct 2023 17:07:54 +0100 [thread overview] Message-ID: <20231023160806.13206-6-Jonathan.Cameron@huawei.com> (raw) In-Reply-To: <20231023160806.13206-1-Jonathan.Cameron@huawei.com> To avoid repetition of switch upstream port specific data in the CXLDeviceState structure it will be necessary to access the switch USP specific data from mailbox callbacks. Hence move it to cxl_device.h so it is no longer an opaque structure. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> --- include/hw/pci-bridge/cxl_upstream_port.h | 18 ++++++++++++++++++ hw/pci-bridge/cxl_upstream.c | 11 +---------- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/include/hw/pci-bridge/cxl_upstream_port.h b/include/hw/pci-bridge/cxl_upstream_port.h new file mode 100644 index 0000000000..b02aa8f659 --- /dev/null +++ b/include/hw/pci-bridge/cxl_upstream_port.h @@ -0,0 +1,18 @@ + +#ifndef CXL_USP_H +#define CXL_USP_H +#include "hw/pci/pcie.h" +#include "hw/pci/pcie_port.h" +#include "hw/cxl/cxl.h" + +typedef struct CXLUpstreamPort { + /*< private >*/ + PCIEPort parent_obj; + + /*< public >*/ + CXLComponentState cxl_cstate; + DOECap doe_cdat; + uint64_t sn; +} CXLUpstreamPort; + +#endif /* CXL_SUP_H */ diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index b81bb5fec9..36737189c6 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -14,6 +14,7 @@ #include "hw/pci/msi.h" #include "hw/pci/pcie.h" #include "hw/pci/pcie_port.h" +#include "hw/pci-bridge/cxl_upstream_port.h" /* * Null value of all Fs suggested by IEEE RA guidelines for use of * EU, OUI and CID @@ -30,16 +31,6 @@ #define CXL_UPSTREAM_PORT_DVSEC_OFFSET \ (CXL_UPSTREAM_PORT_SN_OFFSET + PCI_EXT_CAP_DSN_SIZEOF) -typedef struct CXLUpstreamPort { - /*< private >*/ - PCIEPort parent_obj; - - /*< public >*/ - CXLComponentState cxl_cstate; - DOECap doe_cdat; - uint64_t sn; -} CXLUpstreamPort; - CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp) { return &usp->cxl_cstate; -- 2.39.2
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron <Jonathan.Cameron@huawei.com> To: <qemu-devel@nongnu.org>, <linux-cxl@vger.kernel.org>, Michael Tsirkin <mst@redhat.com>, Michael Tokarev <mjt@tls.msk.ru> Cc: linuxarm@huawei.com, "Fan Ni" <fan.ni@samsung.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, "Gregory Price" <gregory.price@memverge.com>, "Davidlohr Bueso" <dave@stgolabs.net>, "Klaus Jensen" <its@irrelevant.dk>, "Corey Minyard" <cminyard@mvista.com> Subject: [PATCH v2 05/17] hw/pci-bridge/cxl_upstream: Move defintion of device to header. Date: Mon, 23 Oct 2023 17:07:54 +0100 [thread overview] Message-ID: <20231023160806.13206-6-Jonathan.Cameron@huawei.com> (raw) Message-ID: <20231023160754.nnTVMUlIOmw7yNzU1XroBmkan0cWx58uVqC-stNjkXw@z> (raw) In-Reply-To: <20231023160806.13206-1-Jonathan.Cameron@huawei.com> To avoid repetition of switch upstream port specific data in the CXLDeviceState structure it will be necessary to access the switch USP specific data from mailbox callbacks. Hence move it to cxl_device.h so it is no longer an opaque structure. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> --- include/hw/pci-bridge/cxl_upstream_port.h | 18 ++++++++++++++++++ hw/pci-bridge/cxl_upstream.c | 11 +---------- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/include/hw/pci-bridge/cxl_upstream_port.h b/include/hw/pci-bridge/cxl_upstream_port.h new file mode 100644 index 0000000000..b02aa8f659 --- /dev/null +++ b/include/hw/pci-bridge/cxl_upstream_port.h @@ -0,0 +1,18 @@ + +#ifndef CXL_USP_H +#define CXL_USP_H +#include "hw/pci/pcie.h" +#include "hw/pci/pcie_port.h" +#include "hw/cxl/cxl.h" + +typedef struct CXLUpstreamPort { + /*< private >*/ + PCIEPort parent_obj; + + /*< public >*/ + CXLComponentState cxl_cstate; + DOECap doe_cdat; + uint64_t sn; +} CXLUpstreamPort; + +#endif /* CXL_SUP_H */ diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index b81bb5fec9..36737189c6 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -14,6 +14,7 @@ #include "hw/pci/msi.h" #include "hw/pci/pcie.h" #include "hw/pci/pcie_port.h" +#include "hw/pci-bridge/cxl_upstream_port.h" /* * Null value of all Fs suggested by IEEE RA guidelines for use of * EU, OUI and CID @@ -30,16 +31,6 @@ #define CXL_UPSTREAM_PORT_DVSEC_OFFSET \ (CXL_UPSTREAM_PORT_SN_OFFSET + PCI_EXT_CAP_DSN_SIZEOF) -typedef struct CXLUpstreamPort { - /*< private >*/ - PCIEPort parent_obj; - - /*< public >*/ - CXLComponentState cxl_cstate; - DOECap doe_cdat; - uint64_t sn; -} CXLUpstreamPort; - CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp) { return &usp->cxl_cstate; -- 2.39.2
next prev parent reply other threads:[~2023-10-23 16:12 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-10-23 16:07 [PATCH v2 00/17] QEMU: CXL mailbox rework and features (Part 1) Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 01/17] hw/cxl/mbox: Pull the payload out of struct cxl_cmd and make instances constant Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 02/17] hw/cxl/mbox: Split mailbox command payload into separate input and output Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-24 16:52 ` fan 2023-10-23 16:07 ` [PATCH v2 03/17] hw/cxl/mbox: Pull the CCI definition out of the CXLDeviceState Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-24 17:02 ` fan 2023-10-23 16:07 ` [PATCH v2 04/17] hw/cxl/mbox: Generalize the CCI command processing Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` Jonathan Cameron via [this message] 2023-10-23 16:07 ` [PATCH v2 05/17] hw/pci-bridge/cxl_upstream: Move defintion of device to header Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 06/17] hw/cxl: Add a switch mailbox CCI function Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 07/17] hw/cxl/mbox: Add Information and Status / Identify command Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 08/17] hw/cxl/mbox: Add Physical Switch " Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 09/17] hw/pci-bridge/cxl_downstream: Set default link width and link speed Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:07 ` [PATCH v2 10/17] hw/cxl: Implement Physical Ports status retrieval Jonathan Cameron via 2023-10-23 16:07 ` Jonathan Cameron 2023-10-23 16:08 ` [PATCH v2 11/17] hw/cxl/mbox: Add support for background operations Jonathan Cameron via 2023-10-23 16:08 ` Jonathan Cameron 2023-10-23 16:08 ` [PATCH v2 12/17] hw/cxl/mbox: Wire up interrupts for background completion Jonathan Cameron via 2023-10-23 16:08 ` Jonathan Cameron 2023-10-23 16:08 ` [PATCH v2 13/17] hw/cxl: Add support for device sanitation Jonathan Cameron via 2023-10-23 16:08 ` Jonathan Cameron 2023-11-13 23:13 ` Hyeonggon Yoo 2023-10-23 16:08 ` [PATCH v2 14/17] hw/cxl/mbox: Add Get Background Operation Status Command Jonathan Cameron via 2023-10-23 16:08 ` Jonathan Cameron 2023-10-23 16:08 ` [PATCH v2 15/17] hw/cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions Jonathan Cameron via 2023-10-23 16:08 ` Jonathan Cameron 2023-10-23 16:08 ` [PATCH v2 16/17] hw/cxl: Add dummy security state get Jonathan Cameron via 2023-10-23 16:08 ` Jonathan Cameron 2023-10-23 16:08 ` [PATCH v2 17/17] hw/cxl: Add tunneled command support to mailbox for switch cci Jonathan Cameron via 2023-10-23 16:08 ` Jonathan Cameron 2023-11-07 10:08 ` [PATCH v2 00/17] QEMU: CXL mailbox rework and features (Part 1) Michael S. Tsirkin
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