From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
qemu-ppc@nongnu.org, "Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>
Subject: [PATCH 3/9] target/mips: Use tcg_gen_extract_i32
Date: Mon, 23 Oct 2023 18:09:38 +0200 [thread overview]
Message-ID: <20231023160944.10692-4-philmd@linaro.org> (raw)
In-Reply-To: <20231023160944.10692-1-philmd@linaro.org>
Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/translate.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 13e43fa3b6..2586d9c85a 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1269,8 +1269,7 @@ static inline void gen_load_srsgpr(int from, int to)
TCGv_ptr addr = tcg_temp_new_ptr();
tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl));
- tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
- tcg_gen_andi_i32(t2, t2, 0xf);
+ tcg_gen_extract_i32(t2, t2, CP0SRSCtl_PSS, 4);
tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
tcg_gen_ext_i32_ptr(addr, t2);
tcg_gen_add_ptr(addr, tcg_env, addr);
@@ -1289,8 +1288,7 @@ static inline void gen_store_srsgpr(int from, int to)
gen_load_gpr(t0, from);
tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl));
- tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
- tcg_gen_andi_i32(t2, t2, 0xf);
+ tcg_gen_extract_i32(t2, t2, CP0SRSCtl_PSS, 4);
tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
tcg_gen_ext_i32_ptr(addr, t2);
tcg_gen_add_ptr(addr, tcg_env, addr);
@@ -8981,13 +8979,11 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
tcg_gen_extu_i32_tl(bcond, t0);
goto likely;
case OPC_BC1T:
- tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
- tcg_gen_andi_i32(t0, t0, 1);
+ tcg_gen_extract_i32(t0, fpu_fcr31, get_fp_bit(cc), 1);
tcg_gen_extu_i32_tl(bcond, t0);
goto not_likely;
case OPC_BC1TL:
- tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
- tcg_gen_andi_i32(t0, t0, 1);
+ tcg_gen_extract_i32(t0, fpu_fcr31, get_fp_bit(cc), 1);
tcg_gen_extu_i32_tl(bcond, t0);
likely:
ctx->hflags |= MIPS_HFLAG_BL;
--
2.41.0
next prev parent reply other threads:[~2023-10-23 16:11 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 16:09 [PATCH 0/9] tcg: Use tcg_gen_[s]extract_{i32,i64,tl} Philippe Mathieu-Daudé
2023-10-23 16:09 ` [PATCH 1/9] target/avr: Use tcg_gen_extract_tl Philippe Mathieu-Daudé
2023-10-23 23:32 ` Richard Henderson
2023-10-24 7:21 ` Michael Rolnik
2023-10-23 16:09 ` [PATCH 2/9] target/cris: " Philippe Mathieu-Daudé
2023-10-23 23:36 ` Richard Henderson
2023-10-24 8:44 ` Edgar E. Iglesias
2023-10-23 16:09 ` Philippe Mathieu-Daudé [this message]
2023-10-23 23:39 ` [PATCH 3/9] target/mips: Use tcg_gen_extract_i32 Richard Henderson
2023-10-23 16:09 ` [PATCH 4/9] target/ppc: " Philippe Mathieu-Daudé
2023-10-23 23:40 ` Richard Henderson
2023-10-23 16:09 ` [PATCH 5/9] target/sparc: Use tcg_gen_extract_tl Philippe Mathieu-Daudé
2023-10-23 23:41 ` Richard Henderson
2023-10-23 16:09 ` [PATCH 6/9] target/xtensa: Use tcg_gen_extract_i32 Philippe Mathieu-Daudé
2023-10-23 17:56 ` Max Filippov
2023-10-23 16:09 ` [PATCH 7/9] target/mips: Use tcg_gen_sextract_tl Philippe Mathieu-Daudé
2023-10-24 0:14 ` Richard Henderson
2023-10-24 8:57 ` Philippe Mathieu-Daudé
2023-10-24 16:55 ` Philippe Mathieu-Daudé
2023-10-23 16:09 ` [RFC PATCH 8/9] target/cris: " Philippe Mathieu-Daudé
2023-10-24 0:26 ` Richard Henderson
2023-10-24 8:42 ` Edgar E. Iglesias
2023-10-24 8:53 ` Philippe Mathieu-Daudé
2023-10-24 8:58 ` Philippe Mathieu-Daudé
2023-10-23 16:09 ` [RFC PATCH 9/9] target/ppc: " Philippe Mathieu-Daudé
2023-10-24 1:04 ` Richard Henderson
2023-10-25 7:09 ` Nicholas Piggin
2023-10-25 7:33 ` Philippe Mathieu-Daudé
2023-10-25 20:26 ` Richard Henderson
2023-10-25 7:38 ` Richard Henderson
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