From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL v3 21/38] tcg/ppc: Use tcg_use_softmmu
Date: Mon, 23 Oct 2023 11:13:12 -0700 [thread overview]
Message-ID: <20231023181329.171490-22-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231023181329.171490-1-richard.henderson@linaro.org>
Fix TCG_GUEST_BASE_REG to use 'TCG_REG_R30' instead of '30'.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 284 ++++++++++++++++++++-------------------
1 file changed, 143 insertions(+), 141 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index c31da4da9d..856c3b18f5 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -107,9 +107,7 @@
#define have_isel (cpuinfo & CPUINFO_ISEL)
-#ifndef CONFIG_SOFTMMU
-#define TCG_GUEST_BASE_REG 30
-#endif
+#define TCG_GUEST_BASE_REG TCG_REG_R30
#ifdef CONFIG_DEBUG_TCG
static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
@@ -2317,151 +2315,157 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
s_bits == MO_128);
a_bits = h->aa.align;
-#ifdef CONFIG_SOFTMMU
- int mem_index = get_mmuidx(oi);
- int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
- : offsetof(CPUTLBEntry, addr_write);
- int fast_off = tlb_mask_table_ofs(s, mem_index);
- int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
- int table_off = fast_off + offsetof(CPUTLBDescFast, table);
+ if (tcg_use_softmmu) {
+ int mem_index = get_mmuidx(oi);
+ int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
+ : offsetof(CPUTLBEntry, addr_write);
+ int fast_off = tlb_mask_table_ofs(s, mem_index);
+ int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
+ int table_off = fast_off + offsetof(CPUTLBDescFast, table);
- ldst = new_ldst_label(s);
- ldst->is_ld = is_ld;
- ldst->oi = oi;
- ldst->addrlo_reg = addrlo;
- ldst->addrhi_reg = addrhi;
-
- /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off);
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off);
-
- /* Extract the page index, shifted into place for tlb index. */
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_out_shri32(s, TCG_REG_R0, addrlo,
- s->page_bits - CPU_TLB_ENTRY_BITS);
- } else {
- tcg_out_shri64(s, TCG_REG_R0, addrlo,
- s->page_bits - CPU_TLB_ENTRY_BITS);
- }
- tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0));
-
- /*
- * Load the (low part) TLB comparator into TMP2.
- * For 64-bit host, always load the entire 64-bit slot for simplicity.
- * We will ignore the high bits with tcg_out_cmp(..., addr_type).
- */
- if (TCG_TARGET_REG_BITS == 64) {
- if (cmp_off == 0) {
- tcg_out32(s, LDUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2));
- } else {
- tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2));
- tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off);
- }
- } else if (cmp_off == 0 && !HOST_BIG_ENDIAN) {
- tcg_out32(s, LWZUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2));
- } else {
- tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2));
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1,
- cmp_off + 4 * HOST_BIG_ENDIAN);
- }
-
- /*
- * Load the TLB addend for use on the fast path.
- * Do this asap to minimize any load use delay.
- */
- if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) {
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
- offsetof(CPUTLBEntry, addend));
- }
-
- /* Clear the non-page, non-alignment bits from the address in R0. */
- if (TCG_TARGET_REG_BITS == 32) {
- /*
- * We don't support unaligned accesses on 32-bits.
- * Preserve the bottom bits and thus trigger a comparison
- * failure on unaligned accesses.
- */
- if (a_bits < s_bits) {
- a_bits = s_bits;
- }
- tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
- (32 - a_bits) & 31, 31 - s->page_bits);
- } else {
- TCGReg t = addrlo;
-
- /*
- * If the access is unaligned, we need to make sure we fail if we
- * cross a page boundary. The trick is to add the access size-1
- * to the address before masking the low bits. That will make the
- * address overflow to the next page if we cross a page boundary,
- * which will then force a mismatch of the TLB compare.
- */
- if (a_bits < s_bits) {
- unsigned a_mask = (1 << a_bits) - 1;
- unsigned s_mask = (1 << s_bits) - 1;
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
- t = TCG_REG_R0;
- }
-
- /* Mask the address for the requested alignment. */
- if (addr_type == TCG_TYPE_I32) {
- tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
- (32 - a_bits) & 31, 31 - s->page_bits);
- } else if (a_bits == 0) {
- tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - s->page_bits);
- } else {
- tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
- 64 - s->page_bits, s->page_bits - a_bits);
- tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, s->page_bits, 0);
- }
- }
-
- if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {
- /* Low part comparison into cr7. */
- tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2,
- 0, 7, TCG_TYPE_I32);
-
- /* Load the high part TLB comparator into TMP2. */
- tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1,
- cmp_off + 4 * !HOST_BIG_ENDIAN);
-
- /* Load addend, deferred for this case. */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
- offsetof(CPUTLBEntry, addend));
-
- /* High part comparison into cr6. */
- tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2, 0, 6, TCG_TYPE_I32);
-
- /* Combine comparisons into cr7. */
- tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
- } else {
- /* Full comparison into cr7. */
- tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, addr_type);
- }
-
- /* Load a pointer into the current opcode w/conditional branch-link. */
- ldst->label_ptr[0] = s->code_ptr;
- tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
-
- h->base = TCG_REG_TMP1;
-#else
- if (a_bits) {
ldst = new_ldst_label(s);
ldst->is_ld = is_ld;
ldst->oi = oi;
ldst->addrlo_reg = addrlo;
ldst->addrhi_reg = addrhi;
- /* We are expecting a_bits to max out at 7, much lower than ANDI. */
- tcg_debug_assert(a_bits < 16);
- tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1));
+ /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off);
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off);
+ /* Extract the page index, shifted into place for tlb index. */
+ if (TCG_TARGET_REG_BITS == 32) {
+ tcg_out_shri32(s, TCG_REG_R0, addrlo,
+ s->page_bits - CPU_TLB_ENTRY_BITS);
+ } else {
+ tcg_out_shri64(s, TCG_REG_R0, addrlo,
+ s->page_bits - CPU_TLB_ENTRY_BITS);
+ }
+ tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0));
+
+ /*
+ * Load the (low part) TLB comparator into TMP2.
+ * For 64-bit host, always load the entire 64-bit slot for simplicity.
+ * We will ignore the high bits with tcg_out_cmp(..., addr_type).
+ */
+ if (TCG_TARGET_REG_BITS == 64) {
+ if (cmp_off == 0) {
+ tcg_out32(s, LDUX | TAB(TCG_REG_TMP2,
+ TCG_REG_TMP1, TCG_REG_TMP2));
+ } else {
+ tcg_out32(s, ADD | TAB(TCG_REG_TMP1,
+ TCG_REG_TMP1, TCG_REG_TMP2));
+ tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_TMP2,
+ TCG_REG_TMP1, cmp_off);
+ }
+ } else if (cmp_off == 0 && !HOST_BIG_ENDIAN) {
+ tcg_out32(s, LWZUX | TAB(TCG_REG_TMP2,
+ TCG_REG_TMP1, TCG_REG_TMP2));
+ } else {
+ tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2));
+ tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1,
+ cmp_off + 4 * HOST_BIG_ENDIAN);
+ }
+
+ /*
+ * Load the TLB addend for use on the fast path.
+ * Do this asap to minimize any load use delay.
+ */
+ if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) {
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
+ offsetof(CPUTLBEntry, addend));
+ }
+
+ /* Clear the non-page, non-alignment bits from the address in R0. */
+ if (TCG_TARGET_REG_BITS == 32) {
+ /*
+ * We don't support unaligned accesses on 32-bits.
+ * Preserve the bottom bits and thus trigger a comparison
+ * failure on unaligned accesses.
+ */
+ if (a_bits < s_bits) {
+ a_bits = s_bits;
+ }
+ tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
+ (32 - a_bits) & 31, 31 - s->page_bits);
+ } else {
+ TCGReg t = addrlo;
+
+ /*
+ * If the access is unaligned, we need to make sure we fail if we
+ * cross a page boundary. The trick is to add the access size-1
+ * to the address before masking the low bits. That will make the
+ * address overflow to the next page if we cross a page boundary,
+ * which will then force a mismatch of the TLB compare.
+ */
+ if (a_bits < s_bits) {
+ unsigned a_mask = (1 << a_bits) - 1;
+ unsigned s_mask = (1 << s_bits) - 1;
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
+ t = TCG_REG_R0;
+ }
+
+ /* Mask the address for the requested alignment. */
+ if (addr_type == TCG_TYPE_I32) {
+ tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
+ (32 - a_bits) & 31, 31 - s->page_bits);
+ } else if (a_bits == 0) {
+ tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - s->page_bits);
+ } else {
+ tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
+ 64 - s->page_bits, s->page_bits - a_bits);
+ tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, s->page_bits, 0);
+ }
+ }
+
+ if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {
+ /* Low part comparison into cr7. */
+ tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2,
+ 0, 7, TCG_TYPE_I32);
+
+ /* Load the high part TLB comparator into TMP2. */
+ tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1,
+ cmp_off + 4 * !HOST_BIG_ENDIAN);
+
+ /* Load addend, deferred for this case. */
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
+ offsetof(CPUTLBEntry, addend));
+
+ /* High part comparison into cr6. */
+ tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2,
+ 0, 6, TCG_TYPE_I32);
+
+ /* Combine comparisons into cr7. */
+ tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
+ } else {
+ /* Full comparison into cr7. */
+ tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2,
+ 0, 7, addr_type);
+ }
+
+ /* Load a pointer into the current opcode w/conditional branch-link. */
ldst->label_ptr[0] = s->code_ptr;
- tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK);
- }
+ tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
- h->base = guest_base ? TCG_GUEST_BASE_REG : 0;
-#endif
+ h->base = TCG_REG_TMP1;
+ } else {
+ if (a_bits) {
+ ldst = new_ldst_label(s);
+ ldst->is_ld = is_ld;
+ ldst->oi = oi;
+ ldst->addrlo_reg = addrlo;
+ ldst->addrhi_reg = addrhi;
+
+ /* We are expecting a_bits to max out at 7, much lower than ANDI. */
+ tcg_debug_assert(a_bits < 16);
+ tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1));
+
+ ldst->label_ptr[0] = s->code_ptr;
+ tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK);
+ }
+
+ h->base = guest_base ? TCG_GUEST_BASE_REG : 0;
+ }
if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
/* Zero-extend the guest address for use in the host address. */
@@ -2695,12 +2699,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
}
tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
-#ifndef CONFIG_SOFTMMU
- if (guest_base) {
+ if (!tcg_use_softmmu && guest_base) {
tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
}
-#endif
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
--
2.34.1
next prev parent reply other threads:[~2023-10-23 18:15 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 18:12 [PULL v3 00/38] tcg patch queue Richard Henderson
2023-10-23 18:12 ` [PULL v3 01/38] tcg/ppc: Untabify tcg-target.c.inc Richard Henderson
2023-10-23 18:12 ` [PULL v3 02/38] tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB Richard Henderson
2023-10-23 18:12 ` [PULL v3 03/38] tcg/ppc: Reinterpret tb-relative to TB+4 Richard Henderson
2023-10-23 18:12 ` [PULL v3 04/38] tcg/ppc: Use ADDPCIS in tcg_out_tb_start Richard Henderson
2023-10-23 18:12 ` [PULL v3 05/38] tcg/ppc: Use ADDPCIS in tcg_out_movi_int Richard Henderson
2023-10-23 18:12 ` [PULL v3 06/38] tcg/ppc: Use ADDPCIS for the constant pool Richard Henderson
2023-10-23 18:12 ` [PULL v3 07/38] tcg/ppc: Use ADDPCIS in tcg_out_goto_tb Richard Henderson
2023-10-23 18:12 ` [PULL v3 08/38] tcg/ppc: Use PADDI in tcg_out_movi Richard Henderson
2023-10-23 18:13 ` [PULL v3 09/38] tcg/ppc: Use prefixed instructions in tcg_out_mem_long Richard Henderson
2023-10-23 18:13 ` [PULL v3 10/38] tcg/ppc: Use PLD in tcg_out_movi for constant pool Richard Henderson
2023-10-23 18:13 ` [PULL v3 11/38] tcg/ppc: Use prefixed instructions in tcg_out_dupi_vec Richard Henderson
2023-10-23 18:13 ` [PULL v3 12/38] tcg/ppc: Use PLD in tcg_out_goto_tb Richard Henderson
2023-10-23 18:13 ` [PULL v3 13/38] tcg/ppc: Disable TCG_REG_TB for Power9/Power10 Richard Henderson
2023-10-23 18:13 ` [PULL v3 14/38] tcg: Introduce tcg_use_softmmu Richard Henderson
2023-10-23 18:13 ` [PULL v3 15/38] tcg: Provide guest_base fallback for system mode Richard Henderson
2023-10-23 18:13 ` [PULL v3 16/38] tcg/arm: Use tcg_use_softmmu Richard Henderson
2023-10-23 18:13 ` [PULL v3 17/38] tcg/aarch64: " Richard Henderson
2023-10-23 18:13 ` [PULL v3 18/38] tcg/i386: " Richard Henderson
2023-10-23 18:13 ` [PULL v3 19/38] tcg/loongarch64: " Richard Henderson
2023-10-23 18:13 ` [PULL v3 20/38] tcg/mips: " Richard Henderson
2023-10-23 18:13 ` Richard Henderson [this message]
2023-10-23 18:13 ` [PULL v3 22/38] tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero Richard Henderson
2023-10-23 18:13 ` [PULL v3 23/38] tcg/riscv: Use tcg_use_softmmu Richard Henderson
2023-10-23 18:13 ` [PULL v3 24/38] tcg/s390x: " Richard Henderson
2023-10-23 18:13 ` [PULL v3 25/38] tcg: drop unused tcg_temp_free define Richard Henderson
2023-10-23 18:13 ` [PULL v3 26/38] tcg: Use constant zero when expanding with divu2 Richard Henderson
2023-10-23 18:13 ` [PULL v3 27/38] tcg: Optimize past conditional branches Richard Henderson
2023-10-23 18:13 ` [PULL v3 28/38] tcg: Add tcg_gen_{ld,st}_i128 Richard Henderson
2023-10-23 18:13 ` [PULL v3 29/38] target/i386: Use i128 for 128 and 256-bit loads and stores Richard Henderson
2023-10-23 18:13 ` [PULL v3 30/38] tcg: add negsetcondi Richard Henderson
2023-10-23 18:13 ` [PULL v3 31/38] tcg: Export tcg_gen_ext_{i32,i64,tl} Richard Henderson
2023-10-23 18:13 ` [PULL v3 32/38] tcg: Define MO_TL Richard Henderson
2023-10-23 18:13 ` [PULL v3 33/38] target/arm: Use tcg_gen_ext_i64 Richard Henderson
2023-10-23 18:13 ` [PULL v3 34/38] target/i386: Use tcg_gen_ext_tl Richard Henderson
2023-10-23 18:13 ` [PULL v3 35/38] target/m68k: Use tcg_gen_ext_i32 Richard Henderson
2023-10-23 18:13 ` [PULL v3 36/38] target/rx: " Richard Henderson
2023-10-23 18:13 ` [PULL v3 37/38] target/tricore: Use tcg_gen_*extract_tl Richard Henderson
2023-10-23 18:13 ` [PULL v3 38/38] target/xtensa: Use tcg_gen_sextract_i32 Richard Henderson
2023-10-24 1:15 ` [PULL v3 00/38] tcg patch queue Stefan Hajnoczi
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