From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>
Subject: [PULL v3 30/38] tcg: add negsetcondi
Date: Mon, 23 Oct 2023 11:13:21 -0700 [thread overview]
Message-ID: <20231023181329.171490-31-richard.henderson@linaro.org> (raw)
In-Reply-To: <20231023181329.171490-1-richard.henderson@linaro.org>
From: Paolo Bonzini <pbonzini@redhat.com>
This can be useful to write a shift bit extraction that does not
depend on TARGET_LONG_BITS.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20231019104648.389942-15-pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op-common.h | 4 ++++
include/tcg/tcg-op.h | 2 ++
tcg/tcg-op.c | 12 ++++++++++++
3 files changed, 18 insertions(+)
diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index 56d4e9cb9f..a0bae5df01 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -346,6 +346,8 @@ void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
TCGv_i32 arg1, int32_t arg2);
void tcg_gen_negsetcond_i32(TCGCond cond, TCGv_i32 ret,
TCGv_i32 arg1, TCGv_i32 arg2);
+void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 ret,
+ TCGv_i32 arg1, int32_t arg2);
void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
@@ -544,6 +546,8 @@ void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
TCGv_i64 arg1, int64_t arg2);
void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 ret,
TCGv_i64 arg1, TCGv_i64 arg2);
+void tcg_gen_negsetcondi_i64(TCGCond cond, TCGv_i64 ret,
+ TCGv_i64 arg1, int64_t arg2);
void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 3ead59e459..e81dd7dd9e 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -199,6 +199,7 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)
#define tcg_gen_setcond_tl tcg_gen_setcond_i64
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
#define tcg_gen_negsetcond_tl tcg_gen_negsetcond_i64
+#define tcg_gen_negsetcondi_tl tcg_gen_negsetcondi_i64
#define tcg_gen_mul_tl tcg_gen_mul_i64
#define tcg_gen_muli_tl tcg_gen_muli_i64
#define tcg_gen_div_tl tcg_gen_div_i64
@@ -317,6 +318,7 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)
#define tcg_gen_setcond_tl tcg_gen_setcond_i32
#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
#define tcg_gen_negsetcond_tl tcg_gen_negsetcond_i32
+#define tcg_gen_negsetcondi_tl tcg_gen_negsetcondi_i32
#define tcg_gen_mul_tl tcg_gen_mul_i32
#define tcg_gen_muli_tl tcg_gen_muli_i32
#define tcg_gen_div_tl tcg_gen_div_i32
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index b4dbb2f2ba..828eb9ee46 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -291,6 +291,12 @@ void tcg_gen_negsetcond_i32(TCGCond cond, TCGv_i32 ret,
}
}
+void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 ret,
+ TCGv_i32 arg1, int32_t arg2)
+{
+ tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2));
+}
+
void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
{
if (arg2 == 0) {
@@ -1602,6 +1608,12 @@ void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
}
}
+void tcg_gen_negsetcondi_i64(TCGCond cond, TCGv_i64 ret,
+ TCGv_i64 arg1, int64_t arg2)
+{
+ tcg_gen_negsetcond_i64(cond, ret, arg1, tcg_constant_i64(arg2));
+}
+
void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 ret,
TCGv_i64 arg1, TCGv_i64 arg2)
{
--
2.34.1
next prev parent reply other threads:[~2023-10-23 18:15 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-23 18:12 [PULL v3 00/38] tcg patch queue Richard Henderson
2023-10-23 18:12 ` [PULL v3 01/38] tcg/ppc: Untabify tcg-target.c.inc Richard Henderson
2023-10-23 18:12 ` [PULL v3 02/38] tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB Richard Henderson
2023-10-23 18:12 ` [PULL v3 03/38] tcg/ppc: Reinterpret tb-relative to TB+4 Richard Henderson
2023-10-23 18:12 ` [PULL v3 04/38] tcg/ppc: Use ADDPCIS in tcg_out_tb_start Richard Henderson
2023-10-23 18:12 ` [PULL v3 05/38] tcg/ppc: Use ADDPCIS in tcg_out_movi_int Richard Henderson
2023-10-23 18:12 ` [PULL v3 06/38] tcg/ppc: Use ADDPCIS for the constant pool Richard Henderson
2023-10-23 18:12 ` [PULL v3 07/38] tcg/ppc: Use ADDPCIS in tcg_out_goto_tb Richard Henderson
2023-10-23 18:12 ` [PULL v3 08/38] tcg/ppc: Use PADDI in tcg_out_movi Richard Henderson
2023-10-23 18:13 ` [PULL v3 09/38] tcg/ppc: Use prefixed instructions in tcg_out_mem_long Richard Henderson
2023-10-23 18:13 ` [PULL v3 10/38] tcg/ppc: Use PLD in tcg_out_movi for constant pool Richard Henderson
2023-10-23 18:13 ` [PULL v3 11/38] tcg/ppc: Use prefixed instructions in tcg_out_dupi_vec Richard Henderson
2023-10-23 18:13 ` [PULL v3 12/38] tcg/ppc: Use PLD in tcg_out_goto_tb Richard Henderson
2023-10-23 18:13 ` [PULL v3 13/38] tcg/ppc: Disable TCG_REG_TB for Power9/Power10 Richard Henderson
2023-10-23 18:13 ` [PULL v3 14/38] tcg: Introduce tcg_use_softmmu Richard Henderson
2023-10-23 18:13 ` [PULL v3 15/38] tcg: Provide guest_base fallback for system mode Richard Henderson
2023-10-23 18:13 ` [PULL v3 16/38] tcg/arm: Use tcg_use_softmmu Richard Henderson
2023-10-23 18:13 ` [PULL v3 17/38] tcg/aarch64: " Richard Henderson
2023-10-23 18:13 ` [PULL v3 18/38] tcg/i386: " Richard Henderson
2023-10-23 18:13 ` [PULL v3 19/38] tcg/loongarch64: " Richard Henderson
2023-10-23 18:13 ` [PULL v3 20/38] tcg/mips: " Richard Henderson
2023-10-23 18:13 ` [PULL v3 21/38] tcg/ppc: " Richard Henderson
2023-10-23 18:13 ` [PULL v3 22/38] tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero Richard Henderson
2023-10-23 18:13 ` [PULL v3 23/38] tcg/riscv: Use tcg_use_softmmu Richard Henderson
2023-10-23 18:13 ` [PULL v3 24/38] tcg/s390x: " Richard Henderson
2023-10-23 18:13 ` [PULL v3 25/38] tcg: drop unused tcg_temp_free define Richard Henderson
2023-10-23 18:13 ` [PULL v3 26/38] tcg: Use constant zero when expanding with divu2 Richard Henderson
2023-10-23 18:13 ` [PULL v3 27/38] tcg: Optimize past conditional branches Richard Henderson
2023-10-23 18:13 ` [PULL v3 28/38] tcg: Add tcg_gen_{ld,st}_i128 Richard Henderson
2023-10-23 18:13 ` [PULL v3 29/38] target/i386: Use i128 for 128 and 256-bit loads and stores Richard Henderson
2023-10-23 18:13 ` Richard Henderson [this message]
2023-10-23 18:13 ` [PULL v3 31/38] tcg: Export tcg_gen_ext_{i32,i64,tl} Richard Henderson
2023-10-23 18:13 ` [PULL v3 32/38] tcg: Define MO_TL Richard Henderson
2023-10-23 18:13 ` [PULL v3 33/38] target/arm: Use tcg_gen_ext_i64 Richard Henderson
2023-10-23 18:13 ` [PULL v3 34/38] target/i386: Use tcg_gen_ext_tl Richard Henderson
2023-10-23 18:13 ` [PULL v3 35/38] target/m68k: Use tcg_gen_ext_i32 Richard Henderson
2023-10-23 18:13 ` [PULL v3 36/38] target/rx: " Richard Henderson
2023-10-23 18:13 ` [PULL v3 37/38] target/tricore: Use tcg_gen_*extract_tl Richard Henderson
2023-10-23 18:13 ` [PULL v3 38/38] target/xtensa: Use tcg_gen_sextract_i32 Richard Henderson
2023-10-24 1:15 ` [PULL v3 00/38] tcg patch queue Stefan Hajnoczi
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