From: Zhao Liu <zhao1.liu@linux.intel.com>
To: "Eduardo Habkost" <eduardo@habkost.net>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
Zhenyu Wang <zhenyu.z.wang@intel.com>,
Xiaoyao Li <xiaoyao.li@intel.com>,
Babu Moger <babu.moger@amd.com>,
Yongwei Ma <yongwei.ma@intel.com>, Zhao Liu <zhao1.liu@intel.com>
Subject: [PATCH v5 12/20] i386: Expose module level in CPUID[0x1F]
Date: Tue, 24 Oct 2023 17:03:15 +0800 [thread overview]
Message-ID: <20231024090323.1859210-13-zhao1.liu@linux.intel.com> (raw)
In-Reply-To: <20231024090323.1859210-1-zhao1.liu@linux.intel.com>
From: Zhao Liu <zhao1.liu@intel.com>
Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix
erroneous smp_num_siblings on Intel Hybrid platforms") is able to
handle platforms with Module level enumerated via CPUID.1F.
Expose the module level in CPUID[0x1F] if the machine has more than 1
modules.
(Tested CPU topology in CPUID[0x1F] leaf with various die/cluster
configurations in "-smp".)
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
---
Changes since v3:
* New patch to expose module level in 0x1F.
* Add Tested-by tag from Yongwei.
---
target/i386/cpu.c | 12 +++++++++++-
target/i386/cpu.h | 2 ++
target/i386/kvm/kvm.c | 2 +-
3 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 63c33b77ba74..37566eca7e23 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -277,6 +277,8 @@ static uint32_t num_cpus_by_topo_level(X86CPUTopoInfo *topo_info,
return 1;
case CPU_TOPO_LEVEL_CORE:
return topo_info->threads_per_core;
+ case CPU_TOPO_LEVEL_MODULE:
+ return topo_info->threads_per_core * topo_info->cores_per_module;
case CPU_TOPO_LEVEL_DIE:
return topo_info->threads_per_core * topo_info->cores_per_module *
topo_info->modules_per_die;
@@ -297,6 +299,8 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info,
return 0;
case CPU_TOPO_LEVEL_CORE:
return apicid_core_offset(topo_info);
+ case CPU_TOPO_LEVEL_MODULE:
+ return apicid_module_offset(topo_info);
case CPU_TOPO_LEVEL_DIE:
return apicid_die_offset(topo_info);
case CPU_TOPO_LEVEL_PACKAGE:
@@ -316,6 +320,8 @@ static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level)
return CPUID_1F_ECX_TOPO_LEVEL_SMT;
case CPU_TOPO_LEVEL_CORE:
return CPUID_1F_ECX_TOPO_LEVEL_CORE;
+ case CPU_TOPO_LEVEL_MODULE:
+ return CPUID_1F_ECX_TOPO_LEVEL_MODULE;
case CPU_TOPO_LEVEL_DIE:
return CPUID_1F_ECX_TOPO_LEVEL_DIE;
default:
@@ -347,6 +353,10 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count,
if (env->nr_dies > 1) {
set_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap);
}
+
+ if (env->nr_modules > 1) {
+ set_bit(CPU_TOPO_LEVEL_MODULE, topo_bitmap);
+ }
}
*ecx = count & 0xff;
@@ -6393,7 +6403,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
break;
case 0x1F:
/* V2 Extended Topology Enumeration Leaf */
- if (topo_info.dies_per_pkg < 2) {
+ if (topo_info.modules_per_die < 2 && topo_info.dies_per_pkg < 2) {
*eax = *ebx = *ecx = *edx = 0;
break;
}
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 18577bc0bf6b..37bbf32f6c78 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1018,6 +1018,7 @@ enum CPUTopoLevel {
CPU_TOPO_LEVEL_INVALID,
CPU_TOPO_LEVEL_SMT,
CPU_TOPO_LEVEL_CORE,
+ CPU_TOPO_LEVEL_MODULE,
CPU_TOPO_LEVEL_DIE,
CPU_TOPO_LEVEL_PACKAGE,
CPU_TOPO_LEVEL_MAX,
@@ -1032,6 +1033,7 @@ enum CPUTopoLevel {
#define CPUID_1F_ECX_TOPO_LEVEL_INVALID CPUID_B_ECX_TOPO_LEVEL_INVALID
#define CPUID_1F_ECX_TOPO_LEVEL_SMT CPUID_B_ECX_TOPO_LEVEL_SMT
#define CPUID_1F_ECX_TOPO_LEVEL_CORE CPUID_B_ECX_TOPO_LEVEL_CORE
+#define CPUID_1F_ECX_TOPO_LEVEL_MODULE 3
#define CPUID_1F_ECX_TOPO_LEVEL_DIE 5
/* MSR Feature Bits */
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index e7c054cc160b..bd5a69ac76f3 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -1961,7 +1961,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
break;
}
case 0x1f:
- if (env->nr_dies < 2) {
+ if (env->nr_modules < 2 && env->nr_dies < 2) {
break;
}
/* fallthrough */
--
2.34.1
next prev parent reply other threads:[~2023-10-24 8:56 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-24 9:03 [PATCH v5 00/20] Support smp.clusters for x86 in QEMU Zhao Liu
2023-10-24 9:03 ` [PATCH v5 01/20] i386: Fix comment style in topology.h Zhao Liu
2023-10-24 9:03 ` [PATCH v5 02/20] tests: Rename test-x86-cpuid.c to test-x86-topo.c Zhao Liu
2023-10-24 9:09 ` Thomas Huth
2023-10-25 8:22 ` Zhao Liu
2023-10-24 9:03 ` [PATCH v5 03/20] softmmu: Fix CPUSTATE.nr_cores' calculation Zhao Liu
2023-10-24 9:03 ` [PATCH v5 04/20] hw/cpu: Update the comments of nr_cores and nr_dies Zhao Liu
2023-10-24 9:03 ` [PATCH v5 05/20] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Zhao Liu
2023-10-24 9:03 ` [PATCH v5 06/20] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4] Zhao Liu
2023-10-24 9:03 ` [PATCH v5 07/20] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Zhao Liu
2023-10-24 9:03 ` [PATCH v5 08/20] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Zhao Liu
2023-10-24 9:03 ` [PATCH v5 09/20] i386: Decouple CPUID[0x1F] subleaf with specific topology level Zhao Liu
2023-10-24 9:03 ` [PATCH v5 10/20] i386: Introduce module-level cpu topology to CPUX86State Zhao Liu
2023-10-24 9:03 ` [PATCH v5 11/20] i386: Support modules_per_die in X86CPUTopoInfo Zhao Liu
2023-10-24 9:03 ` Zhao Liu [this message]
2023-10-24 9:03 ` [PATCH v5 13/20] i386: Support module_id in X86CPUTopoIDs Zhao Liu
2023-10-24 9:03 ` [PATCH v5 14/20] i386/cpu: Introduce cluster-id to X86CPU Zhao Liu
2023-10-24 9:03 ` [PATCH v5 15/20] tests: Add test case of APIC ID for module level parsing Zhao Liu
2023-10-24 9:03 ` [PATCH v5 16/20] hw/i386/pc: Support smp.clusters for x86 PC machine Zhao Liu
2023-10-24 9:03 ` [PATCH v5 17/20] i386: Add cache topology info in CPUCacheInfo Zhao Liu
2023-10-24 9:03 ` [PATCH v5 18/20] i386: Use CPUCacheInfo.share_level to encode CPUID[4] Zhao Liu
2023-10-24 9:03 ` [PATCH v5 19/20] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2023-10-24 9:03 ` [PATCH v5 20/20] i386: Use CPUCacheInfo.share_level to encode " Zhao Liu
2023-10-25 10:04 ` [PATCH v5 00/20] Support smp.clusters for x86 in QEMU Philippe Mathieu-Daudé
2023-10-25 13:42 ` Zhao Liu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231024090323.1859210-13-zhao1.liu@linux.intel.com \
--to=zhao1.liu@linux.intel.com \
--cc=babu.moger@amd.com \
--cc=eduardo@habkost.net \
--cc=kvm@vger.kernel.org \
--cc=marcel.apfelbaum@gmail.com \
--cc=mst@redhat.com \
--cc=mtosatti@redhat.com \
--cc=pbonzini@redhat.com \
--cc=philmd@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=wangyanan55@huawei.com \
--cc=xiaoyao.li@intel.com \
--cc=yongwei.ma@intel.com \
--cc=zhao1.liu@intel.com \
--cc=zhenyu.z.wang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).