From: Zhao Liu <zhao1.liu@linux.intel.com>
To: "Eduardo Habkost" <eduardo@habkost.net>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
Zhenyu Wang <zhenyu.z.wang@intel.com>,
Xiaoyao Li <xiaoyao.li@intel.com>,
Babu Moger <babu.moger@amd.com>,
Yongwei Ma <yongwei.ma@intel.com>, Zhao Liu <zhao1.liu@intel.com>
Subject: [PATCH v5 20/20] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14]
Date: Tue, 24 Oct 2023 17:03:23 +0800 [thread overview]
Message-ID: <20231024090323.1859210-21-zhao1.liu@linux.intel.com> (raw)
In-Reply-To: <20231024090323.1859210-1-zhao1.liu@linux.intel.com>
From: Zhao Liu <zhao1.liu@intel.com>
CPUID[0x8000001D].EAX[bits 25:14] NumSharingCache: number of logical
processors sharing cache.
The number of logical processors sharing this cache is
NumSharingCache + 1.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[0x8000001D].EAX[bits 25:14].
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Babu Moger <babu.moger@amd.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
---
Changes since v3:
* Explain what "CPUID[0x8000001D].EAX[bits 25:14]" means in the commit
message. (Babu)
Changes since v1:
* Use cache->share_level as the parameter in
max_processor_ids_for_cache().
---
target/i386/cpu.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 226c5be6ea95..7672c94946ec 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -483,20 +483,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
- uint32_t num_sharing_cache;
assert(cache->size == cache->line_size * cache->associativity *
cache->partitions * cache->sets);
*eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
(cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
-
- /* L3 is shared among multiple cores */
- if (cache->level == 3) {
- num_sharing_cache = 1 << apicid_die_offset(topo_info);
- } else {
- num_sharing_cache = 1 << apicid_core_offset(topo_info);
- }
- *eax |= (num_sharing_cache - 1) << 14;
+ *eax |= max_processor_ids_for_cache(topo_info, cache->share_level) << 14;
assert(cache->line_size > 0);
assert(cache->partitions > 0);
--
2.34.1
next prev parent reply other threads:[~2023-10-24 8:55 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-24 9:03 [PATCH v5 00/20] Support smp.clusters for x86 in QEMU Zhao Liu
2023-10-24 9:03 ` [PATCH v5 01/20] i386: Fix comment style in topology.h Zhao Liu
2023-10-24 9:03 ` [PATCH v5 02/20] tests: Rename test-x86-cpuid.c to test-x86-topo.c Zhao Liu
2023-10-24 9:09 ` Thomas Huth
2023-10-25 8:22 ` Zhao Liu
2023-10-24 9:03 ` [PATCH v5 03/20] softmmu: Fix CPUSTATE.nr_cores' calculation Zhao Liu
2023-10-24 9:03 ` [PATCH v5 04/20] hw/cpu: Update the comments of nr_cores and nr_dies Zhao Liu
2023-10-24 9:03 ` [PATCH v5 05/20] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Zhao Liu
2023-10-24 9:03 ` [PATCH v5 06/20] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4] Zhao Liu
2023-10-24 9:03 ` [PATCH v5 07/20] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Zhao Liu
2023-10-24 9:03 ` [PATCH v5 08/20] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Zhao Liu
2023-10-24 9:03 ` [PATCH v5 09/20] i386: Decouple CPUID[0x1F] subleaf with specific topology level Zhao Liu
2023-10-24 9:03 ` [PATCH v5 10/20] i386: Introduce module-level cpu topology to CPUX86State Zhao Liu
2023-10-24 9:03 ` [PATCH v5 11/20] i386: Support modules_per_die in X86CPUTopoInfo Zhao Liu
2023-10-24 9:03 ` [PATCH v5 12/20] i386: Expose module level in CPUID[0x1F] Zhao Liu
2023-10-24 9:03 ` [PATCH v5 13/20] i386: Support module_id in X86CPUTopoIDs Zhao Liu
2023-10-24 9:03 ` [PATCH v5 14/20] i386/cpu: Introduce cluster-id to X86CPU Zhao Liu
2023-10-24 9:03 ` [PATCH v5 15/20] tests: Add test case of APIC ID for module level parsing Zhao Liu
2023-10-24 9:03 ` [PATCH v5 16/20] hw/i386/pc: Support smp.clusters for x86 PC machine Zhao Liu
2023-10-24 9:03 ` [PATCH v5 17/20] i386: Add cache topology info in CPUCacheInfo Zhao Liu
2023-10-24 9:03 ` [PATCH v5 18/20] i386: Use CPUCacheInfo.share_level to encode CPUID[4] Zhao Liu
2023-10-24 9:03 ` [PATCH v5 19/20] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2023-10-24 9:03 ` Zhao Liu [this message]
2023-10-25 10:04 ` [PATCH v5 00/20] Support smp.clusters for x86 in QEMU Philippe Mathieu-Daudé
2023-10-25 13:42 ` Zhao Liu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231024090323.1859210-21-zhao1.liu@linux.intel.com \
--to=zhao1.liu@linux.intel.com \
--cc=babu.moger@amd.com \
--cc=eduardo@habkost.net \
--cc=kvm@vger.kernel.org \
--cc=marcel.apfelbaum@gmail.com \
--cc=mst@redhat.com \
--cc=mtosatti@redhat.com \
--cc=pbonzini@redhat.com \
--cc=philmd@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=wangyanan55@huawei.com \
--cc=xiaoyao.li@intel.com \
--cc=yongwei.ma@intel.com \
--cc=zhao1.liu@intel.com \
--cc=zhenyu.z.wang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).