From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH 5/6] target/arm: Move ID_AA64PFR* tests together
Date: Tue, 24 Oct 2023 17:35:09 +0100 [thread overview]
Message-ID: <20231024163510.2972081-6-peter.maydell@linaro.org> (raw)
In-Reply-To: <20231024163510.2972081-1-peter.maydell@linaro.org>
Move all the ID_AA64PFR* feature test functions together.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu-features.h | 86 +++++++++++++++++++--------------------
1 file changed, 43 insertions(+), 43 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index e73120ef974..0ed05b8b19e 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -631,6 +631,49 @@ static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
}
+static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
+}
+
+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
+{
+ int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
+ if (key >= 2) {
+ return true; /* FEAT_CSV2_2 */
+ }
+ if (key == 1) {
+ key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
+ return key >= 2; /* FEAT_CSV2_1p2 */
+ }
+ return false;
+}
+
+static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
+}
+
+static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
+}
+
+static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
+}
+
+static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
+}
+
+static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
+}
+
static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
{
return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
@@ -791,26 +834,6 @@ static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
}
-static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
-{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
-}
-
-static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
-{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
-}
-
-static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
-{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
-}
-
-static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
-{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
-}
-
static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
@@ -829,29 +852,6 @@ static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
}
-static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
-{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
-}
-
-static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
-{
- int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
- if (key >= 2) {
- return true; /* FEAT_CSV2_2 */
- }
- if (key == 1) {
- key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
- return key >= 2; /* FEAT_CSV2_1p2 */
- }
- return false;
-}
-
-static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
-{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
-}
-
static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
--
2.34.1
next prev parent reply other threads:[~2023-10-24 16:37 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-24 16:35 [PATCH 0/6] target/arm: Move feature tests to their own header Peter Maydell
2023-10-24 16:35 ` [PATCH 1/6] target/arm: Move feature test functions " Peter Maydell
2023-10-25 23:34 ` Richard Henderson
2023-10-24 16:35 ` [PATCH 2/6] target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together Peter Maydell
2023-10-25 23:34 ` Richard Henderson
2023-10-24 16:35 ` [PATCH 3/6] target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2 Peter Maydell
2023-10-25 23:35 ` Richard Henderson
2023-10-24 16:35 ` [PATCH 4/6] target/arm: Move ID_AA64ISAR* test functions together Peter Maydell
2023-10-25 23:35 ` Richard Henderson
2023-10-24 16:35 ` Peter Maydell [this message]
2023-10-25 23:36 ` [PATCH 5/6] target/arm: Move ID_AA64PFR* tests together Richard Henderson
2023-10-24 16:35 ` [PATCH 6/6] target/arm: Move ID_AA64DFR* feature " Peter Maydell
2023-10-25 23:36 ` Richard Henderson
2023-10-24 16:50 ` [PATCH 0/6] target/arm: Move feature tests to their own header Philippe Mathieu-Daudé
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